1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMTARGETMACHINE_H
15 #define ARMTARGETMACHINE_H
17 #include "ARMInstrInfo.h"
18 #include "ARMSubtarget.h"
19 #include "llvm/IR/DataLayout.h"
20 #include "llvm/Target/TargetMachine.h"
24 class ARMBaseTargetMachine : public LLVMTargetMachine {
26 ARMSubtarget Subtarget;
28 ARMBaseTargetMachine(const Target &T, StringRef TT,
29 StringRef CPU, StringRef FS,
30 const TargetOptions &Options,
31 Reloc::Model RM, CodeModel::Model CM,
35 const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }
36 ARMSubtarget *getSubtargetImpl() override { return &Subtarget; }
38 /// \brief Register ARM analysis passes with a pass manager.
39 void addAnalysisPasses(PassManagerBase &PM) override;
41 // Pass Pipeline Configuration
42 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
44 bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &MCE) override;
47 /// ARMTargetMachine - ARM target machine.
49 class ARMTargetMachine : public ARMBaseTargetMachine {
50 virtual void anchor();
52 ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
53 const TargetOptions &Options, Reloc::Model RM,
54 CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
57 /// ARMLETargetMachine - ARM little endian target machine.
59 class ARMLETargetMachine : public ARMTargetMachine {
60 void anchor() override;
62 ARMLETargetMachine(const Target &T, StringRef TT,
63 StringRef CPU, StringRef FS, const TargetOptions &Options,
64 Reloc::Model RM, CodeModel::Model CM,
65 CodeGenOpt::Level OL);
68 /// ARMBETargetMachine - ARM big endian target machine.
70 class ARMBETargetMachine : public ARMTargetMachine {
71 void anchor() override;
73 ARMBETargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
74 const TargetOptions &Options, Reloc::Model RM,
75 CodeModel::Model CM, CodeGenOpt::Level OL);
78 /// ThumbTargetMachine - Thumb target machine.
79 /// Due to the way architectures are handled, this represents both
80 /// Thumb-1 and Thumb-2.
82 class ThumbTargetMachine : public ARMBaseTargetMachine {
83 virtual void anchor();
85 ThumbTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
86 const TargetOptions &Options, Reloc::Model RM,
87 CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
90 /// ThumbLETargetMachine - Thumb little endian target machine.
92 class ThumbLETargetMachine : public ThumbTargetMachine {
93 void anchor() override;
95 ThumbLETargetMachine(const Target &T, StringRef TT, StringRef CPU,
96 StringRef FS, const TargetOptions &Options,
97 Reloc::Model RM, CodeModel::Model CM,
98 CodeGenOpt::Level OL);
101 /// ThumbBETargetMachine - Thumb big endian target machine.
103 class ThumbBETargetMachine : public ThumbTargetMachine {
104 void anchor() override;
106 ThumbBETargetMachine(const Target &T, StringRef TT, StringRef CPU,
107 StringRef FS, const TargetOptions &Options,
108 Reloc::Model RM, CodeModel::Model CM,
109 CodeGenOpt::Level OL);
112 } // end namespace llvm