1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMSUBTARGET_H
15 #define ARMSUBTARGET_H
17 #include "MCTargetDesc/ARMMCTargetDesc.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/MC/MCInstrItineraries.h"
20 #include "llvm/Target/TargetSubtargetInfo.h"
23 #define GET_SUBTARGETINFO_HEADER
24 #include "ARMGenSubtargetInfo.inc"
31 class ARMSubtarget : public ARMGenSubtargetInfo {
33 enum ARMProcFamilyEnum {
34 Others, CortexA5, CortexA8, CortexA9, CortexA15, CortexR5, Swift
37 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
38 ARMProcFamilyEnum ARMProcFamily;
40 /// HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6T2Ops, HasV7Ops -
41 /// Specify whether target support specific ARM ISA variants.
49 /// HasVFPv2, HasVFPv3, HasVFPv4, HasNEON - Specify what
50 /// floating point ISAs are supported.
56 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
57 /// specified. Use the method useNEONForSinglePrecisionFP() to
58 /// determine if NEON should actually be used.
59 bool UseNEONForSinglePrecisionFP;
61 /// UseMulOps - True if non-microcoded fused integer multiply-add and
62 /// multiply-subtract instructions should be used.
65 /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
66 /// whether the FP VML[AS] instructions are slow (if so, don't use them).
69 /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
70 /// forwarding to allow mul + mla being issued back to back.
71 bool HasVMLxForwarding;
73 /// SlowFPBrcc - True if floating point compare + branch is slow.
76 /// InThumbMode - True if compiling for Thumb, false for ARM.
79 /// HasThumb2 - True if Thumb2 instructions are supported.
82 /// IsMClass - True if the subtarget belongs to the 'M' profile of CPUs -
83 /// v6m, v7m for example.
86 /// NoARM - True if subtarget does not support ARM mode execution.
89 /// PostRAScheduler - True if using post-register-allocation scheduler.
92 /// IsR9Reserved - True if R9 is a not available as general purpose register.
95 /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
96 /// imms (including global addresses).
99 /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
100 /// must be able to synthesize call stubs for interworking between ARM and
102 bool SupportsTailCall;
104 /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
108 /// HasD16 - True if subtarget is limited to 16 double precision
109 /// FP registers for VFPv3.
112 /// HasHardwareDivide - True if subtarget supports [su]div
113 bool HasHardwareDivide;
115 /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
116 bool HasHardwareDivideInARM;
118 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
120 bool HasT2ExtractPack;
122 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
126 /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
127 /// over 16-bit ones.
130 /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
131 /// that partially update CPSR and add false dependency on the previous
132 /// CPSR setting instruction.
133 bool AvoidCPSRPartialUpdate;
135 /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
136 /// movs with shifter operand (i.e. asr, lsl, lsr).
137 bool AvoidMOVsShifterOperand;
139 /// HasRAS - Some processors perform return stack prediction. CodeGen should
140 /// avoid issue "normal" call instructions to callees which do not return.
143 /// HasMPExtension - True if the subtarget supports Multiprocessing
144 /// extension (ARMv7 only).
147 /// FPOnlySP - If true, the floating point unit only supports single
151 /// If true, the processor supports the Performance Monitor Extensions. These
152 /// include a generic cycle-counter as well as more fine-grained (often
153 /// implementation-specific) events.
156 /// HasTrustZone - if true, processor supports TrustZone security extensions
159 /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
160 /// accesses for some types. For details, see
161 /// ARMTargetLowering::allowsUnalignedMemoryAccesses().
162 bool AllowsUnalignedMem;
164 /// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith
165 /// and such) instructions in Thumb2 code.
168 /// NaCl TRAP instruction is generated instead of the regular TRAP.
171 /// Target machine allowed unsafe FP math (such as use of NEON fp)
174 /// stackAlignment - The minimum alignment known to hold of the stack frame on
175 /// entry to the function and which must be maintained by every function.
176 unsigned stackAlignment;
178 /// CPUString - String name of used CPU.
179 std::string CPUString;
181 /// TargetTriple - What processor and OS we're targeting.
184 /// SchedModel - Processor specific instruction costs.
185 const MCSchedModel *SchedModel;
187 /// Selected instruction itineraries (one entry per itinerary class.)
188 InstrItineraryData InstrItins;
190 /// Options passed via command line that could influence the target
191 const TargetOptions &Options;
200 ARM_ABI_AAPCS // ARM EABI
203 /// This constructor initializes the data members to match that
204 /// of the specified triple.
206 ARMSubtarget(const std::string &TT, const std::string &CPU,
207 const std::string &FS, const TargetOptions &Options);
209 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
210 /// that still makes it profitable to inline the call.
211 unsigned getMaxInlineSizeThreshold() const {
212 // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1.
213 // Change this once Thumb1 ldmia / stmia support is added.
214 return isThumb1Only() ? 0 : 64;
216 /// ParseSubtargetFeatures - Parses features string setting specified
217 /// subtarget options. Definition of function is auto generated by tblgen.
218 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
220 /// \brief Reset the features for the ARM target.
221 virtual void resetSubtargetFeatures(const MachineFunction *MF);
223 void initializeEnvironment();
224 void resetSubtargetFeatures(StringRef CPU, StringRef FS);
226 void computeIssueWidth();
228 bool hasV4TOps() const { return HasV4TOps; }
229 bool hasV5TOps() const { return HasV5TOps; }
230 bool hasV5TEOps() const { return HasV5TEOps; }
231 bool hasV6Ops() const { return HasV6Ops; }
232 bool hasV6T2Ops() const { return HasV6T2Ops; }
233 bool hasV7Ops() const { return HasV7Ops; }
235 bool isCortexA5() const { return ARMProcFamily == CortexA5; }
236 bool isCortexA8() const { return ARMProcFamily == CortexA8; }
237 bool isCortexA9() const { return ARMProcFamily == CortexA9; }
238 bool isCortexA15() const { return ARMProcFamily == CortexA15; }
239 bool isSwift() const { return ARMProcFamily == Swift; }
240 bool isCortexM3() const { return CPUString == "cortex-m3"; }
241 bool isLikeA9() const { return isCortexA9() || isCortexA15(); }
242 bool isCortexR5() const { return ARMProcFamily == CortexR5; }
244 bool hasARMOps() const { return !NoARM; }
246 bool hasVFP2() const { return HasVFPv2; }
247 bool hasVFP3() const { return HasVFPv3; }
248 bool hasVFP4() const { return HasVFPv4; }
249 bool hasNEON() const { return HasNEON; }
250 bool useNEONForSinglePrecisionFP() const {
251 return hasNEON() && UseNEONForSinglePrecisionFP; }
253 bool hasDivide() const { return HasHardwareDivide; }
254 bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
255 bool hasT2ExtractPack() const { return HasT2ExtractPack; }
256 bool hasDataBarrier() const { return HasDataBarrier; }
257 bool useMulOps() const { return UseMulOps; }
258 bool useFPVMLx() const { return !SlowFPVMLx; }
259 bool hasVMLxForwarding() const { return HasVMLxForwarding; }
260 bool isFPBrccSlow() const { return SlowFPBrcc; }
261 bool isFPOnlySP() const { return FPOnlySP; }
262 bool hasPerfMon() const { return HasPerfMon; }
263 bool hasTrustZone() const { return HasTrustZone; }
264 bool prefers32BitThumb() const { return Pref32BitThumb; }
265 bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
266 bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
267 bool hasRAS() const { return HasRAS; }
268 bool hasMPExtension() const { return HasMPExtension; }
269 bool hasThumb2DSP() const { return Thumb2DSP; }
270 bool useNaClTrap() const { return UseNaClTrap; }
272 bool hasFP16() const { return HasFP16; }
273 bool hasD16() const { return HasD16; }
275 const Triple &getTargetTriple() const { return TargetTriple; }
277 bool isTargetIOS() const { return TargetTriple.getOS() == Triple::IOS; }
278 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
279 bool isTargetNaCl() const { return TargetTriple.getOS() == Triple::NaCl; }
280 bool isTargetLinux() const { return TargetTriple.getOS() == Triple::Linux; }
281 bool isTargetELF() const { return !isTargetDarwin(); }
283 bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
284 bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
286 bool isThumb() const { return InThumbMode; }
287 bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
288 bool isThumb2() const { return InThumbMode && HasThumb2; }
289 bool hasThumb2() const { return HasThumb2; }
290 bool isMClass() const { return IsMClass; }
291 bool isARClass() const { return !IsMClass; }
293 bool isR9Reserved() const { return IsR9Reserved; }
295 bool useMovt() const { return UseMovt && hasV6T2Ops(); }
296 bool supportsTailCall() const { return SupportsTailCall; }
298 bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
300 const std::string & getCPUString() const { return CPUString; }
302 unsigned getMispredictionPenalty() const;
304 /// enablePostRAScheduler - True at 'More' optimization.
305 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
306 TargetSubtargetInfo::AntiDepBreakMode& Mode,
307 RegClassVector& CriticalPathRCs) const;
309 /// getInstrItins - Return the instruction itineraies based on subtarget
311 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
313 /// getStackAlignment - Returns the minimum alignment known to hold of the
314 /// stack frame on entry to the function and which must be maintained by every
315 /// function for this subtarget.
316 unsigned getStackAlignment() const { return stackAlignment; }
318 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
320 bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
322 } // End llvm namespace
324 #endif // ARMSUBTARGET_H