1 //=====---- ARMSubtarget.h - Define Subtarget for the ARM -----*- C++ -*--====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMSUBTARGET_H
15 #define ARMSUBTARGET_H
17 #include "MCTargetDesc/ARMMCTargetDesc.h"
18 #include "llvm/Target/TargetSubtargetInfo.h"
19 #include "llvm/MC/MCInstrItineraries.h"
20 #include "llvm/ADT/Triple.h"
23 #define GET_SUBTARGETINFO_HEADER
24 #include "ARMGenSubtargetInfo.inc"
29 class ARMSubtarget : public ARMGenSubtargetInfo {
31 enum ARMProcFamilyEnum {
32 Others, CortexA8, CortexA9
35 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
36 ARMProcFamilyEnum ARMProcFamily;
38 /// HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6T2Ops, HasV7Ops -
39 /// Specify whether target support specific ARM ISA variants.
47 /// HasVFPv2, HasVFPv3, HasNEON - Specify what floating point ISAs are
53 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
54 /// specified. Use the method useNEONForSinglePrecisionFP() to
55 /// determine if NEON should actually be used.
56 bool UseNEONForSinglePrecisionFP;
58 /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
59 /// whether the FP VML[AS] instructions are slow (if so, don't use them).
62 /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
63 /// forwarding to allow mul + mla being issued back to back.
64 bool HasVMLxForwarding;
66 /// SlowFPBrcc - True if floating point compare + branch is slow.
69 /// IsThumb - True if we are in thumb mode, false if in ARM mode.
72 /// HasThumb2 - True if Thumb2 instructions are supported.
75 /// NoARM - True if subtarget does not support ARM mode execution.
78 /// PostRAScheduler - True if using post-register-allocation scheduler.
81 /// IsR9Reserved - True if R9 is a not available as general purpose register.
84 /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
85 /// imms (including global addresses).
88 /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
92 /// HasD16 - True if subtarget is limited to 16 double precision
93 /// FP registers for VFPv3.
96 /// HasHardwareDivide - True if subtarget supports [su]div
97 bool HasHardwareDivide;
99 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
101 bool HasT2ExtractPack;
103 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
107 /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
108 /// over 16-bit ones.
111 /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
112 /// that partially update CPSR and add false dependency on the previous
113 /// CPSR setting instruction.
114 bool AvoidCPSRPartialUpdate;
116 /// HasMPExtension - True if the subtarget supports Multiprocessing
117 /// extension (ARMv7 only).
120 /// FPOnlySP - If true, the floating point unit only supports single
124 /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
125 /// accesses for some types. For details, see
126 /// ARMTargetLowering::allowsUnalignedMemoryAccesses().
127 bool AllowsUnalignedMem;
129 /// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith
130 /// and such) instructions in Thumb2 code.
133 /// stackAlignment - The minimum alignment known to hold of the stack frame on
134 /// entry to the function and which must be maintained by every function.
135 unsigned stackAlignment;
137 /// CPUString - String name of used CPU.
138 std::string CPUString;
140 /// TargetTriple - What processor and OS we're targeting.
143 /// Selected instruction itineraries (one entry per itinerary class.)
144 InstrItineraryData InstrItins;
153 ARM_ABI_AAPCS // ARM EABI
156 /// This constructor initializes the data members to match that
157 /// of the specified triple.
159 ARMSubtarget(const std::string &TT, const std::string &CPU,
160 const std::string &FS);
162 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
163 /// that still makes it profitable to inline the call.
164 unsigned getMaxInlineSizeThreshold() const {
165 // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1.
166 // Change this once Thumb1 ldmia / stmia support is added.
167 return isThumb1Only() ? 0 : 64;
169 /// ParseSubtargetFeatures - Parses features string setting specified
170 /// subtarget options. Definition of function is auto generated by tblgen.
171 void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
173 void computeIssueWidth();
175 bool hasV4TOps() const { return HasV4TOps; }
176 bool hasV5TOps() const { return HasV5TOps; }
177 bool hasV5TEOps() const { return HasV5TEOps; }
178 bool hasV6Ops() const { return HasV6Ops; }
179 bool hasV6T2Ops() const { return HasV6T2Ops; }
180 bool hasV7Ops() const { return HasV7Ops; }
182 bool isCortexA8() const { return ARMProcFamily == CortexA8; }
183 bool isCortexA9() const { return ARMProcFamily == CortexA9; }
185 bool hasARMOps() const { return !NoARM; }
187 bool hasVFP2() const { return HasVFPv2; }
188 bool hasVFP3() const { return HasVFPv3; }
189 bool hasNEON() const { return HasNEON; }
190 bool useNEONForSinglePrecisionFP() const {
191 return hasNEON() && UseNEONForSinglePrecisionFP; }
193 bool hasDivide() const { return HasHardwareDivide; }
194 bool hasT2ExtractPack() const { return HasT2ExtractPack; }
195 bool hasDataBarrier() const { return HasDataBarrier; }
196 bool useFPVMLx() const { return !SlowFPVMLx; }
197 bool hasVMLxForwarding() const { return HasVMLxForwarding; }
198 bool isFPBrccSlow() const { return SlowFPBrcc; }
199 bool isFPOnlySP() const { return FPOnlySP; }
200 bool prefers32BitThumb() const { return Pref32BitThumb; }
201 bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
202 bool hasMPExtension() const { return HasMPExtension; }
203 bool hasThumb2DSP() const { return Thumb2DSP; }
205 bool hasFP16() const { return HasFP16; }
206 bool hasD16() const { return HasD16; }
208 const Triple &getTargetTriple() const { return TargetTriple; }
210 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
211 bool isTargetELF() const { return !isTargetDarwin(); }
213 bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
214 bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
216 bool isThumb() const { return IsThumb; }
217 bool isThumb1Only() const { return IsThumb && !HasThumb2; }
218 bool isThumb2() const { return IsThumb && HasThumb2; }
219 bool hasThumb2() const { return HasThumb2; }
221 bool isR9Reserved() const { return IsR9Reserved; }
223 bool useMovt() const { return UseMovt && hasV6T2Ops(); }
225 bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
227 const std::string & getCPUString() const { return CPUString; }
229 unsigned getMispredictionPenalty() const;
231 /// enablePostRAScheduler - True at 'More' optimization.
232 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
233 TargetSubtargetInfo::AntiDepBreakMode& Mode,
234 RegClassVector& CriticalPathRCs) const;
236 /// getInstrItins - Return the instruction itineraies based on subtarget
238 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
240 /// getStackAlignment - Returns the minimum alignment known to hold of the
241 /// stack frame on entry to the function and which must be maintained by every
242 /// function for this subtarget.
243 unsigned getStackAlignment() const { return stackAlignment; }
245 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
247 bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
249 } // End llvm namespace
251 #endif // ARMSUBTARGET_H