1 //=====---- ARMSubtarget.h - Define Subtarget for the ARM -----*- C++ -*--====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMSUBTARGET_H
15 #define ARMSUBTARGET_H
17 #include "llvm/Target/TargetInstrItineraries.h"
18 #include "llvm/Target/TargetMachine.h"
19 #include "llvm/Target/TargetSubtarget.h"
20 #include "llvm/ADT/Triple.h"
26 class ARMSubtarget : public TargetSubtarget {
29 V4, V4T, V5T, V5TE, V6, V6M, V6T2, V7A, V7M
32 enum ARMProcFamilyEnum {
33 Others, CortexA8, CortexA9
37 None, VFPv2, VFPv3, NEON
45 /// ARMArchVersion - ARM architecture version: V4, V4T (base), V5T, V5TE,
46 /// V6, V6T2, V7A, V7M.
47 ARMArchEnum ARMArchVersion;
49 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
50 ARMProcFamilyEnum ARMProcFamily;
52 /// ARMFPUType - Floating Point Unit type.
55 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
56 /// specified. Use the method useNEONForSinglePrecisionFP() to
57 /// determine if NEON should actually be used.
58 bool UseNEONForSinglePrecisionFP;
60 /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
61 /// whether the FP VML[AS] instructions are slow (if so, don't use them).
64 /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
65 /// forwarding to allow mul + mla being issued back to back.
66 bool HasVMLxForwarding;
68 /// SlowFPBrcc - True if floating point compare + branch is slow.
71 /// IsThumb - True if we are in thumb mode, false if in ARM mode.
74 /// ThumbMode - Indicates supported Thumb version.
75 ThumbTypeEnum ThumbMode;
77 /// NoARM - True if subtarget does not support ARM mode execution.
80 /// PostRAScheduler - True if using post-register-allocation scheduler.
83 /// IsR9Reserved - True if R9 is a not available as general purpose register.
86 /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
87 /// imms (including global addresses).
90 /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
91 /// must be able to synthesize call stubs for interworking between ARM and
93 bool SupportsTailCall;
95 /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
99 /// HasD16 - True if subtarget is limited to 16 double precision
100 /// FP registers for VFPv3.
103 /// HasHardwareDivide - True if subtarget supports [su]div
104 bool HasHardwareDivide;
106 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
108 bool HasT2ExtractPack;
110 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
114 /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
115 /// over 16-bit ones.
118 /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
119 /// that partially update CPSR and add false dependency on the previous
120 /// CPSR setting instruction.
121 bool AvoidCPSRPartialUpdate;
123 /// HasMPExtension - True if the subtarget supports Multiprocessing
124 /// extension (ARMv7 only).
127 /// FPOnlySP - If true, the floating point unit only supports single
131 /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
132 /// accesses for some types. For details, see
133 /// ARMTargetLowering::allowsUnalignedMemoryAccesses().
134 bool AllowsUnalignedMem;
136 /// stackAlignment - The minimum alignment known to hold of the stack frame on
137 /// entry to the function and which must be maintained by every function.
138 unsigned stackAlignment;
140 /// CPUString - String name of used CPU.
141 std::string CPUString;
143 /// TargetTriple - What processor and OS we're targeting.
146 /// Selected instruction itineraries (one entry per itinerary class.)
147 InstrItineraryData InstrItins;
156 ARM_ABI_AAPCS // ARM EABI
159 /// This constructor initializes the data members to match that
160 /// of the specified triple.
162 ARMSubtarget(const std::string &TT, const std::string &FS, bool isThumb);
164 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
165 /// that still makes it profitable to inline the call.
166 unsigned getMaxInlineSizeThreshold() const {
167 // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1.
168 // Change this once Thumb1 ldmia / stmia support is added.
169 return isThumb1Only() ? 0 : 64;
171 /// ParseSubtargetFeatures - Parses features string setting specified
172 /// subtarget options. Definition of function is auto generated by tblgen.
173 std::string ParseSubtargetFeatures(const std::string &FS,
174 const std::string &CPU);
176 void computeIssueWidth();
178 bool hasV4TOps() const { return ARMArchVersion >= V4T; }
179 bool hasV5TOps() const { return ARMArchVersion >= V5T; }
180 bool hasV5TEOps() const { return ARMArchVersion >= V5TE; }
181 bool hasV6Ops() const { return ARMArchVersion >= V6; }
182 bool hasV6T2Ops() const { return ARMArchVersion >= V6T2; }
183 bool hasV7Ops() const { return ARMArchVersion >= V7A; }
185 bool isCortexA8() const { return ARMProcFamily == CortexA8; }
186 bool isCortexA9() const { return ARMProcFamily == CortexA9; }
188 bool hasARMOps() const { return !NoARM; }
190 bool hasVFP2() const { return ARMFPUType >= VFPv2; }
191 bool hasVFP3() const { return ARMFPUType >= VFPv3; }
192 bool hasNEON() const { return ARMFPUType >= NEON; }
193 bool useNEONForSinglePrecisionFP() const {
194 return hasNEON() && UseNEONForSinglePrecisionFP; }
195 bool hasDivide() const { return HasHardwareDivide; }
196 bool hasT2ExtractPack() const { return HasT2ExtractPack; }
197 bool hasDataBarrier() const { return HasDataBarrier; }
198 bool useFPVMLx() const { return !SlowFPVMLx; }
199 bool hasVMLxForwarding() const { return HasVMLxForwarding; }
200 bool isFPBrccSlow() const { return SlowFPBrcc; }
201 bool isFPOnlySP() const { return FPOnlySP; }
202 bool prefers32BitThumb() const { return Pref32BitThumb; }
203 bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
204 bool hasMPExtension() const { return HasMPExtension; }
206 bool hasFP16() const { return HasFP16; }
207 bool hasD16() const { return HasD16; }
209 const Triple &getTargetTriple() const { return TargetTriple; }
211 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
212 bool isTargetELF() const { return !isTargetDarwin(); }
214 bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
215 bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
217 bool isThumb() const { return IsThumb; }
218 bool isThumb1Only() const { return IsThumb && (ThumbMode == Thumb1); }
219 bool isThumb2() const { return IsThumb && (ThumbMode == Thumb2); }
220 bool hasThumb2() const { return ThumbMode >= Thumb2; }
222 bool isR9Reserved() const { return IsR9Reserved; }
224 bool useMovt() const { return UseMovt && hasV6T2Ops(); }
225 bool supportsTailCall() const { return SupportsTailCall; }
227 bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
229 const std::string & getCPUString() const { return CPUString; }
231 unsigned getMispredictionPenalty() const;
233 /// enablePostRAScheduler - True at 'More' optimization.
234 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
235 TargetSubtarget::AntiDepBreakMode& Mode,
236 RegClassVector& CriticalPathRCs) const;
238 /// getInstrItins - Return the instruction itineraies based on subtarget
240 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
242 /// getStackAlignment - Returns the minimum alignment known to hold of the
243 /// stack frame on entry to the function and which must be maintained by every
244 /// function for this subtarget.
245 unsigned getStackAlignment() const { return stackAlignment; }
247 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
249 bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
251 } // End llvm namespace
253 #endif // ARMSUBTARGET_H