1 //=====---- ARMSubtarget.h - Define Subtarget for the ARM -----*- C++ -*--====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMSUBTARGET_H
15 #define ARMSUBTARGET_H
17 #include "llvm/Target/TargetSubtarget.h"
18 #include "llvm/MC/MCInstrItineraries.h"
19 #include "llvm/ADT/Triple.h"
25 class ARMSubtarget : public TargetSubtarget {
28 V4, V4T, V5T, V5TE, V6, V6M, V6T2, V7A, V7M
31 enum ARMProcFamilyEnum {
32 Others, CortexA8, CortexA9
36 None, VFPv2, VFPv3, NEON
44 /// ARMArchVersion - ARM architecture version: V4, V4T (base), V5T, V5TE,
45 /// V6, V6T2, V7A, V7M.
46 ARMArchEnum ARMArchVersion;
48 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
49 ARMProcFamilyEnum ARMProcFamily;
51 /// ARMFPUType - Floating Point Unit type.
54 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
55 /// specified. Use the method useNEONForSinglePrecisionFP() to
56 /// determine if NEON should actually be used.
57 bool UseNEONForSinglePrecisionFP;
59 /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
60 /// whether the FP VML[AS] instructions are slow (if so, don't use them).
63 /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
64 /// forwarding to allow mul + mla being issued back to back.
65 bool HasVMLxForwarding;
67 /// SlowFPBrcc - True if floating point compare + branch is slow.
70 /// IsThumb - True if we are in thumb mode, false if in ARM mode.
73 /// ThumbMode - Indicates supported Thumb version.
74 ThumbTypeEnum ThumbMode;
76 /// NoARM - True if subtarget does not support ARM mode execution.
79 /// PostRAScheduler - True if using post-register-allocation scheduler.
82 /// IsR9Reserved - True if R9 is a not available as general purpose register.
85 /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
86 /// imms (including global addresses).
89 /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
93 /// HasD16 - True if subtarget is limited to 16 double precision
94 /// FP registers for VFPv3.
97 /// HasHardwareDivide - True if subtarget supports [su]div
98 bool HasHardwareDivide;
100 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
102 bool HasT2ExtractPack;
104 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
108 /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
109 /// over 16-bit ones.
112 /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
113 /// that partially update CPSR and add false dependency on the previous
114 /// CPSR setting instruction.
115 bool AvoidCPSRPartialUpdate;
117 /// HasMPExtension - True if the subtarget supports Multiprocessing
118 /// extension (ARMv7 only).
121 /// FPOnlySP - If true, the floating point unit only supports single
125 /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
126 /// accesses for some types. For details, see
127 /// ARMTargetLowering::allowsUnalignedMemoryAccesses().
128 bool AllowsUnalignedMem;
130 /// stackAlignment - The minimum alignment known to hold of the stack frame on
131 /// entry to the function and which must be maintained by every function.
132 unsigned stackAlignment;
134 /// CPUString - String name of used CPU.
135 std::string CPUString;
137 /// TargetTriple - What processor and OS we're targeting.
140 /// Selected instruction itineraries (one entry per itinerary class.)
141 InstrItineraryData InstrItins;
150 ARM_ABI_AAPCS // ARM EABI
153 /// This constructor initializes the data members to match that
154 /// of the specified triple.
156 ARMSubtarget(const std::string &TT, const std::string &CPU,
157 const std::string &FS, bool isThumb);
159 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
160 /// that still makes it profitable to inline the call.
161 unsigned getMaxInlineSizeThreshold() const {
162 // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1.
163 // Change this once Thumb1 ldmia / stmia support is added.
164 return isThumb1Only() ? 0 : 64;
166 /// ParseSubtargetFeatures - Parses features string setting specified
167 /// subtarget options. Definition of function is auto generated by tblgen.
168 void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
170 void computeIssueWidth();
172 bool hasV4TOps() const { return ARMArchVersion >= V4T; }
173 bool hasV5TOps() const { return ARMArchVersion >= V5T; }
174 bool hasV5TEOps() const { return ARMArchVersion >= V5TE; }
175 bool hasV6Ops() const { return ARMArchVersion >= V6; }
176 bool hasV6T2Ops() const { return ARMArchVersion >= V6T2; }
177 bool hasV7Ops() const { return ARMArchVersion >= V7A; }
179 bool isCortexA8() const { return ARMProcFamily == CortexA8; }
180 bool isCortexA9() const { return ARMProcFamily == CortexA9; }
182 bool hasARMOps() const { return !NoARM; }
184 bool hasVFP2() const { return ARMFPUType >= VFPv2; }
185 bool hasVFP3() const { return ARMFPUType >= VFPv3; }
186 bool hasNEON() const { return ARMFPUType >= NEON; }
187 bool useNEONForSinglePrecisionFP() const {
188 return hasNEON() && UseNEONForSinglePrecisionFP; }
189 bool hasDivide() const { return HasHardwareDivide; }
190 bool hasT2ExtractPack() const { return HasT2ExtractPack; }
191 bool hasDataBarrier() const { return HasDataBarrier; }
192 bool useFPVMLx() const { return !SlowFPVMLx; }
193 bool hasVMLxForwarding() const { return HasVMLxForwarding; }
194 bool isFPBrccSlow() const { return SlowFPBrcc; }
195 bool isFPOnlySP() const { return FPOnlySP; }
196 bool prefers32BitThumb() const { return Pref32BitThumb; }
197 bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
198 bool hasMPExtension() const { return HasMPExtension; }
200 bool hasFP16() const { return HasFP16; }
201 bool hasD16() const { return HasD16; }
203 const Triple &getTargetTriple() const { return TargetTriple; }
205 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
206 bool isTargetELF() const { return !isTargetDarwin(); }
208 bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
209 bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
211 bool isThumb() const { return IsThumb; }
212 bool isThumb1Only() const { return IsThumb && (ThumbMode == Thumb1); }
213 bool isThumb2() const { return IsThumb && (ThumbMode == Thumb2); }
214 bool hasThumb2() const { return ThumbMode >= Thumb2; }
216 bool isR9Reserved() const { return IsR9Reserved; }
218 bool useMovt() const { return UseMovt && hasV6T2Ops(); }
220 bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
222 const std::string & getCPUString() const { return CPUString; }
224 unsigned getMispredictionPenalty() const;
226 /// enablePostRAScheduler - True at 'More' optimization.
227 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
228 TargetSubtarget::AntiDepBreakMode& Mode,
229 RegClassVector& CriticalPathRCs) const;
231 /// getInstrItins - Return the instruction itineraies based on subtarget
233 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
235 /// getStackAlignment - Returns the minimum alignment known to hold of the
236 /// stack frame on entry to the function and which must be maintained by every
237 /// function for this subtarget.
238 unsigned getStackAlignment() const { return stackAlignment; }
240 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
242 bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
244 } // End llvm namespace
246 #endif // ARMSUBTARGET_H