1 //===- ARMInstrThumb.td - Thumb support for ARM ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
22 def imm_sr_XFORM: SDNodeXForm<imm, [{
23 unsigned Imm = N->getZExtValue();
24 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), MVT::i32);
26 def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; }
27 def imm_sr : Operand<i32>, PatLeaf<(imm), [{
28 uint64_t Imm = N->getZExtValue();
29 return Imm > 0 && Imm <= 32;
31 let PrintMethod = "printThumbSRImm";
32 let ParserMatchClass = ThumbSRImmAsmOperand;
35 def imm_neg_XFORM : SDNodeXForm<imm, [{
36 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
38 def imm_comp_XFORM : SDNodeXForm<imm, [{
39 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
42 def imm0_7_neg : PatLeaf<(i32 imm), [{
43 return (uint32_t)-N->getZExtValue() < 8;
46 def imm0_255_comp : PatLeaf<(i32 imm), [{
47 return ~((uint32_t)N->getZExtValue()) < 256;
50 def imm8_255 : ImmLeaf<i32, [{
51 return Imm >= 8 && Imm < 256;
53 def imm8_255_neg : PatLeaf<(i32 imm), [{
54 unsigned Val = -N->getZExtValue();
55 return Val >= 8 && Val < 256;
58 // Break imm's up into two pieces: an immediate + a left shift. This uses
59 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
60 // to get the val/shift pieces.
61 def thumb_immshifted : PatLeaf<(imm), [{
62 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
65 def thumb_immshifted_val : SDNodeXForm<imm, [{
66 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
67 return CurDAG->getTargetConstant(V, MVT::i32);
70 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
71 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
72 return CurDAG->getTargetConstant(V, MVT::i32);
75 // ADR instruction labels.
76 def t_adrlabel : Operand<i32> {
77 let EncoderMethod = "getThumbAdrLabelOpValue";
80 // Scaled 4 immediate.
81 def t_imm_s4 : Operand<i32> {
82 let PrintMethod = "printThumbS4ImmOperand";
83 let OperandType = "OPERAND_IMMEDIATE";
86 // Define Thumb specific addressing modes.
88 let OperandType = "OPERAND_PCREL" in {
89 def t_brtarget : Operand<OtherVT> {
90 let EncoderMethod = "getThumbBRTargetOpValue";
91 let DecoderMethod = "DecodeThumbBROperand";
94 def t_bcctarget : Operand<i32> {
95 let EncoderMethod = "getThumbBCCTargetOpValue";
96 let DecoderMethod = "DecodeThumbBCCTargetOperand";
99 def t_cbtarget : Operand<i32> {
100 let EncoderMethod = "getThumbCBTargetOpValue";
101 let DecoderMethod = "DecodeThumbCmpBROperand";
104 def t_bltarget : Operand<i32> {
105 let EncoderMethod = "getThumbBLTargetOpValue";
106 let DecoderMethod = "DecodeThumbBLTargetOperand";
109 def t_blxtarget : Operand<i32> {
110 let EncoderMethod = "getThumbBLXTargetOpValue";
111 let DecoderMethod = "DecodeThumbBLXOffset";
115 // t_addrmode_rr := reg + reg
117 def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; }
118 def t_addrmode_rr : Operand<i32>,
119 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
120 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
121 let PrintMethod = "printThumbAddrModeRROperand";
122 let DecoderMethod = "DecodeThumbAddrModeRR";
123 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
126 // t_addrmode_rrs := reg + reg
128 // We use separate scaled versions because the Select* functions need
129 // to explicitly check for a matching constant and return false here so that
130 // the reg+imm forms will match instead. This is a horrible way to do that,
131 // as it forces tight coupling between the methods, but it's how selectiondag
133 def t_addrmode_rrs1 : Operand<i32>,
134 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
135 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
136 let PrintMethod = "printThumbAddrModeRROperand";
137 let DecoderMethod = "DecodeThumbAddrModeRR";
138 let ParserMatchClass = t_addrmode_rr_asm_operand;
139 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
141 def t_addrmode_rrs2 : Operand<i32>,
142 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
143 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
144 let DecoderMethod = "DecodeThumbAddrModeRR";
145 let PrintMethod = "printThumbAddrModeRROperand";
146 let ParserMatchClass = t_addrmode_rr_asm_operand;
147 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
149 def t_addrmode_rrs4 : Operand<i32>,
150 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
151 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
152 let DecoderMethod = "DecodeThumbAddrModeRR";
153 let PrintMethod = "printThumbAddrModeRROperand";
154 let ParserMatchClass = t_addrmode_rr_asm_operand;
155 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
158 // t_addrmode_is4 := reg + imm5 * 4
160 def t_addrmode_is4_asm_operand : AsmOperandClass { let Name = "MemThumbRIs4"; }
161 def t_addrmode_is4 : Operand<i32>,
162 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
163 let EncoderMethod = "getAddrModeISOpValue";
164 let DecoderMethod = "DecodeThumbAddrModeIS";
165 let PrintMethod = "printThumbAddrModeImm5S4Operand";
166 let ParserMatchClass = t_addrmode_is4_asm_operand;
167 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
170 // t_addrmode_is2 := reg + imm5 * 2
172 def t_addrmode_is2 : Operand<i32>,
173 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
174 let EncoderMethod = "getAddrModeISOpValue";
175 let DecoderMethod = "DecodeThumbAddrModeIS";
176 let PrintMethod = "printThumbAddrModeImm5S2Operand";
177 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
180 // t_addrmode_is1 := reg + imm5
182 def t_addrmode_is1 : Operand<i32>,
183 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
184 let EncoderMethod = "getAddrModeISOpValue";
185 let DecoderMethod = "DecodeThumbAddrModeIS";
186 let PrintMethod = "printThumbAddrModeImm5S1Operand";
187 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
190 // t_addrmode_sp := sp + imm8 * 4
192 def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; }
193 def t_addrmode_sp : Operand<i32>,
194 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
195 let EncoderMethod = "getAddrModeThumbSPOpValue";
196 let DecoderMethod = "DecodeThumbAddrModeSP";
197 let PrintMethod = "printThumbAddrModeSPOperand";
198 let ParserMatchClass = t_addrmode_sp_asm_operand;
199 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
202 // t_addrmode_pc := <label> => pc + imm8 * 4
204 def t_addrmode_pc : Operand<i32> {
205 let EncoderMethod = "getAddrModePCOpValue";
206 let DecoderMethod = "DecodeThumbAddrModePC";
209 //===----------------------------------------------------------------------===//
210 // Miscellaneous Instructions.
213 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
214 // from removing one half of the matched pairs. That breaks PEI, which assumes
215 // these will always be in pairs, and asserts if it finds otherwise. Better way?
216 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
217 def tADJCALLSTACKUP :
218 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
219 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
220 Requires<[IsThumb, IsThumb1Only]>;
222 def tADJCALLSTACKDOWN :
223 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
224 [(ARMcallseq_start imm:$amt)]>,
225 Requires<[IsThumb, IsThumb1Only]>;
228 class T1SystemEncoding<bits<8> opc>
229 : T1Encoding<0b101111> {
230 let Inst{9-8} = 0b11;
234 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "", []>,
235 T1SystemEncoding<0x00>; // A8.6.110
237 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "", []>,
238 T1SystemEncoding<0x10>; // A8.6.410
240 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "", []>,
241 T1SystemEncoding<0x20>; // A8.6.408
243 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "", []>,
244 T1SystemEncoding<0x30>; // A8.6.409
246 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "", []>,
247 T1SystemEncoding<0x40>; // A8.6.157
249 // The imm operand $val can be used by a debugger to store more information
250 // about the breakpoint.
251 def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val",
253 T1Encoding<0b101111> {
254 let Inst{9-8} = 0b10;
260 def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end",
261 []>, T1Encoding<0b101101> {
264 let Inst{9-5} = 0b10010;
267 let Inst{2-0} = 0b000;
270 // Change Processor State is a system instruction -- for disassembly only.
271 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
272 NoItinerary, "cps$imod $iflags",
273 [/* For disassembly only; pattern left blank */]>,
281 let Inst{2-0} = iflags;
282 let DecoderMethod = "DecodeThumbCPS";
285 // For both thumb1 and thumb2.
286 let isNotDuplicable = 1, isCodeGenOnly = 1 in
287 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
288 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
289 T1Special<{0,0,?,?}> {
292 let Inst{6-3} = 0b1111; // Rm = pc
296 // ADD <Rd>, sp, #<imm8>
297 // This is rematerializable, which is particularly useful for taking the
298 // address of locals.
299 let isReMaterializable = 1 in
300 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
301 "add\t$dst, $sp, $rhs", []>,
302 T1Encoding<{1,0,1,0,1,?}> {
306 let Inst{10-8} = dst;
308 let DecoderMethod = "DecodeThumbAddSpecialReg";
311 // ADD sp, sp, #<imm7>
312 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
313 "add\t$dst, $rhs", []>,
314 T1Misc<{0,0,0,0,0,?,?}> {
318 let DecoderMethod = "DecodeThumbAddSPImm";
321 // SUB sp, sp, #<imm7>
322 // FIXME: The encoding and the ASM string don't match up.
323 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
324 "sub\t$dst, $rhs", []>,
325 T1Misc<{0,0,0,0,1,?,?}> {
329 let DecoderMethod = "DecodeThumbAddSPImm";
333 def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
334 "add\t$dst, $rhs", []>,
335 T1Special<{0,0,?,?}> {
336 // A8.6.9 Encoding T1
338 let Inst{7} = dst{3};
339 let Inst{6-3} = 0b1101;
340 let Inst{2-0} = dst{2-0};
341 let DecoderMethod = "DecodeThumbAddSPReg";
345 def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
346 "add\t$dst, $rhs", []>,
347 T1Special<{0,0,?,?}> {
348 // A8.6.9 Encoding T2
352 let Inst{2-0} = 0b101;
353 let DecoderMethod = "DecodeThumbAddSPReg";
356 //===----------------------------------------------------------------------===//
357 // Control Flow Instructions.
361 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
362 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
363 T1Special<{1,1,0,?}> {
367 let Inst{2-0} = 0b000;
371 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
372 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br,
373 [(ARMretflag)], (tBX LR, pred:$p)>;
375 // Alternative return instruction used by vararg functions.
376 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
378 (tBX GPR:$Rm, pred:$p)>;
381 // All calls clobber the non-callee saved registers. SP is marked as a use to
382 // prevent stack-pointer assignments that appear immediately before calls from
383 // potentially appearing dead.
385 // On non-Darwin platforms R9 is callee-saved.
386 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
388 // Also used for Thumb2
389 def tBL : TIx2<0b11110, 0b11, 1,
390 (outs), (ins pred:$p, t_bltarget:$func, variable_ops), IIC_Br,
392 [(ARMtcall tglobaladdr:$func)]>,
393 Requires<[IsThumb, IsNotDarwin]> {
395 let Inst{26} = func{21};
396 let Inst{25-16} = func{20-11};
399 let Inst{10-0} = func{10-0};
402 // ARMv5T and above, also used for Thumb2
403 def tBLXi : TIx2<0b11110, 0b11, 0,
404 (outs), (ins pred:$p, t_blxtarget:$func, variable_ops), IIC_Br,
406 [(ARMcall tglobaladdr:$func)]>,
407 Requires<[IsThumb, HasV5T, IsNotDarwin]> {
409 let Inst{25-16} = func{20-11};
412 let Inst{10-1} = func{10-1};
413 let Inst{0} = 0; // func{0} is assumed zero
416 // Also used for Thumb2
417 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br,
419 [(ARMtcall GPR:$func)]>,
420 Requires<[IsThumb, HasV5T, IsNotDarwin]>,
421 T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24;
423 let Inst{6-3} = func;
424 let Inst{2-0} = 0b000;
428 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
430 [(ARMcall_nolink tGPR:$func)]>,
431 Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>;
435 // On Darwin R9 is call-clobbered.
436 // R7 is marked as a use to prevent frame-pointer assignments from being
437 // moved above / below calls.
438 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
440 // Also used for Thumb2
441 def tBLr9 : tPseudoExpand<(outs), (ins pred:$p, t_bltarget:$func, variable_ops),
442 4, IIC_Br, [(ARMtcall tglobaladdr:$func)],
443 (tBL pred:$p, t_bltarget:$func)>,
444 Requires<[IsThumb, IsDarwin]>;
446 // ARMv5T and above, also used for Thumb2
447 def tBLXi_r9 : tPseudoExpand<(outs), (ins pred:$p, t_blxtarget:$func, variable_ops),
448 4, IIC_Br, [(ARMcall tglobaladdr:$func)],
449 (tBLXi pred:$p, t_blxtarget:$func)>,
450 Requires<[IsThumb, HasV5T, IsDarwin]>;
452 // Also used for Thumb2
453 def tBLXr_r9 : tPseudoExpand<(outs), (ins pred:$p, GPR:$func, variable_ops),
454 2, IIC_Br, [(ARMtcall GPR:$func)],
455 (tBLXr pred:$p, GPR:$func)>,
456 Requires<[IsThumb, HasV5T, IsDarwin]>;
459 def tBXr9_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
461 [(ARMcall_nolink tGPR:$func)]>,
462 Requires<[IsThumb, IsThumb1Only, IsDarwin]>;
465 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
466 let isPredicable = 1 in
467 def tB : T1I<(outs), (ins t_brtarget:$target), IIC_Br,
468 "b\t$target", [(br bb:$target)]>,
469 T1Encoding<{1,1,1,0,0,?}> {
471 let Inst{10-0} = target;
475 // Just a pseudo for a tBL instruction. Needed to let regalloc know about
476 // the clobber of LR.
478 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p),
479 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>;
481 def tBR_JTr : tPseudoInst<(outs),
482 (ins tGPR:$target, i32imm:$jt, i32imm:$id),
484 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
485 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
489 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
490 // a two-value operand where a dag node expects two operands. :(
491 let isBranch = 1, isTerminator = 1 in
492 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
494 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
495 T1BranchCond<{1,1,0,1}> {
499 let Inst{7-0} = target;
503 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
505 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
507 // tTAILJMPd: Darwin version uses a Thumb2 branch (no Thumb1 tail calls
508 // on Darwin), so it's in ARMInstrThumb2.td.
509 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
511 (tBX GPR:$dst, (ops 14, zero_reg))>,
512 Requires<[IsThumb, IsDarwin]>;
514 // Non-Darwin versions (the difference is R9).
515 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
517 def tTAILJMPdND : tPseudoExpand<(outs), (ins t_brtarget:$dst, variable_ops),
519 (tB t_brtarget:$dst)>,
520 Requires<[IsThumb, IsNotDarwin]>;
521 def tTAILJMPrND : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
523 (tBX GPR:$dst, (ops 14, zero_reg))>,
524 Requires<[IsThumb, IsNotDarwin]>;
529 // A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
530 // A8.6.16 B: Encoding T1
531 // If Inst{11-8} == 0b1111 then SEE SVC
532 let isCall = 1, Uses = [SP] in
533 def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br,
534 "svc", "\t$imm", []>, Encoding16 {
536 let Inst{15-12} = 0b1101;
537 let Inst{11-8} = 0b1111;
541 // The assembler uses 0xDEFE for a trap instruction.
542 let isBarrier = 1, isTerminator = 1 in
543 def tTRAP : TI<(outs), (ins), IIC_Br,
544 "trap", [(trap)]>, Encoding16 {
548 //===----------------------------------------------------------------------===//
549 // Load Store Instructions.
552 // Loads: reg/reg and reg/imm5
553 let canFoldAsLoad = 1, isReMaterializable = 1 in
554 multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
555 Operand AddrMode_r, Operand AddrMode_i,
556 AddrMode am, InstrItinClass itin_r,
557 InstrItinClass itin_i, string asm,
560 T1pILdStEncode<reg_opc,
561 (outs tGPR:$Rt), (ins AddrMode_r:$addr),
562 am, itin_r, asm, "\t$Rt, $addr",
563 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
565 T1pILdStEncodeImm<imm_opc, 1 /* Load */,
566 (outs tGPR:$Rt), (ins AddrMode_i:$addr),
567 am, itin_i, asm, "\t$Rt, $addr",
568 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
570 // Stores: reg/reg and reg/imm5
571 multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
572 Operand AddrMode_r, Operand AddrMode_i,
573 AddrMode am, InstrItinClass itin_r,
574 InstrItinClass itin_i, string asm,
577 T1pILdStEncode<reg_opc,
578 (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
579 am, itin_r, asm, "\t$Rt, $addr",
580 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
582 T1pILdStEncodeImm<imm_opc, 0 /* Store */,
583 (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
584 am, itin_i, asm, "\t$Rt, $addr",
585 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
589 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4,
590 t_addrmode_is4, AddrModeT1_4,
591 IIC_iLoad_r, IIC_iLoad_i, "ldr",
592 UnOpFrag<(load node:$Src)>>;
595 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1,
596 t_addrmode_is1, AddrModeT1_1,
597 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
598 UnOpFrag<(zextloadi8 node:$Src)>>;
601 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
602 t_addrmode_is2, AddrModeT1_2,
603 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
604 UnOpFrag<(zextloadi16 node:$Src)>>;
606 let AddedComplexity = 10 in
607 def tLDRSB : // A8.6.80
608 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
609 AddrModeT1_1, IIC_iLoad_bh_r,
610 "ldrsb", "\t$Rt, $addr",
611 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))]>;
613 let AddedComplexity = 10 in
614 def tLDRSH : // A8.6.84
615 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
616 AddrModeT1_2, IIC_iLoad_bh_r,
617 "ldrsh", "\t$Rt, $addr",
618 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))]>;
620 let canFoldAsLoad = 1 in
621 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
622 "ldr", "\t$Rt, $addr",
623 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
628 let Inst{7-0} = addr;
632 // FIXME: Use ldr.n to work around a Darwin assembler bug.
633 let canFoldAsLoad = 1, isReMaterializable = 1, isCodeGenOnly = 1 in
634 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
635 "ldr", ".n\t$Rt, $addr",
636 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
637 T1Encoding<{0,1,0,0,1,?}> {
642 let Inst{7-0} = addr;
645 // FIXME: Remove this entry when the above ldr.n workaround is fixed.
646 // For disassembly use only.
647 def tLDRpciDIS : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
648 "ldr", "\t$Rt, $addr",
649 [/* disassembly only */]>,
650 T1Encoding<{0,1,0,0,1,?}> {
655 let Inst{7-0} = addr;
658 // A8.6.194 & A8.6.192
659 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
660 t_addrmode_is4, AddrModeT1_4,
661 IIC_iStore_r, IIC_iStore_i, "str",
662 BinOpFrag<(store node:$LHS, node:$RHS)>>;
664 // A8.6.197 & A8.6.195
665 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
666 t_addrmode_is1, AddrModeT1_1,
667 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
668 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
670 // A8.6.207 & A8.6.205
671 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
672 t_addrmode_is2, AddrModeT1_2,
673 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
674 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
677 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
678 "str", "\t$Rt, $addr",
679 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
684 let Inst{7-0} = addr;
687 //===----------------------------------------------------------------------===//
688 // Load / store multiple Instructions.
691 multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
692 InstrItinClass itin_upd, bits<6> T1Enc,
693 bit L_bit, string baseOpc> {
695 T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
696 itin, !strconcat(asm, "${p}\t$Rn, $regs"), []>,
701 let Inst{7-0} = regs;
705 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
706 "$Rn = $wb", itin_upd>,
707 PseudoInstExpansion<(!cast<Instruction>(!strconcat(baseOpc, "IA"))
708 tGPR:$Rn, pred:$p, reglist:$regs)> {
710 let OutOperandList = (outs GPR:$wb);
711 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
713 let isCodeGenOnly = 1;
715 list<Predicate> Predicates = [IsThumb];
719 // These require base address to be written back or one of the loaded regs.
720 let neverHasSideEffects = 1 in {
722 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
723 defm tLDM : thumb_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu,
724 {1,1,0,0,1,?}, 1, "tLDM">;
726 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
727 defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu,
728 {1,1,0,0,0,?}, 0, "tSTM">;
730 } // neverHasSideEffects
732 def : InstAlias<"ldm${p} $Rn!, $regs",
733 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>,
734 Requires<[IsThumb, IsThumb1Only]>;
737 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
738 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
740 "pop${p}\t$regs", []>,
741 T1Misc<{1,1,0,?,?,?,?}> {
743 let Inst{8} = regs{15};
744 let Inst{7-0} = regs{7-0};
747 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
748 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
750 "push${p}\t$regs", []>,
751 T1Misc<{0,1,0,?,?,?,?}> {
753 let Inst{8} = regs{14};
754 let Inst{7-0} = regs{7-0};
757 //===----------------------------------------------------------------------===//
758 // Arithmetic Instructions.
761 // Helper classes for encoding T1pI patterns:
762 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
763 string opc, string asm, list<dag> pattern>
764 : T1pI<oops, iops, itin, opc, asm, pattern>,
765 T1DataProcessing<opA> {
771 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
772 string opc, string asm, list<dag> pattern>
773 : T1pI<oops, iops, itin, opc, asm, pattern>,
781 // Helper classes for encoding T1sI patterns:
782 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
783 string opc, string asm, list<dag> pattern>
784 : T1sI<oops, iops, itin, opc, asm, pattern>,
785 T1DataProcessing<opA> {
791 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
792 string opc, string asm, list<dag> pattern>
793 : T1sI<oops, iops, itin, opc, asm, pattern>,
802 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
803 string opc, string asm, list<dag> pattern>
804 : T1sI<oops, iops, itin, opc, asm, pattern>,
812 // Helper classes for encoding T1sIt patterns:
813 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
814 string opc, string asm, list<dag> pattern>
815 : T1sIt<oops, iops, itin, opc, asm, pattern>,
816 T1DataProcessing<opA> {
822 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
823 string opc, string asm, list<dag> pattern>
824 : T1sIt<oops, iops, itin, opc, asm, pattern>,
828 let Inst{10-8} = Rdn;
829 let Inst{7-0} = imm8;
832 // Add with carry register
833 let isCommutable = 1, Uses = [CPSR] in
835 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
836 "adc", "\t$Rdn, $Rm",
837 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>;
840 def tADDi3 : // A8.6.4 T1
841 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
843 "add", "\t$Rd, $Rm, $imm3",
844 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> {
846 let Inst{8-6} = imm3;
849 def tADDi8 : // A8.6.4 T2
850 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),
851 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
852 "add", "\t$Rdn, $imm8",
853 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>;
856 let isCommutable = 1 in
857 def tADDrr : // A8.6.6 T1
858 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
860 "add", "\t$Rd, $Rn, $Rm",
861 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>;
863 let neverHasSideEffects = 1 in
864 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
865 "add", "\t$Rdn, $Rm", []>,
866 T1Special<{0,0,?,?}> {
870 let Inst{7} = Rdn{3};
872 let Inst{2-0} = Rdn{2-0};
876 let isCommutable = 1 in
877 def tAND : // A8.6.12
878 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
880 "and", "\t$Rdn, $Rm",
881 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>;
884 def tASRri : // A8.6.14
885 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
887 "asr", "\t$Rd, $Rm, $imm5",
888 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
890 let Inst{10-6} = imm5;
894 def tASRrr : // A8.6.15
895 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
897 "asr", "\t$Rdn, $Rm",
898 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>;
901 def tBIC : // A8.6.20
902 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
904 "bic", "\t$Rdn, $Rm",
905 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>;
908 let isCompare = 1, Defs = [CPSR] in {
909 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
910 // Compare-to-zero still works out, just not the relationals
911 //def tCMN : // A8.6.33
912 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
914 // "cmn", "\t$lhs, $rhs",
915 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
917 def tCMNz : // A8.6.33
918 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
921 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>;
923 } // isCompare = 1, Defs = [CPSR]
926 let isCompare = 1, Defs = [CPSR] in {
927 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi,
928 "cmp", "\t$Rn, $imm8",
929 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
930 T1General<{1,0,1,?,?}> {
935 let Inst{7-0} = imm8;
939 def tCMPr : // A8.6.36 T1
940 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
943 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>;
945 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
946 "cmp", "\t$Rn, $Rm", []>,
947 T1Special<{0,1,?,?}> {
953 let Inst{2-0} = Rn{2-0};
955 } // isCompare = 1, Defs = [CPSR]
959 let isCommutable = 1 in
960 def tEOR : // A8.6.45
961 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
963 "eor", "\t$Rdn, $Rm",
964 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>;
967 def tLSLri : // A8.6.88
968 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
970 "lsl", "\t$Rd, $Rm, $imm5",
971 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> {
973 let Inst{10-6} = imm5;
977 def tLSLrr : // A8.6.89
978 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
980 "lsl", "\t$Rdn, $Rm",
981 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>;
984 def tLSRri : // A8.6.90
985 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
987 "lsr", "\t$Rd, $Rm, $imm5",
988 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
990 let Inst{10-6} = imm5;
994 def tLSRrr : // A8.6.91
995 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
997 "lsr", "\t$Rdn, $Rm",
998 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>;
1001 let isMoveImm = 1 in
1002 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
1003 "mov", "\t$Rd, $imm8",
1004 [(set tGPR:$Rd, imm0_255:$imm8)]>,
1005 T1General<{1,0,0,?,?}> {
1009 let Inst{10-8} = Rd;
1010 let Inst{7-0} = imm8;
1013 // A7-73: MOV(2) - mov setting flag.
1015 let neverHasSideEffects = 1 in {
1016 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1018 "mov", "\t$Rd, $Rm", "", []>,
1019 T1Special<{1,0,?,?}> {
1023 let Inst{7} = Rd{3};
1025 let Inst{2-0} = Rd{2-0};
1027 let Defs = [CPSR] in
1028 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1029 "movs\t$Rd, $Rm", []>, Encoding16 {
1033 let Inst{15-6} = 0b0000000000;
1037 } // neverHasSideEffects
1039 // Multiply register
1040 let isCommutable = 1 in
1041 def tMUL : // A8.6.105 T1
1042 T1sItDPEncode<0b1101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1044 "mul", "\t$Rdn, $Rm, $Rdn",
1045 [(set tGPR:$Rdn, (mul tGPR:$Rn, tGPR:$Rm))]>;
1047 // Move inverse register
1048 def tMVN : // A8.6.107
1049 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1050 "mvn", "\t$Rd, $Rn",
1051 [(set tGPR:$Rd, (not tGPR:$Rn))]>;
1053 // Bitwise or register
1054 let isCommutable = 1 in
1055 def tORR : // A8.6.114
1056 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1058 "orr", "\t$Rdn, $Rm",
1059 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>;
1062 def tREV : // A8.6.134
1063 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1065 "rev", "\t$Rd, $Rm",
1066 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1067 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1069 def tREV16 : // A8.6.135
1070 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1072 "rev16", "\t$Rd, $Rm",
1073 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,
1074 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1076 def tREVSH : // A8.6.136
1077 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1079 "revsh", "\t$Rd, $Rm",
1080 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,
1081 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1083 // Rotate right register
1084 def tROR : // A8.6.139
1085 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1087 "ror", "\t$Rdn, $Rm",
1088 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>;
1091 def tRSB : // A8.6.141
1092 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1094 "rsb", "\t$Rd, $Rn, #0",
1095 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
1097 // Subtract with carry register
1098 let Uses = [CPSR] in
1099 def tSBC : // A8.6.151
1100 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1102 "sbc", "\t$Rdn, $Rm",
1103 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>;
1105 // Subtract immediate
1106 def tSUBi3 : // A8.6.210 T1
1107 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
1109 "sub", "\t$Rd, $Rm, $imm3",
1110 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> {
1112 let Inst{8-6} = imm3;
1115 def tSUBi8 : // A8.6.210 T2
1116 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
1118 "sub", "\t$Rdn, $imm8",
1119 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>;
1121 // Subtract register
1122 def tSUBrr : // A8.6.212
1123 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1125 "sub", "\t$Rd, $Rn, $Rm",
1126 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>;
1128 // TODO: A7-96: STMIA - store multiple.
1131 def tSXTB : // A8.6.222
1132 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1134 "sxtb", "\t$Rd, $Rm",
1135 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1136 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1138 // Sign-extend short
1139 def tSXTH : // A8.6.224
1140 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1142 "sxth", "\t$Rd, $Rm",
1143 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1144 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1147 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1148 def tTST : // A8.6.230
1149 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1150 "tst", "\t$Rn, $Rm",
1151 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>;
1154 def tUXTB : // A8.6.262
1155 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1157 "uxtb", "\t$Rd, $Rm",
1158 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1159 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1161 // Zero-extend short
1162 def tUXTH : // A8.6.264
1163 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1165 "uxth", "\t$Rd, $Rm",
1166 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1167 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1169 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1170 // Expanded after instruction selection into a branch sequence.
1171 let usesCustomInserter = 1 in // Expanded after instruction selection.
1172 def tMOVCCr_pseudo :
1173 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
1175 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
1177 // tLEApcrel - Load a pc-relative address into a register without offending the
1180 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1181 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>,
1182 T1Encoding<{1,0,1,0,0,?}> {
1185 let Inst{10-8} = Rd;
1186 let Inst{7-0} = addr;
1187 let DecoderMethod = "DecodeThumbAddSpecialReg";
1190 let neverHasSideEffects = 1, isReMaterializable = 1 in
1191 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1194 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1195 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1198 //===----------------------------------------------------------------------===//
1202 // __aeabi_read_tp preserves the registers r1-r3.
1203 // This is a pseudo inst so that we can get the encoding right,
1204 // complete with fixup for the aeabi_read_tp function.
1205 let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in
1206 def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br,
1207 [(set R0, ARMthread_pointer)]>;
1209 //===----------------------------------------------------------------------===//
1210 // SJLJ Exception handling intrinsics
1213 // eh_sjlj_setjmp() is an instruction sequence to store the return address and
1214 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1215 // from some other function to get here, and we're using the stack frame for the
1216 // containing function to save/restore registers, we can't keep anything live in
1217 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1218 // tromped upon when we get here from a longjmp(). We force everything out of
1219 // registers except for our own input by listing the relevant registers in
1220 // Defs. By doing so, we also cause the prologue/epilogue code to actively
1221 // preserve all of the callee-saved resgisters, which is exactly what we want.
1222 // $val is a scratch register for our use.
1223 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1224 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in
1225 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1226 AddrModeNone, 0, NoItinerary, "","",
1227 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1229 // FIXME: Non-Darwin version(s)
1230 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1231 Defs = [ R7, LR, SP ] in
1232 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1233 AddrModeNone, 0, IndexModeNone,
1234 Pseudo, NoItinerary, "", "",
1235 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1236 Requires<[IsThumb, IsDarwin]>;
1238 //===----------------------------------------------------------------------===//
1239 // Non-Instruction Patterns
1243 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1244 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>;
1245 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1246 (tCMPr tGPR:$Rn, tGPR:$Rm)>;
1249 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
1250 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1251 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
1252 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1253 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
1254 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1256 // Subtract with carry
1257 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
1258 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1259 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
1260 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1261 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
1262 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1264 // ConstantPool, GlobalAddress
1265 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1266 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1269 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1270 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1273 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1274 Requires<[IsThumb, IsNotDarwin]>;
1275 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
1276 Requires<[IsThumb, IsDarwin]>;
1278 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1279 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1280 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
1281 Requires<[IsThumb, HasV5T, IsDarwin]>;
1283 // Indirect calls to ARM routines
1284 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1285 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1286 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
1287 Requires<[IsThumb, HasV5T, IsDarwin]>;
1289 // zextload i1 -> zextload i8
1290 def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
1291 (tLDRBr t_addrmode_rrs1:$addr)>;
1292 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1293 (tLDRBi t_addrmode_is1:$addr)>;
1295 // extload -> zextload
1296 def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1297 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1298 def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1299 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1300 def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
1301 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>;
1303 // If it's impossible to use [r,r] address mode for sextload, select to
1304 // ldr{b|h} + sxt{b|h} instead.
1305 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1306 (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
1307 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1308 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1309 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
1310 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1311 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1312 (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
1313 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1314 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1315 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
1316 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1318 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1319 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
1320 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1321 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
1322 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1323 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>;
1324 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1325 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
1327 // Large immediate handling.
1330 def : T1Pat<(i32 thumb_immshifted:$src),
1331 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1332 (thumb_immshifted_shamt imm:$src))>;
1334 def : T1Pat<(i32 imm0_255_comp:$src),
1335 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1337 // Pseudo instruction that combines ldr from constpool and add pc. This should
1338 // be expanded into two instructions late to allow if-conversion and
1340 let isReMaterializable = 1 in
1341 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1343 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1345 Requires<[IsThumb, IsThumb1Only]>;
1347 // Pseudo-instruction for merged POP and return.
1348 // FIXME: remove when we have a way to marking a MI with these properties.
1349 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1350 hasExtraDefRegAllocReq = 1 in
1351 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1353 (tPOP pred:$p, reglist:$regs)>;
1355 // Indirect branch using "mov pc, $Rm"
1356 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1357 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p),
1358 2, IIC_Br, [(brind GPR:$Rm)],
1359 (tMOVr PC, GPR:$Rm, pred:$p)>;