1 //===-- ARMInstrThumb.td - Thumb support for ARM -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
22 def imm_sr_XFORM: SDNodeXForm<imm, [{
23 unsigned Imm = N->getZExtValue();
24 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), MVT::i32);
26 def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; }
27 def imm_sr : Operand<i32>, PatLeaf<(imm), [{
28 uint64_t Imm = N->getZExtValue();
29 return Imm > 0 && Imm <= 32;
31 let PrintMethod = "printThumbSRImm";
32 let ParserMatchClass = ThumbSRImmAsmOperand;
35 def imm_comp_XFORM : SDNodeXForm<imm, [{
36 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
39 def imm0_7_neg : PatLeaf<(i32 imm), [{
40 return (uint32_t)-N->getZExtValue() < 8;
43 def imm0_255_comp : PatLeaf<(i32 imm), [{
44 return ~((uint32_t)N->getZExtValue()) < 256;
47 def imm8_255 : ImmLeaf<i32, [{
48 return Imm >= 8 && Imm < 256;
50 def imm8_255_neg : PatLeaf<(i32 imm), [{
51 unsigned Val = -N->getZExtValue();
52 return Val >= 8 && Val < 256;
55 // Break imm's up into two pieces: an immediate + a left shift. This uses
56 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
57 // to get the val/shift pieces.
58 def thumb_immshifted : PatLeaf<(imm), [{
59 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
62 def thumb_immshifted_val : SDNodeXForm<imm, [{
63 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
64 return CurDAG->getTargetConstant(V, MVT::i32);
67 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
68 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
69 return CurDAG->getTargetConstant(V, MVT::i32);
72 // ADR instruction labels.
73 def t_adrlabel : Operand<i32> {
74 let EncoderMethod = "getThumbAdrLabelOpValue";
77 // Scaled 4 immediate.
78 def t_imm0_1020s4_asmoperand: AsmOperandClass { let Name = "Imm0_1020s4"; }
79 def t_imm0_1020s4 : Operand<i32> {
80 let PrintMethod = "printThumbS4ImmOperand";
81 let ParserMatchClass = t_imm0_1020s4_asmoperand;
82 let OperandType = "OPERAND_IMMEDIATE";
85 def t_imm0_508s4_asmoperand: AsmOperandClass { let Name = "Imm0_508s4"; }
86 def t_imm0_508s4 : Operand<i32> {
87 let PrintMethod = "printThumbS4ImmOperand";
88 let ParserMatchClass = t_imm0_508s4_asmoperand;
89 let OperandType = "OPERAND_IMMEDIATE";
91 // Alias use only, so no printer is necessary.
92 def t_imm0_508s4_neg_asmoperand: AsmOperandClass { let Name = "Imm0_508s4Neg"; }
93 def t_imm0_508s4_neg : Operand<i32> {
94 let ParserMatchClass = t_imm0_508s4_neg_asmoperand;
95 let OperandType = "OPERAND_IMMEDIATE";
98 // Define Thumb specific addressing modes.
100 let OperandType = "OPERAND_PCREL" in {
101 def t_brtarget : Operand<OtherVT> {
102 let EncoderMethod = "getThumbBRTargetOpValue";
103 let DecoderMethod = "DecodeThumbBROperand";
106 def t_bcctarget : Operand<i32> {
107 let EncoderMethod = "getThumbBCCTargetOpValue";
108 let DecoderMethod = "DecodeThumbBCCTargetOperand";
111 def t_cbtarget : Operand<i32> {
112 let EncoderMethod = "getThumbCBTargetOpValue";
113 let DecoderMethod = "DecodeThumbCmpBROperand";
116 def t_bltarget : Operand<i32> {
117 let EncoderMethod = "getThumbBLTargetOpValue";
118 let DecoderMethod = "DecodeThumbBLTargetOperand";
121 def t_blxtarget : Operand<i32> {
122 let EncoderMethod = "getThumbBLXTargetOpValue";
123 let DecoderMethod = "DecodeThumbBLXOffset";
127 // t_addrmode_rr := reg + reg
129 def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; }
130 def t_addrmode_rr : Operand<i32>,
131 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
132 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
133 let PrintMethod = "printThumbAddrModeRROperand";
134 let DecoderMethod = "DecodeThumbAddrModeRR";
135 let ParserMatchClass = t_addrmode_rr_asm_operand;
136 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
139 // t_addrmode_rrs := reg + reg
141 // We use separate scaled versions because the Select* functions need
142 // to explicitly check for a matching constant and return false here so that
143 // the reg+imm forms will match instead. This is a horrible way to do that,
144 // as it forces tight coupling between the methods, but it's how selectiondag
146 def t_addrmode_rrs1 : Operand<i32>,
147 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
148 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
149 let PrintMethod = "printThumbAddrModeRROperand";
150 let DecoderMethod = "DecodeThumbAddrModeRR";
151 let ParserMatchClass = t_addrmode_rr_asm_operand;
152 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
154 def t_addrmode_rrs2 : Operand<i32>,
155 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
156 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
157 let DecoderMethod = "DecodeThumbAddrModeRR";
158 let PrintMethod = "printThumbAddrModeRROperand";
159 let ParserMatchClass = t_addrmode_rr_asm_operand;
160 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
162 def t_addrmode_rrs4 : Operand<i32>,
163 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
164 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
165 let DecoderMethod = "DecodeThumbAddrModeRR";
166 let PrintMethod = "printThumbAddrModeRROperand";
167 let ParserMatchClass = t_addrmode_rr_asm_operand;
168 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
171 // t_addrmode_is4 := reg + imm5 * 4
173 def t_addrmode_is4_asm_operand : AsmOperandClass { let Name = "MemThumbRIs4"; }
174 def t_addrmode_is4 : Operand<i32>,
175 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
176 let EncoderMethod = "getAddrModeISOpValue";
177 let DecoderMethod = "DecodeThumbAddrModeIS";
178 let PrintMethod = "printThumbAddrModeImm5S4Operand";
179 let ParserMatchClass = t_addrmode_is4_asm_operand;
180 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
183 // t_addrmode_is2 := reg + imm5 * 2
185 def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; }
186 def t_addrmode_is2 : Operand<i32>,
187 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
188 let EncoderMethod = "getAddrModeISOpValue";
189 let DecoderMethod = "DecodeThumbAddrModeIS";
190 let PrintMethod = "printThumbAddrModeImm5S2Operand";
191 let ParserMatchClass = t_addrmode_is2_asm_operand;
192 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
195 // t_addrmode_is1 := reg + imm5
197 def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; }
198 def t_addrmode_is1 : Operand<i32>,
199 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
200 let EncoderMethod = "getAddrModeISOpValue";
201 let DecoderMethod = "DecodeThumbAddrModeIS";
202 let PrintMethod = "printThumbAddrModeImm5S1Operand";
203 let ParserMatchClass = t_addrmode_is1_asm_operand;
204 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
207 // t_addrmode_sp := sp + imm8 * 4
209 // FIXME: This really shouldn't have an explicit SP operand at all. It should
210 // be implicit, just like in the instruction encoding itself.
211 def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; }
212 def t_addrmode_sp : Operand<i32>,
213 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
214 let EncoderMethod = "getAddrModeThumbSPOpValue";
215 let DecoderMethod = "DecodeThumbAddrModeSP";
216 let PrintMethod = "printThumbAddrModeSPOperand";
217 let ParserMatchClass = t_addrmode_sp_asm_operand;
218 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
221 // t_addrmode_pc := <label> => pc + imm8 * 4
223 def t_addrmode_pc : Operand<i32> {
224 let EncoderMethod = "getAddrModePCOpValue";
225 let DecoderMethod = "DecodeThumbAddrModePC";
226 let PrintMethod = "printThumbLdrLabelOperand";
229 //===----------------------------------------------------------------------===//
230 // Miscellaneous Instructions.
233 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
234 // from removing one half of the matched pairs. That breaks PEI, which assumes
235 // these will always be in pairs, and asserts if it finds otherwise. Better way?
236 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
237 def tADJCALLSTACKUP :
238 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
239 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
240 Requires<[IsThumb, IsThumb1Only]>;
242 def tADJCALLSTACKDOWN :
243 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
244 [(ARMcallseq_start imm:$amt)]>,
245 Requires<[IsThumb, IsThumb1Only]>;
248 class T1SystemEncoding<bits<8> opc>
249 : T1Encoding<0b101111> {
250 let Inst{9-8} = 0b11;
254 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "", []>,
255 T1SystemEncoding<0x00>, // A8.6.110
256 Requires<[IsThumb2]>;
258 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "", []>,
259 T1SystemEncoding<0x10>, // A8.6.410
260 Requires<[IsThumb2]>;
262 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "", []>,
263 T1SystemEncoding<0x20>, // A8.6.408
264 Requires<[IsThumb2]>;
266 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "", []>,
267 T1SystemEncoding<0x30>, // A8.6.409
268 Requires<[IsThumb2]>;
270 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "", []>,
271 T1SystemEncoding<0x40>, // A8.6.157
272 Requires<[IsThumb2]>;
274 // The imm operand $val can be used by a debugger to store more information
275 // about the breakpoint.
276 def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val",
278 T1Encoding<0b101111> {
279 let Inst{9-8} = 0b10;
285 def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end",
286 []>, T1Encoding<0b101101> {
289 let Inst{9-5} = 0b10010;
292 let Inst{2-0} = 0b000;
295 // Change Processor State is a system instruction -- for disassembly only.
296 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
297 NoItinerary, "cps$imod $iflags", []>,
305 let Inst{2-0} = iflags;
306 let DecoderMethod = "DecodeThumbCPS";
309 // For both thumb1 and thumb2.
310 let isNotDuplicable = 1, isCodeGenOnly = 1 in
311 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
312 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
313 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
316 let Inst{6-3} = 0b1111; // Rm = pc
320 // ADD <Rd>, sp, #<imm8>
321 // FIXME: This should not be marked as having side effects, and it should be
322 // rematerializable. Clearing the side effect bit causes miscompilations,
323 // probably because the instruction can be moved around.
324 def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm0_1020s4:$imm),
325 IIC_iALUi, "add", "\t$dst, $sp, $imm", []>,
326 T1Encoding<{1,0,1,0,1,?}>, Sched<[WriteALU]> {
330 let Inst{10-8} = dst;
332 let DecoderMethod = "DecodeThumbAddSpecialReg";
335 // ADD sp, sp, #<imm7>
336 def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
337 IIC_iALUi, "add", "\t$Rdn, $imm", []>,
338 T1Misc<{0,0,0,0,0,?,?}>, Sched<[WriteALU]> {
342 let DecoderMethod = "DecodeThumbAddSPImm";
345 // SUB sp, sp, #<imm7>
346 // FIXME: The encoding and the ASM string don't match up.
347 def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
348 IIC_iALUi, "sub", "\t$Rdn, $imm", []>,
349 T1Misc<{0,0,0,0,1,?,?}>, Sched<[WriteALU]> {
353 let DecoderMethod = "DecodeThumbAddSPImm";
356 def : tInstAlias<"add${p} sp, $imm",
357 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>;
358 def : tInstAlias<"add${p} sp, sp, $imm",
359 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>;
361 // Can optionally specify SP as a three operand instruction.
362 def : tInstAlias<"add${p} sp, sp, $imm",
363 (tADDspi SP, t_imm0_508s4:$imm, pred:$p)>;
364 def : tInstAlias<"sub${p} sp, sp, $imm",
365 (tSUBspi SP, t_imm0_508s4:$imm, pred:$p)>;
368 def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr,
369 "add", "\t$Rdn, $sp, $Rn", []>,
370 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
371 // A8.6.9 Encoding T1
373 let Inst{7} = Rdn{3};
374 let Inst{6-3} = 0b1101;
375 let Inst{2-0} = Rdn{2-0};
376 let DecoderMethod = "DecodeThumbAddSPReg";
380 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
381 "add", "\t$Rdn, $Rm", []>,
382 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
383 // A8.6.9 Encoding T2
387 let Inst{2-0} = 0b101;
388 let DecoderMethod = "DecodeThumbAddSPReg";
391 //===----------------------------------------------------------------------===//
392 // Control Flow Instructions.
396 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
397 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
398 T1Special<{1,1,0,?}> {
402 let Inst{2-0} = 0b000;
403 let Unpredictable{2-0} = 0b111;
407 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
408 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br,
409 [(ARMretflag)], (tBX LR, pred:$p)>;
411 // Alternative return instruction used by vararg functions.
412 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
414 (tBX GPR:$Rm, pred:$p)>;
417 // All calls clobber the non-callee saved registers. SP is marked as a use to
418 // prevent stack-pointer assignments that appear immediately before calls from
419 // potentially appearing dead.
421 Defs = [LR], Uses = [SP] in {
422 // Also used for Thumb2
423 def tBL : TIx2<0b11110, 0b11, 1,
424 (outs), (ins pred:$p, t_bltarget:$func), IIC_Br,
426 [(ARMtcall tglobaladdr:$func)]>,
427 Requires<[IsThumb]> {
429 let Inst{26} = func{23};
430 let Inst{25-16} = func{20-11};
431 let Inst{13} = func{22};
432 let Inst{11} = func{21};
433 let Inst{10-0} = func{10-0};
436 // ARMv5T and above, also used for Thumb2
437 def tBLXi : TIx2<0b11110, 0b11, 0,
438 (outs), (ins pred:$p, t_blxtarget:$func), IIC_Br,
440 [(ARMcall tglobaladdr:$func)]>,
441 Requires<[IsThumb, HasV5T]> {
443 let Inst{26} = func{23};
444 let Inst{25-16} = func{20-11};
445 let Inst{13} = func{22};
446 let Inst{11} = func{21};
447 let Inst{10-1} = func{10-1};
448 let Inst{0} = 0; // func{0} is assumed zero
451 // Also used for Thumb2
452 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func), IIC_Br,
454 [(ARMtcall GPR:$func)]>,
455 Requires<[IsThumb, HasV5T]>,
456 T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24;
458 let Inst{6-3} = func;
459 let Inst{2-0} = 0b000;
463 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func),
465 [(ARMcall_nolink tGPR:$func)]>,
466 Requires<[IsThumb, IsThumb1Only]>;
469 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
470 let isPredicable = 1 in
471 def tB : T1pI<(outs), (ins t_brtarget:$target), IIC_Br,
472 "b", "\t$target", [(br bb:$target)]>,
473 T1Encoding<{1,1,1,0,0,?}> {
475 let Inst{10-0} = target;
479 // Just a pseudo for a tBL instruction. Needed to let regalloc know about
480 // the clobber of LR.
482 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p),
483 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>;
485 def tBR_JTr : tPseudoInst<(outs),
486 (ins tGPR:$target, i32imm:$jt, i32imm:$id),
488 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
489 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
493 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
494 // a two-value operand where a dag node expects two operands. :(
495 let isBranch = 1, isTerminator = 1 in
496 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
498 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
499 T1BranchCond<{1,1,0,1}> {
503 let Inst{7-0} = target;
507 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
510 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst),
512 (tBX GPR:$dst, (ops 14, zero_reg))>,
515 // tTAILJMPd: IOS version uses a Thumb2 branch (no Thumb1 tail calls
516 // on IOS), so it's in ARMInstrThumb2.td.
519 def tTAILJMPdND : tPseudoExpand<(outs),
520 (ins t_brtarget:$dst, pred:$p),
522 (tB t_brtarget:$dst, pred:$p)>,
523 Requires<[IsThumb, IsNotIOS]>;
528 // A8.6.218 Supervisor Call (Software Interrupt)
529 // A8.6.16 B: Encoding T1
530 // If Inst{11-8} == 0b1111 then SEE SVC
531 let isCall = 1, Uses = [SP] in
532 def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br,
533 "svc", "\t$imm", []>, Encoding16 {
535 let Inst{15-12} = 0b1101;
536 let Inst{11-8} = 0b1111;
540 // The assembler uses 0xDEFE for a trap instruction.
541 let isBarrier = 1, isTerminator = 1 in
542 def tTRAP : TI<(outs), (ins), IIC_Br,
543 "trap", [(trap)]>, Encoding16 {
547 //===----------------------------------------------------------------------===//
548 // Load Store Instructions.
551 // Loads: reg/reg and reg/imm5
552 let canFoldAsLoad = 1, isReMaterializable = 1 in
553 multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
554 Operand AddrMode_r, Operand AddrMode_i,
555 AddrMode am, InstrItinClass itin_r,
556 InstrItinClass itin_i, string asm,
559 T1pILdStEncode<reg_opc,
560 (outs tGPR:$Rt), (ins AddrMode_r:$addr),
561 am, itin_r, asm, "\t$Rt, $addr",
562 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
564 T1pILdStEncodeImm<imm_opc, 1 /* Load */,
565 (outs tGPR:$Rt), (ins AddrMode_i:$addr),
566 am, itin_i, asm, "\t$Rt, $addr",
567 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
569 // Stores: reg/reg and reg/imm5
570 multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
571 Operand AddrMode_r, Operand AddrMode_i,
572 AddrMode am, InstrItinClass itin_r,
573 InstrItinClass itin_i, string asm,
576 T1pILdStEncode<reg_opc,
577 (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
578 am, itin_r, asm, "\t$Rt, $addr",
579 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
581 T1pILdStEncodeImm<imm_opc, 0 /* Store */,
582 (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
583 am, itin_i, asm, "\t$Rt, $addr",
584 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
588 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4,
589 t_addrmode_is4, AddrModeT1_4,
590 IIC_iLoad_r, IIC_iLoad_i, "ldr",
591 UnOpFrag<(load node:$Src)>>;
594 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1,
595 t_addrmode_is1, AddrModeT1_1,
596 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
597 UnOpFrag<(zextloadi8 node:$Src)>>;
600 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
601 t_addrmode_is2, AddrModeT1_2,
602 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
603 UnOpFrag<(zextloadi16 node:$Src)>>;
605 let AddedComplexity = 10 in
606 def tLDRSB : // A8.6.80
607 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
608 AddrModeT1_1, IIC_iLoad_bh_r,
609 "ldrsb", "\t$Rt, $addr",
610 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))]>;
612 let AddedComplexity = 10 in
613 def tLDRSH : // A8.6.84
614 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
615 AddrModeT1_2, IIC_iLoad_bh_r,
616 "ldrsh", "\t$Rt, $addr",
617 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))]>;
619 let canFoldAsLoad = 1 in
620 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
621 "ldr", "\t$Rt, $addr",
622 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
627 let Inst{7-0} = addr;
631 // FIXME: Use ldr.n to work around a darwin assembler bug.
632 let canFoldAsLoad = 1, isReMaterializable = 1, isCodeGenOnly = 1 in
633 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
634 "ldr", ".n\t$Rt, $addr",
635 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
636 T1Encoding<{0,1,0,0,1,?}> {
641 let Inst{7-0} = addr;
644 // FIXME: Remove this entry when the above ldr.n workaround is fixed.
645 // For assembly/disassembly use only.
646 def tLDRpciASM : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
647 "ldr", "\t$Rt, $addr", []>,
648 T1Encoding<{0,1,0,0,1,?}> {
653 let Inst{7-0} = addr;
656 // A8.6.194 & A8.6.192
657 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
658 t_addrmode_is4, AddrModeT1_4,
659 IIC_iStore_r, IIC_iStore_i, "str",
660 BinOpFrag<(store node:$LHS, node:$RHS)>>;
662 // A8.6.197 & A8.6.195
663 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
664 t_addrmode_is1, AddrModeT1_1,
665 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
666 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
668 // A8.6.207 & A8.6.205
669 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
670 t_addrmode_is2, AddrModeT1_2,
671 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
672 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
675 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
676 "str", "\t$Rt, $addr",
677 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
682 let Inst{7-0} = addr;
685 //===----------------------------------------------------------------------===//
686 // Load / store multiple Instructions.
689 // These require base address to be written back or one of the loaded regs.
690 let neverHasSideEffects = 1 in {
692 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
693 def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
694 IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> {
698 let Inst{7-0} = regs;
701 // Writeback version is just a pseudo, as there's no encoding difference.
702 // Writeback happens iff the base register is not in the destination register
705 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
706 "$Rn = $wb", IIC_iLoad_mu>,
707 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> {
709 let OutOperandList = (outs GPR:$wb);
710 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
712 let isCodeGenOnly = 1;
714 list<Predicate> Predicates = [IsThumb];
717 // There is no non-writeback version of STM for Thumb.
718 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
719 def tSTMIA_UPD : Thumb1I<(outs GPR:$wb),
720 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
721 AddrModeNone, 2, IIC_iStore_mu,
722 "stm${p}\t$Rn!, $regs", "$Rn = $wb", []>,
723 T1Encoding<{1,1,0,0,0,?}> {
727 let Inst{7-0} = regs;
730 } // neverHasSideEffects
732 def : InstAlias<"ldm${p} $Rn!, $regs",
733 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>,
734 Requires<[IsThumb, IsThumb1Only]>;
736 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
737 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
739 "pop${p}\t$regs", []>,
740 T1Misc<{1,1,0,?,?,?,?}> {
742 let Inst{8} = regs{15};
743 let Inst{7-0} = regs{7-0};
746 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
747 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
749 "push${p}\t$regs", []>,
750 T1Misc<{0,1,0,?,?,?,?}> {
752 let Inst{8} = regs{14};
753 let Inst{7-0} = regs{7-0};
756 //===----------------------------------------------------------------------===//
757 // Arithmetic Instructions.
760 // Helper classes for encoding T1pI patterns:
761 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
762 string opc, string asm, list<dag> pattern>
763 : T1pI<oops, iops, itin, opc, asm, pattern>,
764 T1DataProcessing<opA> {
770 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
771 string opc, string asm, list<dag> pattern>
772 : T1pI<oops, iops, itin, opc, asm, pattern>,
780 // Helper classes for encoding T1sI patterns:
781 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
782 string opc, string asm, list<dag> pattern>
783 : T1sI<oops, iops, itin, opc, asm, pattern>,
784 T1DataProcessing<opA> {
790 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
791 string opc, string asm, list<dag> pattern>
792 : T1sI<oops, iops, itin, opc, asm, pattern>,
801 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
802 string opc, string asm, list<dag> pattern>
803 : T1sI<oops, iops, itin, opc, asm, pattern>,
811 // Helper classes for encoding T1sIt patterns:
812 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
813 string opc, string asm, list<dag> pattern>
814 : T1sIt<oops, iops, itin, opc, asm, pattern>,
815 T1DataProcessing<opA> {
821 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
822 string opc, string asm, list<dag> pattern>
823 : T1sIt<oops, iops, itin, opc, asm, pattern>,
827 let Inst{10-8} = Rdn;
828 let Inst{7-0} = imm8;
831 // Add with carry register
832 let isCommutable = 1, Uses = [CPSR] in
834 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
835 "adc", "\t$Rdn, $Rm",
836 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
839 def tADDi3 : // A8.6.4 T1
840 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
842 "add", "\t$Rd, $Rm, $imm3",
843 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>,
846 let Inst{8-6} = imm3;
849 def tADDi8 : // A8.6.4 T2
850 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),
851 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
852 "add", "\t$Rdn, $imm8",
853 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>,
857 let isCommutable = 1 in
858 def tADDrr : // A8.6.6 T1
859 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
861 "add", "\t$Rd, $Rn, $Rm",
862 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
864 let neverHasSideEffects = 1 in
865 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
866 "add", "\t$Rdn, $Rm", []>,
867 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
871 let Inst{7} = Rdn{3};
873 let Inst{2-0} = Rdn{2-0};
877 let isCommutable = 1 in
878 def tAND : // A8.6.12
879 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
881 "and", "\t$Rdn, $Rm",
882 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
885 def tASRri : // A8.6.14
886 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
888 "asr", "\t$Rd, $Rm, $imm5",
889 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
892 let Inst{10-6} = imm5;
896 def tASRrr : // A8.6.15
897 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
899 "asr", "\t$Rdn, $Rm",
900 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
903 def tBIC : // A8.6.20
904 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
906 "bic", "\t$Rdn, $Rm",
907 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>,
911 let isCompare = 1, Defs = [CPSR] in {
912 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
913 // Compare-to-zero still works out, just not the relationals
914 //def tCMN : // A8.6.33
915 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
917 // "cmn", "\t$lhs, $rhs",
918 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
920 def tCMNz : // A8.6.33
921 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
924 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>, Sched<[WriteCMP]>;
926 } // isCompare = 1, Defs = [CPSR]
929 let isCompare = 1, Defs = [CPSR] in {
930 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi,
931 "cmp", "\t$Rn, $imm8",
932 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
933 T1General<{1,0,1,?,?}>, Sched<[WriteCMP]> {
938 let Inst{7-0} = imm8;
942 def tCMPr : // A8.6.36 T1
943 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
946 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>, Sched<[WriteCMP]>;
948 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
949 "cmp", "\t$Rn, $Rm", []>,
950 T1Special<{0,1,?,?}>, Sched<[WriteCMP]> {
956 let Inst{2-0} = Rn{2-0};
958 } // isCompare = 1, Defs = [CPSR]
962 let isCommutable = 1 in
963 def tEOR : // A8.6.45
964 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
966 "eor", "\t$Rdn, $Rm",
967 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
970 def tLSLri : // A8.6.88
971 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5),
973 "lsl", "\t$Rd, $Rm, $imm5",
974 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]>,
977 let Inst{10-6} = imm5;
981 def tLSLrr : // A8.6.89
982 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
984 "lsl", "\t$Rdn, $Rm",
985 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
988 def tLSRri : // A8.6.90
989 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
991 "lsr", "\t$Rd, $Rm, $imm5",
992 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
995 let Inst{10-6} = imm5;
999 def tLSRrr : // A8.6.91
1000 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1002 "lsr", "\t$Rdn, $Rm",
1003 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1006 let isMoveImm = 1 in
1007 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
1008 "mov", "\t$Rd, $imm8",
1009 [(set tGPR:$Rd, imm0_255:$imm8)]>,
1010 T1General<{1,0,0,?,?}>, Sched<[WriteALU]> {
1014 let Inst{10-8} = Rd;
1015 let Inst{7-0} = imm8;
1017 // Because we have an explicit tMOVSr below, we need an alias to handle
1018 // the immediate "movs" form here. Blech.
1019 def : tInstAlias <"movs $Rdn, $imm",
1020 (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>;
1022 // A7-73: MOV(2) - mov setting flag.
1024 let neverHasSideEffects = 1 in {
1025 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1027 "mov", "\t$Rd, $Rm", "", []>,
1028 T1Special<{1,0,?,?}>, Sched<[WriteALU]> {
1032 let Inst{7} = Rd{3};
1034 let Inst{2-0} = Rd{2-0};
1036 let Defs = [CPSR] in
1037 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1038 "movs\t$Rd, $Rm", []>, Encoding16, Sched<[WriteALU]> {
1042 let Inst{15-6} = 0b0000000000;
1046 } // neverHasSideEffects
1048 // Multiply register
1049 let isCommutable = 1 in
1050 def tMUL : // A8.6.105 T1
1051 Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2,
1052 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd",
1053 [(set tGPR:$Rd, (mul tGPR:$Rn, tGPR:$Rm))]>,
1054 T1DataProcessing<0b1101> {
1059 let AsmMatchConverter = "cvtThumbMultiply";
1062 def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn,
1065 // Move inverse register
1066 def tMVN : // A8.6.107
1067 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1068 "mvn", "\t$Rd, $Rn",
1069 [(set tGPR:$Rd, (not tGPR:$Rn))]>, Sched<[WriteALU]>;
1071 // Bitwise or register
1072 let isCommutable = 1 in
1073 def tORR : // A8.6.114
1074 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1076 "orr", "\t$Rdn, $Rm",
1077 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1080 def tREV : // A8.6.134
1081 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1083 "rev", "\t$Rd, $Rm",
1084 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1085 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1087 def tREV16 : // A8.6.135
1088 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1090 "rev16", "\t$Rd, $Rm",
1091 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,
1092 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1094 def tREVSH : // A8.6.136
1095 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1097 "revsh", "\t$Rd, $Rm",
1098 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,
1099 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1101 // Rotate right register
1102 def tROR : // A8.6.139
1103 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1105 "ror", "\t$Rdn, $Rm",
1106 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>,
1110 def tRSB : // A8.6.141
1111 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1113 "rsb", "\t$Rd, $Rn, #0",
1114 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>, Sched<[WriteALU]>;
1116 // Subtract with carry register
1117 let Uses = [CPSR] in
1118 def tSBC : // A8.6.151
1119 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1121 "sbc", "\t$Rdn, $Rm",
1122 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>,
1125 // Subtract immediate
1126 def tSUBi3 : // A8.6.210 T1
1127 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
1129 "sub", "\t$Rd, $Rm, $imm3",
1130 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]>,
1133 let Inst{8-6} = imm3;
1136 def tSUBi8 : // A8.6.210 T2
1137 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn),
1138 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
1139 "sub", "\t$Rdn, $imm8",
1140 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>,
1143 // Subtract register
1144 def tSUBrr : // A8.6.212
1145 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1147 "sub", "\t$Rd, $Rn, $Rm",
1148 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>,
1152 def tSXTB : // A8.6.222
1153 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1155 "sxtb", "\t$Rd, $Rm",
1156 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1157 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1160 // Sign-extend short
1161 def tSXTH : // A8.6.224
1162 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1164 "sxth", "\t$Rd, $Rm",
1165 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1166 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1170 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1171 def tTST : // A8.6.230
1172 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1173 "tst", "\t$Rn, $Rm",
1174 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>,
1178 def tUXTB : // A8.6.262
1179 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1181 "uxtb", "\t$Rd, $Rm",
1182 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1183 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1186 // Zero-extend short
1187 def tUXTH : // A8.6.264
1188 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1190 "uxth", "\t$Rd, $Rm",
1191 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1192 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1194 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1195 // Expanded after instruction selection into a branch sequence.
1196 let usesCustomInserter = 1 in // Expanded after instruction selection.
1197 def tMOVCCr_pseudo :
1198 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
1200 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
1202 // tLEApcrel - Load a pc-relative address into a register without offending the
1205 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1206 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>,
1207 T1Encoding<{1,0,1,0,0,?}>, Sched<[WriteALU]> {
1210 let Inst{10-8} = Rd;
1211 let Inst{7-0} = addr;
1212 let DecoderMethod = "DecodeThumbAddSpecialReg";
1215 let neverHasSideEffects = 1, isReMaterializable = 1 in
1216 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1217 2, IIC_iALUi, []>, Sched<[WriteALU]>;
1219 let hasSideEffects = 1 in
1220 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1221 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1222 2, IIC_iALUi, []>, Sched<[WriteALU]>;
1224 //===----------------------------------------------------------------------===//
1228 // __aeabi_read_tp preserves the registers r1-r3.
1229 // This is a pseudo inst so that we can get the encoding right,
1230 // complete with fixup for the aeabi_read_tp function.
1231 let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in
1232 def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br,
1233 [(set R0, ARMthread_pointer)]>;
1235 //===----------------------------------------------------------------------===//
1236 // SJLJ Exception handling intrinsics
1239 // eh_sjlj_setjmp() is an instruction sequence to store the return address and
1240 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1241 // from some other function to get here, and we're using the stack frame for the
1242 // containing function to save/restore registers, we can't keep anything live in
1243 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1244 // tromped upon when we get here from a longjmp(). We force everything out of
1245 // registers except for our own input by listing the relevant registers in
1246 // Defs. By doing so, we also cause the prologue/epilogue code to actively
1247 // preserve all of the callee-saved resgisters, which is exactly what we want.
1248 // $val is a scratch register for our use.
1249 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1250 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
1251 usesCustomInserter = 1 in
1252 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1253 AddrModeNone, 0, NoItinerary, "","",
1254 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1256 // FIXME: Non-IOS version(s)
1257 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1258 Defs = [ R7, LR, SP ] in
1259 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1260 AddrModeNone, 0, IndexModeNone,
1261 Pseudo, NoItinerary, "", "",
1262 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1263 Requires<[IsThumb, IsIOS]>;
1265 //===----------------------------------------------------------------------===//
1266 // Non-Instruction Patterns
1270 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1271 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>;
1272 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1273 (tCMPr tGPR:$Rn, tGPR:$Rm)>;
1276 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
1277 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1278 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
1279 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1280 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
1281 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1283 // Subtract with carry
1284 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
1285 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1286 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
1287 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1288 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
1289 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1291 // ConstantPool, GlobalAddress
1292 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1293 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1296 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1297 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1300 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1301 Requires<[IsThumb]>;
1303 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1304 Requires<[IsThumb, HasV5T]>;
1306 // Indirect calls to ARM routines
1307 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1308 Requires<[IsThumb, HasV5T]>;
1310 // zextload i1 -> zextload i8
1311 def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
1312 (tLDRBr t_addrmode_rrs1:$addr)>;
1313 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1314 (tLDRBi t_addrmode_is1:$addr)>;
1316 // extload -> zextload
1317 def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1318 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1319 def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1320 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1321 def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
1322 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>;
1324 // If it's impossible to use [r,r] address mode for sextload, select to
1325 // ldr{b|h} + sxt{b|h} instead.
1326 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1327 (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
1328 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1329 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1330 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
1331 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1332 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1333 (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
1334 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1335 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1336 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
1337 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1339 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1340 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
1341 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1342 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
1343 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1344 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>;
1345 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1346 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
1348 def : T1Pat<(atomic_load_8 t_addrmode_is1:$src),
1349 (tLDRBi t_addrmode_is1:$src)>;
1350 def : T1Pat<(atomic_load_8 t_addrmode_rrs1:$src),
1351 (tLDRBr t_addrmode_rrs1:$src)>;
1352 def : T1Pat<(atomic_load_16 t_addrmode_is2:$src),
1353 (tLDRHi t_addrmode_is2:$src)>;
1354 def : T1Pat<(atomic_load_16 t_addrmode_rrs2:$src),
1355 (tLDRHr t_addrmode_rrs2:$src)>;
1356 def : T1Pat<(atomic_load_32 t_addrmode_is4:$src),
1357 (tLDRi t_addrmode_is4:$src)>;
1358 def : T1Pat<(atomic_load_32 t_addrmode_rrs4:$src),
1359 (tLDRr t_addrmode_rrs4:$src)>;
1360 def : T1Pat<(atomic_store_8 t_addrmode_is1:$ptr, tGPR:$val),
1361 (tSTRBi tGPR:$val, t_addrmode_is1:$ptr)>;
1362 def : T1Pat<(atomic_store_8 t_addrmode_rrs1:$ptr, tGPR:$val),
1363 (tSTRBr tGPR:$val, t_addrmode_rrs1:$ptr)>;
1364 def : T1Pat<(atomic_store_16 t_addrmode_is2:$ptr, tGPR:$val),
1365 (tSTRHi tGPR:$val, t_addrmode_is2:$ptr)>;
1366 def : T1Pat<(atomic_store_16 t_addrmode_rrs2:$ptr, tGPR:$val),
1367 (tSTRHr tGPR:$val, t_addrmode_rrs2:$ptr)>;
1368 def : T1Pat<(atomic_store_32 t_addrmode_is4:$ptr, tGPR:$val),
1369 (tSTRi tGPR:$val, t_addrmode_is4:$ptr)>;
1370 def : T1Pat<(atomic_store_32 t_addrmode_rrs4:$ptr, tGPR:$val),
1371 (tSTRr tGPR:$val, t_addrmode_rrs4:$ptr)>;
1373 // Large immediate handling.
1376 def : T1Pat<(i32 thumb_immshifted:$src),
1377 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1378 (thumb_immshifted_shamt imm:$src))>;
1380 def : T1Pat<(i32 imm0_255_comp:$src),
1381 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1383 // Pseudo instruction that combines ldr from constpool and add pc. This should
1384 // be expanded into two instructions late to allow if-conversion and
1386 let isReMaterializable = 1 in
1387 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1389 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1391 Requires<[IsThumb, IsThumb1Only]>;
1393 // Pseudo-instruction for merged POP and return.
1394 // FIXME: remove when we have a way to marking a MI with these properties.
1395 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1396 hasExtraDefRegAllocReq = 1 in
1397 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1399 (tPOP pred:$p, reglist:$regs)>;
1401 // Indirect branch using "mov pc, $Rm"
1402 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1403 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p),
1404 2, IIC_Br, [(brind GPR:$Rm)],
1405 (tMOVr PC, GPR:$Rm, pred:$p)>;
1409 // In Thumb1, "nop" is encoded as a "mov r8, r8". Technically, the bf00
1410 // encoding is available on ARMv6K, but we don't differentiate that finely.
1411 def : InstAlias<"nop", (tMOVr R8, R8, 14, 0)>,Requires<[IsThumb, IsThumb1Only]>;
1414 // For round-trip assembly/disassembly, we have to handle a CPS instruction
1415 // without any iflags. That's not, strictly speaking, valid syntax, but it's
1416 // a useful extension and assembles to defined behaviour (the insn does
1418 def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>;
1419 def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>;
1421 // "neg" is and alias for "rsb rd, rn, #0"
1422 def : tInstAlias<"neg${s}${p} $Rd, $Rm",
1423 (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>;
1426 // Implied destination operand forms for shifts.
1427 def : tInstAlias<"lsl${s}${p} $Rdm, $imm",
1428 (tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p)>;
1429 def : tInstAlias<"lsr${s}${p} $Rdm, $imm",
1430 (tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;
1431 def : tInstAlias<"asr${s}${p} $Rdm, $imm",
1432 (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;