1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
20 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
27 // Types for vector shift by immediates. The "SHX" version is for long and
28 // narrow operations where the source and destination vectors have different
29 // types. The "SHINS" version is for shift and insert operations.
30 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
32 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
34 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
37 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
45 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
49 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
56 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
60 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
63 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
65 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
68 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
70 // VDUPLANE can produce a quad-register result from a double-register source,
71 // so the result is not constrained to match the source.
72 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
73 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
76 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
77 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
78 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
80 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
81 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
82 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
83 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
85 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
86 SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>]>;
87 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
88 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
89 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
91 //===----------------------------------------------------------------------===//
92 // NEON operand definitions
93 //===----------------------------------------------------------------------===//
95 // addrmode_neonldstm := reg
97 /* TODO: Take advantage of vldm.
98 def addrmode_neonldstm : Operand<i32>,
99 ComplexPattern<i32, 2, "SelectAddrModeNeonLdStM", []> {
100 let PrintMethod = "printAddrNeonLdStMOperand";
101 let MIOperandInfo = (ops GPR, i32imm);
105 //===----------------------------------------------------------------------===//
106 // NEON load / store instructions
107 //===----------------------------------------------------------------------===//
109 /* TODO: Take advantage of vldm.
111 def VLDMD : NI<(outs),
112 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
114 "vldm${addr:submode} ${addr:base}, $dst1",
116 let Inst{27-25} = 0b110;
118 let Inst{11-9} = 0b101;
121 def VLDMS : NI<(outs),
122 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
124 "vldm${addr:submode} ${addr:base}, $dst1",
126 let Inst{27-25} = 0b110;
128 let Inst{11-9} = 0b101;
133 // Use vldmia to load a Q register as a D register pair.
134 def VLDRQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr),
136 "vldmia $addr, ${dst:dregpair}",
137 [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]> {
138 let Inst{27-25} = 0b110;
139 let Inst{24} = 0; // P bit
140 let Inst{23} = 1; // U bit
142 let Inst{11-9} = 0b101;
145 // Use vstmia to store a Q register as a D register pair.
146 def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr),
148 "vstmia $addr, ${src:dregpair}",
149 [(store (v2f64 QPR:$src), addrmode4:$addr)]> {
150 let Inst{27-25} = 0b110;
151 let Inst{24} = 0; // P bit
152 let Inst{23} = 1; // U bit
154 let Inst{11-9} = 0b101;
157 // VLD1 : Vector Load (multiple single elements)
158 class VLD1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
159 : NLdSt<(outs DPR:$dst), (ins addrmode6:$addr), NoItinerary,
160 !strconcat(OpcodeStr, "\t\\{$dst\\}, $addr"), "",
161 [(set DPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
162 class VLD1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
163 : NLdSt<(outs QPR:$dst), (ins addrmode6:$addr), NoItinerary,
164 !strconcat(OpcodeStr, "\t${dst:dregpair}, $addr"), "",
165 [(set QPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
167 def VLD1d8 : VLD1D<"vld1.8", v8i8, int_arm_neon_vld1>;
168 def VLD1d16 : VLD1D<"vld1.16", v4i16, int_arm_neon_vld1>;
169 def VLD1d32 : VLD1D<"vld1.32", v2i32, int_arm_neon_vld1>;
170 def VLD1df : VLD1D<"vld1.32", v2f32, int_arm_neon_vld1>;
171 def VLD1d64 : VLD1D<"vld1.64", v1i64, int_arm_neon_vld1>;
173 def VLD1q8 : VLD1Q<"vld1.8", v16i8, int_arm_neon_vld1>;
174 def VLD1q16 : VLD1Q<"vld1.16", v8i16, int_arm_neon_vld1>;
175 def VLD1q32 : VLD1Q<"vld1.32", v4i32, int_arm_neon_vld1>;
176 def VLD1qf : VLD1Q<"vld1.32", v4f32, int_arm_neon_vld1>;
177 def VLD1q64 : VLD1Q<"vld1.64", v2i64, int_arm_neon_vld1>;
181 // VLD2 : Vector Load (multiple 2-element structures)
182 class VLD2D<string OpcodeStr>
183 : NLdSt<(outs DPR:$dst1, DPR:$dst2), (ins addrmode6:$addr), NoItinerary,
184 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2\\}, $addr"), "", []>;
186 def VLD2d8 : VLD2D<"vld2.8">;
187 def VLD2d16 : VLD2D<"vld2.16">;
188 def VLD2d32 : VLD2D<"vld2.32">;
190 // VLD3 : Vector Load (multiple 3-element structures)
191 class VLD3D<string OpcodeStr>
192 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3), (ins addrmode6:$addr),
194 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"), "", []>;
196 def VLD3d8 : VLD3D<"vld3.8">;
197 def VLD3d16 : VLD3D<"vld3.16">;
198 def VLD3d32 : VLD3D<"vld3.32">;
200 // VLD4 : Vector Load (multiple 4-element structures)
201 class VLD4D<string OpcodeStr>
202 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
203 (ins addrmode6:$addr), NoItinerary,
204 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"),
207 def VLD4d8 : VLD4D<"vld4.8">;
208 def VLD4d16 : VLD4D<"vld4.16">;
209 def VLD4d32 : VLD4D<"vld4.32">;
212 // VST1 : Vector Store (multiple single elements)
213 class VST1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
214 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src), NoItinerary,
215 !strconcat(OpcodeStr, "\t\\{$src\\}, $addr"), "",
216 [(IntOp addrmode6:$addr, (Ty DPR:$src))]>;
217 class VST1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
218 : NLdSt<(outs), (ins addrmode6:$addr, QPR:$src), NoItinerary,
219 !strconcat(OpcodeStr, "\t${src:dregpair}, $addr"), "",
220 [(IntOp addrmode6:$addr, (Ty QPR:$src))]>;
222 def VST1d8 : VST1D<"vst1.8", v8i8, int_arm_neon_vst1>;
223 def VST1d16 : VST1D<"vst1.16", v4i16, int_arm_neon_vst1>;
224 def VST1d32 : VST1D<"vst1.32", v2i32, int_arm_neon_vst1>;
225 def VST1df : VST1D<"vst1.32", v2f32, int_arm_neon_vst1>;
226 def VST1d64 : VST1D<"vst1.64", v1i64, int_arm_neon_vst1>;
228 def VST1q8 : VST1Q<"vst1.8", v16i8, int_arm_neon_vst1>;
229 def VST1q16 : VST1Q<"vst1.16", v8i16, int_arm_neon_vst1>;
230 def VST1q32 : VST1Q<"vst1.32", v4i32, int_arm_neon_vst1>;
231 def VST1qf : VST1Q<"vst1.32", v4f32, int_arm_neon_vst1>;
232 def VST1q64 : VST1Q<"vst1.64", v2i64, int_arm_neon_vst1>;
234 let mayStore = 1 in {
236 // VST2 : Vector Store (multiple 2-element structures)
237 class VST2D<string OpcodeStr>
238 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2), NoItinerary,
239 !strconcat(OpcodeStr, "\t\\{$src1,$src2\\}, $addr"), "", []>;
241 def VST2d8 : VST2D<"vst2.8">;
242 def VST2d16 : VST2D<"vst2.16">;
243 def VST2d32 : VST2D<"vst2.32">;
245 // VST3 : Vector Store (multiple 3-element structures)
246 class VST3D<string OpcodeStr>
247 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
249 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr"), "", []>;
251 def VST3d8 : VST3D<"vst3.8">;
252 def VST3d16 : VST3D<"vst3.16">;
253 def VST3d32 : VST3D<"vst3.32">;
255 // VST4 : Vector Store (multiple 4-element structures)
256 class VST4D<string OpcodeStr>
257 : NLdSt<(outs), (ins addrmode6:$addr,
258 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), NoItinerary,
259 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"),
262 def VST4d8 : VST4D<"vst4.8">;
263 def VST4d16 : VST4D<"vst4.16">;
264 def VST4d32 : VST4D<"vst4.32">;
268 //===----------------------------------------------------------------------===//
269 // NEON pattern fragments
270 //===----------------------------------------------------------------------===//
272 // Extract D sub-registers of Q registers.
273 // (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6)
274 def DSubReg_i8_reg : SDNodeXForm<imm, [{
275 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
277 def DSubReg_i16_reg : SDNodeXForm<imm, [{
278 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
280 def DSubReg_i32_reg : SDNodeXForm<imm, [{
281 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
283 def DSubReg_f64_reg : SDNodeXForm<imm, [{
284 return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
287 // Extract S sub-registers of Q/D registers.
288 // (arm_ssubreg_0 is 1; arm_ssubreg_1 is 2; etc.)
289 def SSubReg_f32_reg : SDNodeXForm<imm, [{
290 return CurDAG->getTargetConstant(1 + N->getZExtValue(), MVT::i32);
293 // Translate lane numbers from Q registers to D subregs.
294 def SubReg_i8_lane : SDNodeXForm<imm, [{
295 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
297 def SubReg_i16_lane : SDNodeXForm<imm, [{
298 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
300 def SubReg_i32_lane : SDNodeXForm<imm, [{
301 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
304 //===----------------------------------------------------------------------===//
305 // Instruction Classes
306 //===----------------------------------------------------------------------===//
308 // Basic 2-register operations, both double- and quad-register.
309 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
310 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
311 ValueType ResTy, ValueType OpTy, SDNode OpNode>
312 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
313 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
314 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
315 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
316 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
317 ValueType ResTy, ValueType OpTy, SDNode OpNode>
318 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
319 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
320 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
322 // Basic 2-register operations, scalar single-precision.
323 class N2VDs<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
324 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
325 ValueType ResTy, ValueType OpTy, SDNode OpNode>
326 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
327 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
328 NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "", []>;
330 class N2VDsPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
331 : NEONFPPat<(ResTy (OpNode SPR:$a)),
333 (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
336 // Basic 2-register intrinsics, both double- and quad-register.
337 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
338 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
339 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
340 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
341 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
342 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
343 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
344 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
345 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
346 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
347 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
348 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
350 // Basic 2-register intrinsics, scalar single-precision
351 class N2VDInts<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
352 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
353 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
354 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
355 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NoItinerary,
356 !strconcat(OpcodeStr, "\t$dst, $src"), "", []>;
358 class N2VDIntsPat<SDNode OpNode, NeonI Inst>
359 : NEONFPPat<(f32 (OpNode SPR:$a)),
361 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
364 // Narrow 2-register intrinsics.
365 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
366 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
367 string OpcodeStr, ValueType TyD, ValueType TyQ, Intrinsic IntOp>
368 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
369 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
370 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
372 // Long 2-register intrinsics. (This is currently only used for VMOVL and is
373 // derived from N2VImm instead of N2V because of the way the size is encoded.)
374 class N2VLInt<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
375 bit op6, bit op4, string OpcodeStr, ValueType TyQ, ValueType TyD,
377 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4, (outs QPR:$dst),
378 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
379 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>;
381 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
382 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr>
383 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
384 (ins DPR:$src1, DPR:$src2), NoItinerary,
385 !strconcat(OpcodeStr, "\t$dst1, $dst2"),
386 "$src1 = $dst1, $src2 = $dst2", []>;
387 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr>
388 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
389 (ins QPR:$src1, QPR:$src2), NoItinerary,
390 !strconcat(OpcodeStr, "\t$dst1, $dst2"),
391 "$src1 = $dst1, $src2 = $dst2", []>;
393 // Basic 3-register operations, both double- and quad-register.
394 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
395 string OpcodeStr, ValueType ResTy, ValueType OpTy,
396 SDNode OpNode, bit Commutable>
397 : N3V<op24, op23, op21_20, op11_8, 0, op4,
398 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
399 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
400 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
401 let isCommutable = Commutable;
403 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
404 string OpcodeStr, ValueType ResTy, ValueType OpTy,
405 SDNode OpNode, bit Commutable>
406 : N3V<op24, op23, op21_20, op11_8, 1, op4,
407 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
408 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
409 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
410 let isCommutable = Commutable;
413 // Basic 3-register operations, scalar single-precision
414 class N3VDs<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
415 string OpcodeStr, ValueType ResTy, ValueType OpTy,
416 SDNode OpNode, bit Commutable>
417 : N3V<op24, op23, op21_20, op11_8, 0, op4,
418 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), NoItinerary,
419 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", []> {
420 let isCommutable = Commutable;
422 class N3VDsPat<SDNode OpNode, NeonI Inst>
423 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
425 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
426 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
429 // Basic 3-register intrinsics, both double- and quad-register.
430 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
431 string OpcodeStr, ValueType ResTy, ValueType OpTy,
432 Intrinsic IntOp, bit Commutable>
433 : N3V<op24, op23, op21_20, op11_8, 0, op4,
434 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
435 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
436 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
437 let isCommutable = Commutable;
439 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
440 string OpcodeStr, ValueType ResTy, ValueType OpTy,
441 Intrinsic IntOp, bit Commutable>
442 : N3V<op24, op23, op21_20, op11_8, 1, op4,
443 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
444 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
445 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
446 let isCommutable = Commutable;
449 // Multiply-Add/Sub operations, both double- and quad-register.
450 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
451 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
452 : N3V<op24, op23, op21_20, op11_8, 0, op4,
453 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
454 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
455 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
456 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
457 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
458 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
459 : N3V<op24, op23, op21_20, op11_8, 1, op4,
460 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
461 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
462 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
463 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
465 // Multiply-Add/Sub operations, scalar single-precision
466 class N3VDMulOps<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
467 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
468 : N3V<op24, op23, op21_20, op11_8, 0, op4,
469 (outs DPR_VFP2:$dst),
470 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), NoItinerary,
471 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", []>;
473 class N3VDMulOpsPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
474 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
476 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$acc, arm_ssubreg_0),
477 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
478 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
481 // Neon 3-argument intrinsics, both double- and quad-register.
482 // The destination register is also used as the first source operand register.
483 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
484 string OpcodeStr, ValueType ResTy, ValueType OpTy,
486 : N3V<op24, op23, op21_20, op11_8, 0, op4,
487 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
488 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
489 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
490 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
491 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
492 string OpcodeStr, ValueType ResTy, ValueType OpTy,
494 : N3V<op24, op23, op21_20, op11_8, 1, op4,
495 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
496 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
497 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
498 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
500 // Neon Long 3-argument intrinsic. The destination register is
501 // a quad-register and is also used as the first source operand register.
502 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
503 string OpcodeStr, ValueType TyQ, ValueType TyD, Intrinsic IntOp>
504 : N3V<op24, op23, op21_20, op11_8, 0, op4,
505 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
506 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
508 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
510 // Narrowing 3-register intrinsics.
511 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
512 string OpcodeStr, ValueType TyD, ValueType TyQ,
513 Intrinsic IntOp, bit Commutable>
514 : N3V<op24, op23, op21_20, op11_8, 0, op4,
515 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
516 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
517 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
518 let isCommutable = Commutable;
521 // Long 3-register intrinsics.
522 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
523 string OpcodeStr, ValueType TyQ, ValueType TyD,
524 Intrinsic IntOp, bit Commutable>
525 : N3V<op24, op23, op21_20, op11_8, 0, op4,
526 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
527 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
528 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
529 let isCommutable = Commutable;
532 // Wide 3-register intrinsics.
533 class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
534 string OpcodeStr, ValueType TyQ, ValueType TyD,
535 Intrinsic IntOp, bit Commutable>
536 : N3V<op24, op23, op21_20, op11_8, 0, op4,
537 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), NoItinerary,
538 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
539 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
540 let isCommutable = Commutable;
543 // Pairwise long 2-register intrinsics, both double- and quad-register.
544 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
545 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
546 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
547 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
548 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
549 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
550 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
551 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
552 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
553 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
554 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
555 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
557 // Pairwise long 2-register accumulate intrinsics,
558 // both double- and quad-register.
559 // The destination register is also used as the first source operand register.
560 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
561 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
562 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
563 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
564 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
565 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
566 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
567 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
568 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
569 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
570 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
571 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
572 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
573 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
575 // Shift by immediate,
576 // both double- and quad-register.
577 class N2VDSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
578 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode>
579 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
580 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary,
581 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
582 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
583 class N2VQSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
584 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode>
585 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
586 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary,
587 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
588 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
590 // Long shift by immediate.
591 class N2VLSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
592 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
593 ValueType OpTy, SDNode OpNode>
594 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
595 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary,
596 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
597 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
598 (i32 imm:$SIMM))))]>;
600 // Narrow shift by immediate.
601 class N2VNSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
602 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
603 ValueType OpTy, SDNode OpNode>
604 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
605 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary,
606 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
607 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
608 (i32 imm:$SIMM))))]>;
610 // Shift right by immediate and accumulate,
611 // both double- and quad-register.
612 class N2VDShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
613 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
614 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
615 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
617 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
618 [(set DPR:$dst, (Ty (add DPR:$src1,
619 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
620 class N2VQShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
621 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
622 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
623 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
625 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
626 [(set QPR:$dst, (Ty (add QPR:$src1,
627 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
629 // Shift by immediate and insert,
630 // both double- and quad-register.
631 class N2VDShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
632 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
633 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
634 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
636 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
637 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
638 class N2VQShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
639 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
640 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
641 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
643 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
644 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
646 // Convert, with fractional bits immediate,
647 // both double- and quad-register.
648 class N2VCvtD<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
649 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
651 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
652 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary,
653 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
654 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
655 class N2VCvtQ<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
656 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
658 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
659 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary,
660 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
661 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
663 //===----------------------------------------------------------------------===//
665 //===----------------------------------------------------------------------===//
667 // Neon 3-register vector operations.
669 // First with only element sizes of 8, 16 and 32 bits:
670 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
671 string OpcodeStr, SDNode OpNode, bit Commutable = 0> {
672 // 64-bit vector types.
673 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
674 v8i8, v8i8, OpNode, Commutable>;
675 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"),
676 v4i16, v4i16, OpNode, Commutable>;
677 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"),
678 v2i32, v2i32, OpNode, Commutable>;
680 // 128-bit vector types.
681 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
682 v16i8, v16i8, OpNode, Commutable>;
683 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"),
684 v8i16, v8i16, OpNode, Commutable>;
685 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"),
686 v4i32, v4i32, OpNode, Commutable>;
689 // ....then also with element size 64 bits:
690 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
691 string OpcodeStr, SDNode OpNode, bit Commutable = 0>
692 : N3V_QHS<op24, op23, op11_8, op4, OpcodeStr, OpNode, Commutable> {
693 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"),
694 v1i64, v1i64, OpNode, Commutable>;
695 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"),
696 v2i64, v2i64, OpNode, Commutable>;
700 // Neon Narrowing 2-register vector intrinsics,
701 // source operand element sizes of 16, 32 and 64 bits:
702 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
703 bits<5> op11_7, bit op6, bit op4, string OpcodeStr,
705 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
706 !strconcat(OpcodeStr, "16"), v8i8, v8i16, IntOp>;
707 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
708 !strconcat(OpcodeStr, "32"), v4i16, v4i32, IntOp>;
709 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
710 !strconcat(OpcodeStr, "64"), v2i32, v2i64, IntOp>;
714 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
715 // source operand element sizes of 16, 32 and 64 bits:
716 multiclass N2VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
717 bit op4, string OpcodeStr, Intrinsic IntOp> {
718 def v8i16 : N2VLInt<op24, op23, 0b001000, op11_8, op7, op6, op4,
719 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
720 def v4i32 : N2VLInt<op24, op23, 0b010000, op11_8, op7, op6, op4,
721 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
722 def v2i64 : N2VLInt<op24, op23, 0b100000, op11_8, op7, op6, op4,
723 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
727 // Neon 3-register vector intrinsics.
729 // First with only element sizes of 16 and 32 bits:
730 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
731 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
732 // 64-bit vector types.
733 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
734 v4i16, v4i16, IntOp, Commutable>;
735 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
736 v2i32, v2i32, IntOp, Commutable>;
738 // 128-bit vector types.
739 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
740 v8i16, v8i16, IntOp, Commutable>;
741 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
742 v4i32, v4i32, IntOp, Commutable>;
745 // ....then also with element size of 8 bits:
746 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
747 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
748 : N3VInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
749 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
750 v8i8, v8i8, IntOp, Commutable>;
751 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
752 v16i8, v16i8, IntOp, Commutable>;
755 // ....then also with element size of 64 bits:
756 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
757 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
758 : N3VInt_QHS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
759 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"),
760 v1i64, v1i64, IntOp, Commutable>;
761 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"),
762 v2i64, v2i64, IntOp, Commutable>;
766 // Neon Narrowing 3-register vector intrinsics,
767 // source operand element sizes of 16, 32 and 64 bits:
768 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
769 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
770 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr,"16"),
771 v8i8, v8i16, IntOp, Commutable>;
772 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"32"),
773 v4i16, v4i32, IntOp, Commutable>;
774 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"64"),
775 v2i32, v2i64, IntOp, Commutable>;
779 // Neon Long 3-register vector intrinsics.
781 // First with only element sizes of 16 and 32 bits:
782 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
783 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
784 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
785 v4i32, v4i16, IntOp, Commutable>;
786 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
787 v2i64, v2i32, IntOp, Commutable>;
790 // ....then also with element size of 8 bits:
791 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
792 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
793 : N3VLInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
794 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
795 v8i16, v8i8, IntOp, Commutable>;
799 // Neon Wide 3-register vector intrinsics,
800 // source operand element sizes of 8, 16 and 32 bits:
801 multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
802 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
803 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
804 v8i16, v8i8, IntOp, Commutable>;
805 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
806 v4i32, v4i16, IntOp, Commutable>;
807 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
808 v2i64, v2i32, IntOp, Commutable>;
812 // Neon Multiply-Op vector operations,
813 // element sizes of 8, 16 and 32 bits:
814 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
815 string OpcodeStr, SDNode OpNode> {
816 // 64-bit vector types.
817 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4,
818 !strconcat(OpcodeStr, "8"), v8i8, mul, OpNode>;
819 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4,
820 !strconcat(OpcodeStr, "16"), v4i16, mul, OpNode>;
821 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4,
822 !strconcat(OpcodeStr, "32"), v2i32, mul, OpNode>;
824 // 128-bit vector types.
825 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4,
826 !strconcat(OpcodeStr, "8"), v16i8, mul, OpNode>;
827 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4,
828 !strconcat(OpcodeStr, "16"), v8i16, mul, OpNode>;
829 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4,
830 !strconcat(OpcodeStr, "32"), v4i32, mul, OpNode>;
834 // Neon 3-argument intrinsics,
835 // element sizes of 8, 16 and 32 bits:
836 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
837 string OpcodeStr, Intrinsic IntOp> {
838 // 64-bit vector types.
839 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4,
840 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
841 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4,
842 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
843 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4,
844 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
846 // 128-bit vector types.
847 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4,
848 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
849 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4,
850 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
851 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4,
852 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
856 // Neon Long 3-argument intrinsics.
858 // First with only element sizes of 16 and 32 bits:
859 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
860 string OpcodeStr, Intrinsic IntOp> {
861 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4,
862 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
863 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4,
864 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
867 // ....then also with element size of 8 bits:
868 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
869 string OpcodeStr, Intrinsic IntOp>
870 : N3VLInt3_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp> {
871 def v8i16 : N3VLInt3<op24, op23, 0b01, op11_8, op4,
872 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
876 // Neon 2-register vector intrinsics,
877 // element sizes of 8, 16 and 32 bits:
878 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
879 bits<5> op11_7, bit op4, string OpcodeStr,
881 // 64-bit vector types.
882 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
883 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
884 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
885 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
886 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
887 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
889 // 128-bit vector types.
890 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
891 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
892 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
893 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
894 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
895 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
899 // Neon Pairwise long 2-register intrinsics,
900 // element sizes of 8, 16 and 32 bits:
901 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
902 bits<5> op11_7, bit op4,
903 string OpcodeStr, Intrinsic IntOp> {
904 // 64-bit vector types.
905 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
906 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
907 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
908 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
909 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
910 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
912 // 128-bit vector types.
913 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
914 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
915 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
916 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
917 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
918 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
922 // Neon Pairwise long 2-register accumulate intrinsics,
923 // element sizes of 8, 16 and 32 bits:
924 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
925 bits<5> op11_7, bit op4,
926 string OpcodeStr, Intrinsic IntOp> {
927 // 64-bit vector types.
928 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
929 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
930 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
931 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
932 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
933 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
935 // 128-bit vector types.
936 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
937 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
938 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
939 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
940 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
941 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
945 // Neon 2-register vector shift by immediate,
946 // element sizes of 8, 16, 32 and 64 bits:
947 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
948 string OpcodeStr, SDNode OpNode> {
949 // 64-bit vector types.
950 def v8i8 : N2VDSh<op24, op23, 0b001000, op11_8, 0, op4,
951 !strconcat(OpcodeStr, "8"), v8i8, OpNode>;
952 def v4i16 : N2VDSh<op24, op23, 0b010000, op11_8, 0, op4,
953 !strconcat(OpcodeStr, "16"), v4i16, OpNode>;
954 def v2i32 : N2VDSh<op24, op23, 0b100000, op11_8, 0, op4,
955 !strconcat(OpcodeStr, "32"), v2i32, OpNode>;
956 def v1i64 : N2VDSh<op24, op23, 0b000000, op11_8, 1, op4,
957 !strconcat(OpcodeStr, "64"), v1i64, OpNode>;
959 // 128-bit vector types.
960 def v16i8 : N2VQSh<op24, op23, 0b001000, op11_8, 0, op4,
961 !strconcat(OpcodeStr, "8"), v16i8, OpNode>;
962 def v8i16 : N2VQSh<op24, op23, 0b010000, op11_8, 0, op4,
963 !strconcat(OpcodeStr, "16"), v8i16, OpNode>;
964 def v4i32 : N2VQSh<op24, op23, 0b100000, op11_8, 0, op4,
965 !strconcat(OpcodeStr, "32"), v4i32, OpNode>;
966 def v2i64 : N2VQSh<op24, op23, 0b000000, op11_8, 1, op4,
967 !strconcat(OpcodeStr, "64"), v2i64, OpNode>;
971 // Neon Shift-Accumulate vector operations,
972 // element sizes of 8, 16, 32 and 64 bits:
973 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
974 string OpcodeStr, SDNode ShOp> {
975 // 64-bit vector types.
976 def v8i8 : N2VDShAdd<op24, op23, 0b001000, op11_8, 0, op4,
977 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
978 def v4i16 : N2VDShAdd<op24, op23, 0b010000, op11_8, 0, op4,
979 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
980 def v2i32 : N2VDShAdd<op24, op23, 0b100000, op11_8, 0, op4,
981 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
982 def v1i64 : N2VDShAdd<op24, op23, 0b000000, op11_8, 1, op4,
983 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
985 // 128-bit vector types.
986 def v16i8 : N2VQShAdd<op24, op23, 0b001000, op11_8, 0, op4,
987 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
988 def v8i16 : N2VQShAdd<op24, op23, 0b010000, op11_8, 0, op4,
989 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
990 def v4i32 : N2VQShAdd<op24, op23, 0b100000, op11_8, 0, op4,
991 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
992 def v2i64 : N2VQShAdd<op24, op23, 0b000000, op11_8, 1, op4,
993 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
997 // Neon Shift-Insert vector operations,
998 // element sizes of 8, 16, 32 and 64 bits:
999 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1000 string OpcodeStr, SDNode ShOp> {
1001 // 64-bit vector types.
1002 def v8i8 : N2VDShIns<op24, op23, 0b001000, op11_8, 0, op4,
1003 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
1004 def v4i16 : N2VDShIns<op24, op23, 0b010000, op11_8, 0, op4,
1005 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
1006 def v2i32 : N2VDShIns<op24, op23, 0b100000, op11_8, 0, op4,
1007 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
1008 def v1i64 : N2VDShIns<op24, op23, 0b000000, op11_8, 1, op4,
1009 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
1011 // 128-bit vector types.
1012 def v16i8 : N2VQShIns<op24, op23, 0b001000, op11_8, 0, op4,
1013 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
1014 def v8i16 : N2VQShIns<op24, op23, 0b010000, op11_8, 0, op4,
1015 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
1016 def v4i32 : N2VQShIns<op24, op23, 0b100000, op11_8, 0, op4,
1017 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
1018 def v2i64 : N2VQShIns<op24, op23, 0b000000, op11_8, 1, op4,
1019 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
1022 //===----------------------------------------------------------------------===//
1023 // Instruction Definitions.
1024 //===----------------------------------------------------------------------===//
1026 // Vector Add Operations.
1028 // VADD : Vector Add (integer and floating-point)
1029 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, "vadd.i", add, 1>;
1030 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd, 1>;
1031 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, "vadd.f32", v4f32, v4f32, fadd, 1>;
1032 // VADDL : Vector Add Long (Q = D + D)
1033 defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, "vaddl.s", int_arm_neon_vaddls, 1>;
1034 defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, "vaddl.u", int_arm_neon_vaddlu, 1>;
1035 // VADDW : Vector Add Wide (Q = Q + D)
1036 defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw.s", int_arm_neon_vaddws, 0>;
1037 defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw.u", int_arm_neon_vaddwu, 0>;
1038 // VHADD : Vector Halving Add
1039 defm VHADDs : N3VInt_QHS<0,0,0b0000,0, "vhadd.s", int_arm_neon_vhadds, 1>;
1040 defm VHADDu : N3VInt_QHS<1,0,0b0000,0, "vhadd.u", int_arm_neon_vhaddu, 1>;
1041 // VRHADD : Vector Rounding Halving Add
1042 defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, "vrhadd.s", int_arm_neon_vrhadds, 1>;
1043 defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, "vrhadd.u", int_arm_neon_vrhaddu, 1>;
1044 // VQADD : Vector Saturating Add
1045 defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, "vqadd.s", int_arm_neon_vqadds, 1>;
1046 defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, "vqadd.u", int_arm_neon_vqaddu, 1>;
1047 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
1048 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn.i", int_arm_neon_vaddhn, 1>;
1049 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
1050 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn.i", int_arm_neon_vraddhn, 1>;
1052 // Vector Multiply Operations.
1054 // VMUL : Vector Multiply (integer, polynomial and floating-point)
1055 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, "vmul.i", mul, 1>;
1056 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v8i8, v8i8,
1057 int_arm_neon_vmulp, 1>;
1058 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v16i8, v16i8,
1059 int_arm_neon_vmulp, 1>;
1060 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul, 1>;
1061 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, "vmul.f32", v4f32, v4f32, fmul, 1>;
1062 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
1063 defm VQDMULH : N3VInt_HS<0,0,0b1011,0, "vqdmulh.s", int_arm_neon_vqdmulh, 1>;
1064 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
1065 defm VQRDMULH : N3VInt_HS<1,0,0b1011,0, "vqrdmulh.s", int_arm_neon_vqrdmulh, 1>;
1066 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
1067 defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, "vmull.s", int_arm_neon_vmulls, 1>;
1068 defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, "vmull.u", int_arm_neon_vmullu, 1>;
1069 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, "vmull.p8", v8i16, v8i8,
1070 int_arm_neon_vmullp, 1>;
1071 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
1072 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, "vqdmull.s", int_arm_neon_vqdmull, 1>;
1074 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
1076 // VMLA : Vector Multiply Accumulate (integer and floating-point)
1077 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmla.i", add>;
1078 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v2f32, fmul, fadd>;
1079 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v4f32, fmul, fadd>;
1080 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
1081 defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal.s", int_arm_neon_vmlals>;
1082 defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal.u", int_arm_neon_vmlalu>;
1083 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
1084 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal.s", int_arm_neon_vqdmlal>;
1085 // VMLS : Vector Multiply Subtract (integer and floating-point)
1086 defm VMLS : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmls.i", sub>;
1087 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v2f32, fmul, fsub>;
1088 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v4f32, fmul, fsub>;
1089 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
1090 defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl.s", int_arm_neon_vmlsls>;
1091 defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl.u", int_arm_neon_vmlslu>;
1092 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
1093 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl.s", int_arm_neon_vqdmlsl>;
1095 // Vector Subtract Operations.
1097 // VSUB : Vector Subtract (integer and floating-point)
1098 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, "vsub.i", sub, 0>;
1099 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub, 0>;
1100 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, "vsub.f32", v4f32, v4f32, fsub, 0>;
1101 // VSUBL : Vector Subtract Long (Q = D - D)
1102 defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, "vsubl.s", int_arm_neon_vsubls, 1>;
1103 defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, "vsubl.u", int_arm_neon_vsublu, 1>;
1104 // VSUBW : Vector Subtract Wide (Q = Q - D)
1105 defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw.s", int_arm_neon_vsubws, 0>;
1106 defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw.u", int_arm_neon_vsubwu, 0>;
1107 // VHSUB : Vector Halving Subtract
1108 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, "vhsub.s", int_arm_neon_vhsubs, 0>;
1109 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, "vhsub.u", int_arm_neon_vhsubu, 0>;
1110 // VQSUB : Vector Saturing Subtract
1111 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, "vqsub.s", int_arm_neon_vqsubs, 0>;
1112 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, "vqsub.u", int_arm_neon_vqsubu, 0>;
1113 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
1114 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn.i", int_arm_neon_vsubhn, 0>;
1115 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
1116 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn.i", int_arm_neon_vrsubhn, 0>;
1118 // Vector Comparisons.
1120 // VCEQ : Vector Compare Equal
1121 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, "vceq.i", NEONvceq, 1>;
1122 def VCEQfd : N3VD<0,0,0b00,0b1110,0, "vceq.f32", v2i32, v2f32, NEONvceq, 1>;
1123 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, "vceq.f32", v4i32, v4f32, NEONvceq, 1>;
1124 // VCGE : Vector Compare Greater Than or Equal
1125 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, "vcge.s", NEONvcge, 0>;
1126 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, "vcge.u", NEONvcgeu, 0>;
1127 def VCGEfd : N3VD<1,0,0b00,0b1110,0, "vcge.f32", v2i32, v2f32, NEONvcge, 0>;
1128 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, "vcge.f32", v4i32, v4f32, NEONvcge, 0>;
1129 // VCGT : Vector Compare Greater Than
1130 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, "vcgt.s", NEONvcgt, 0>;
1131 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, "vcgt.u", NEONvcgtu, 0>;
1132 def VCGTfd : N3VD<1,0,0b10,0b1110,0, "vcgt.f32", v2i32, v2f32, NEONvcgt, 0>;
1133 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, "vcgt.f32", v4i32, v4f32, NEONvcgt, 0>;
1134 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
1135 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v2i32, v2f32,
1136 int_arm_neon_vacged, 0>;
1137 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v4i32, v4f32,
1138 int_arm_neon_vacgeq, 0>;
1139 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
1140 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v2i32, v2f32,
1141 int_arm_neon_vacgtd, 0>;
1142 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v4i32, v4f32,
1143 int_arm_neon_vacgtq, 0>;
1144 // VTST : Vector Test Bits
1145 defm VTST : N3V_QHS<0, 0, 0b1000, 1, "vtst.i", NEONvtst, 1>;
1147 // Vector Bitwise Operations.
1149 // VAND : Vector Bitwise AND
1150 def VANDd : N3VD<0, 0, 0b00, 0b0001, 1, "vand", v2i32, v2i32, and, 1>;
1151 def VANDq : N3VQ<0, 0, 0b00, 0b0001, 1, "vand", v4i32, v4i32, and, 1>;
1153 // VEOR : Vector Bitwise Exclusive OR
1154 def VEORd : N3VD<1, 0, 0b00, 0b0001, 1, "veor", v2i32, v2i32, xor, 1>;
1155 def VEORq : N3VQ<1, 0, 0b00, 0b0001, 1, "veor", v4i32, v4i32, xor, 1>;
1157 // VORR : Vector Bitwise OR
1158 def VORRd : N3VD<0, 0, 0b10, 0b0001, 1, "vorr", v2i32, v2i32, or, 1>;
1159 def VORRq : N3VQ<0, 0, 0b10, 0b0001, 1, "vorr", v4i32, v4i32, or, 1>;
1161 // VBIC : Vector Bitwise Bit Clear (AND NOT)
1162 def VBICd : N3V<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1163 (ins DPR:$src1, DPR:$src2), NoItinerary,
1164 "vbic\t$dst, $src1, $src2", "",
1165 [(set DPR:$dst, (v2i32 (and DPR:$src1,(vnot DPR:$src2))))]>;
1166 def VBICq : N3V<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1167 (ins QPR:$src1, QPR:$src2), NoItinerary,
1168 "vbic\t$dst, $src1, $src2", "",
1169 [(set QPR:$dst, (v4i32 (and QPR:$src1,(vnot QPR:$src2))))]>;
1171 // VORN : Vector Bitwise OR NOT
1172 def VORNd : N3V<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
1173 (ins DPR:$src1, DPR:$src2), NoItinerary,
1174 "vorn\t$dst, $src1, $src2", "",
1175 [(set DPR:$dst, (v2i32 (or DPR:$src1, (vnot DPR:$src2))))]>;
1176 def VORNq : N3V<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
1177 (ins QPR:$src1, QPR:$src2), NoItinerary,
1178 "vorn\t$dst, $src1, $src2", "",
1179 [(set QPR:$dst, (v4i32 (or QPR:$src1, (vnot QPR:$src2))))]>;
1181 // VMVN : Vector Bitwise NOT
1182 def VMVNd : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
1183 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1184 "vmvn\t$dst, $src", "",
1185 [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>;
1186 def VMVNq : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
1187 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1188 "vmvn\t$dst, $src", "",
1189 [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>;
1190 def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>;
1191 def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>;
1193 // VBSL : Vector Bitwise Select
1194 def VBSLd : N3V<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1195 (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
1196 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1198 (v2i32 (or (and DPR:$src2, DPR:$src1),
1199 (and DPR:$src3, (vnot DPR:$src1)))))]>;
1200 def VBSLq : N3V<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1201 (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
1202 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1204 (v4i32 (or (and QPR:$src2, QPR:$src1),
1205 (and QPR:$src3, (vnot QPR:$src1)))))]>;
1207 // VBIF : Vector Bitwise Insert if False
1208 // like VBSL but with: "vbif\t$dst, $src3, $src1", "$src2 = $dst",
1209 // VBIT : Vector Bitwise Insert if True
1210 // like VBSL but with: "vbit\t$dst, $src2, $src1", "$src3 = $dst",
1211 // These are not yet implemented. The TwoAddress pass will not go looking
1212 // for equivalent operations with different register constraints; it just
1215 // Vector Absolute Differences.
1217 // VABD : Vector Absolute Difference
1218 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, "vabd.s", int_arm_neon_vabds, 0>;
1219 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, "vabd.u", int_arm_neon_vabdu, 0>;
1220 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v2f32, v2f32,
1221 int_arm_neon_vabds, 0>;
1222 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v4f32, v4f32,
1223 int_arm_neon_vabds, 0>;
1225 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
1226 defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, "vabdl.s", int_arm_neon_vabdls, 0>;
1227 defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, "vabdl.u", int_arm_neon_vabdlu, 0>;
1229 // VABA : Vector Absolute Difference and Accumulate
1230 defm VABAs : N3VInt3_QHS<0,1,0b0101,0, "vaba.s", int_arm_neon_vabas>;
1231 defm VABAu : N3VInt3_QHS<1,1,0b0101,0, "vaba.u", int_arm_neon_vabau>;
1233 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
1234 defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, "vabal.s", int_arm_neon_vabals>;
1235 defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal.u", int_arm_neon_vabalu>;
1237 // Vector Maximum and Minimum.
1239 // VMAX : Vector Maximum
1240 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, "vmax.s", int_arm_neon_vmaxs, 1>;
1241 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, "vmax.u", int_arm_neon_vmaxu, 1>;
1242 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v2f32, v2f32,
1243 int_arm_neon_vmaxs, 1>;
1244 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v4f32, v4f32,
1245 int_arm_neon_vmaxs, 1>;
1247 // VMIN : Vector Minimum
1248 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, "vmin.s", int_arm_neon_vmins, 1>;
1249 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, "vmin.u", int_arm_neon_vminu, 1>;
1250 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v2f32, v2f32,
1251 int_arm_neon_vmins, 1>;
1252 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v4f32, v4f32,
1253 int_arm_neon_vmins, 1>;
1255 // Vector Pairwise Operations.
1257 // VPADD : Vector Pairwise Add
1258 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, "vpadd.i8", v8i8, v8i8,
1259 int_arm_neon_vpadd, 0>;
1260 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, "vpadd.i16", v4i16, v4i16,
1261 int_arm_neon_vpadd, 0>;
1262 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, "vpadd.i32", v2i32, v2i32,
1263 int_arm_neon_vpadd, 0>;
1264 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, "vpadd.f32", v2f32, v2f32,
1265 int_arm_neon_vpadd, 0>;
1267 // VPADDL : Vector Pairwise Add Long
1268 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl.s",
1269 int_arm_neon_vpaddls>;
1270 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl.u",
1271 int_arm_neon_vpaddlu>;
1273 // VPADAL : Vector Pairwise Add and Accumulate Long
1274 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpadal.s",
1275 int_arm_neon_vpadals>;
1276 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpadal.u",
1277 int_arm_neon_vpadalu>;
1279 // VPMAX : Vector Pairwise Maximum
1280 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, "vpmax.s8", v8i8, v8i8,
1281 int_arm_neon_vpmaxs, 0>;
1282 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, "vpmax.s16", v4i16, v4i16,
1283 int_arm_neon_vpmaxs, 0>;
1284 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, "vpmax.s32", v2i32, v2i32,
1285 int_arm_neon_vpmaxs, 0>;
1286 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, "vpmax.u8", v8i8, v8i8,
1287 int_arm_neon_vpmaxu, 0>;
1288 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, "vpmax.u16", v4i16, v4i16,
1289 int_arm_neon_vpmaxu, 0>;
1290 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, "vpmax.u32", v2i32, v2i32,
1291 int_arm_neon_vpmaxu, 0>;
1292 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, "vpmax.f32", v2f32, v2f32,
1293 int_arm_neon_vpmaxs, 0>;
1295 // VPMIN : Vector Pairwise Minimum
1296 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, "vpmin.s8", v8i8, v8i8,
1297 int_arm_neon_vpmins, 0>;
1298 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, "vpmin.s16", v4i16, v4i16,
1299 int_arm_neon_vpmins, 0>;
1300 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, "vpmin.s32", v2i32, v2i32,
1301 int_arm_neon_vpmins, 0>;
1302 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, "vpmin.u8", v8i8, v8i8,
1303 int_arm_neon_vpminu, 0>;
1304 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, "vpmin.u16", v4i16, v4i16,
1305 int_arm_neon_vpminu, 0>;
1306 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, "vpmin.u32", v2i32, v2i32,
1307 int_arm_neon_vpminu, 0>;
1308 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, "vpmin.f32", v2f32, v2f32,
1309 int_arm_neon_vpmins, 0>;
1311 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
1313 // VRECPE : Vector Reciprocal Estimate
1314 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32",
1315 v2i32, v2i32, int_arm_neon_vrecpe>;
1316 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32",
1317 v4i32, v4i32, int_arm_neon_vrecpe>;
1318 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32",
1319 v2f32, v2f32, int_arm_neon_vrecpe>;
1320 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32",
1321 v4f32, v4f32, int_arm_neon_vrecpe>;
1323 // VRECPS : Vector Reciprocal Step
1324 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v2f32, v2f32,
1325 int_arm_neon_vrecps, 1>;
1326 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v4f32, v4f32,
1327 int_arm_neon_vrecps, 1>;
1329 // VRSQRTE : Vector Reciprocal Square Root Estimate
1330 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32",
1331 v2i32, v2i32, int_arm_neon_vrsqrte>;
1332 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32",
1333 v4i32, v4i32, int_arm_neon_vrsqrte>;
1334 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32",
1335 v2f32, v2f32, int_arm_neon_vrsqrte>;
1336 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32",
1337 v4f32, v4f32, int_arm_neon_vrsqrte>;
1339 // VRSQRTS : Vector Reciprocal Square Root Step
1340 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v2f32, v2f32,
1341 int_arm_neon_vrsqrts, 1>;
1342 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v4f32, v4f32,
1343 int_arm_neon_vrsqrts, 1>;
1347 // VSHL : Vector Shift
1348 defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, "vshl.s", int_arm_neon_vshifts, 0>;
1349 defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, "vshl.u", int_arm_neon_vshiftu, 0>;
1350 // VSHL : Vector Shift Left (Immediate)
1351 defm VSHLi : N2VSh_QHSD<0, 1, 0b0111, 1, "vshl.i", NEONvshl>;
1352 // VSHR : Vector Shift Right (Immediate)
1353 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, "vshr.s", NEONvshrs>;
1354 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, "vshr.u", NEONvshru>;
1356 // VSHLL : Vector Shift Left Long
1357 def VSHLLs8 : N2VLSh<0, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.s8",
1358 v8i16, v8i8, NEONvshlls>;
1359 def VSHLLs16 : N2VLSh<0, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.s16",
1360 v4i32, v4i16, NEONvshlls>;
1361 def VSHLLs32 : N2VLSh<0, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.s32",
1362 v2i64, v2i32, NEONvshlls>;
1363 def VSHLLu8 : N2VLSh<1, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.u8",
1364 v8i16, v8i8, NEONvshllu>;
1365 def VSHLLu16 : N2VLSh<1, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.u16",
1366 v4i32, v4i16, NEONvshllu>;
1367 def VSHLLu32 : N2VLSh<1, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.u32",
1368 v2i64, v2i32, NEONvshllu>;
1370 // VSHLL : Vector Shift Left Long (with maximum shift count)
1371 def VSHLLi8 : N2VLSh<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll.i8",
1372 v8i16, v8i8, NEONvshlli>;
1373 def VSHLLi16 : N2VLSh<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll.i16",
1374 v4i32, v4i16, NEONvshlli>;
1375 def VSHLLi32 : N2VLSh<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll.i32",
1376 v2i64, v2i32, NEONvshlli>;
1378 // VSHRN : Vector Shift Right and Narrow
1379 def VSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 0, 1, "vshrn.i16",
1380 v8i8, v8i16, NEONvshrn>;
1381 def VSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 0, 1, "vshrn.i32",
1382 v4i16, v4i32, NEONvshrn>;
1383 def VSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 0, 1, "vshrn.i64",
1384 v2i32, v2i64, NEONvshrn>;
1386 // VRSHL : Vector Rounding Shift
1387 defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, "vrshl.s", int_arm_neon_vrshifts, 0>;
1388 defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, "vrshl.u", int_arm_neon_vrshiftu, 0>;
1389 // VRSHR : Vector Rounding Shift Right
1390 defm VRSHRs : N2VSh_QHSD<0, 1, 0b0010, 1, "vrshr.s", NEONvrshrs>;
1391 defm VRSHRu : N2VSh_QHSD<1, 1, 0b0010, 1, "vrshr.u", NEONvrshru>;
1393 // VRSHRN : Vector Rounding Shift Right and Narrow
1394 def VRSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 1, 1, "vrshrn.i16",
1395 v8i8, v8i16, NEONvrshrn>;
1396 def VRSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 1, 1, "vrshrn.i32",
1397 v4i16, v4i32, NEONvrshrn>;
1398 def VRSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 1, 1, "vrshrn.i64",
1399 v2i32, v2i64, NEONvrshrn>;
1401 // VQSHL : Vector Saturating Shift
1402 defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, "vqshl.s", int_arm_neon_vqshifts, 0>;
1403 defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, "vqshl.u", int_arm_neon_vqshiftu, 0>;
1404 // VQSHL : Vector Saturating Shift Left (Immediate)
1405 defm VQSHLsi : N2VSh_QHSD<0, 1, 0b0111, 1, "vqshl.s", NEONvqshls>;
1406 defm VQSHLui : N2VSh_QHSD<1, 1, 0b0111, 1, "vqshl.u", NEONvqshlu>;
1407 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
1408 defm VQSHLsu : N2VSh_QHSD<1, 1, 0b0110, 1, "vqshlu.s", NEONvqshlsu>;
1410 // VQSHRN : Vector Saturating Shift Right and Narrow
1411 def VQSHRNs16 : N2VNSh<0, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.s16",
1412 v8i8, v8i16, NEONvqshrns>;
1413 def VQSHRNs32 : N2VNSh<0, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.s32",
1414 v4i16, v4i32, NEONvqshrns>;
1415 def VQSHRNs64 : N2VNSh<0, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.s64",
1416 v2i32, v2i64, NEONvqshrns>;
1417 def VQSHRNu16 : N2VNSh<1, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.u16",
1418 v8i8, v8i16, NEONvqshrnu>;
1419 def VQSHRNu32 : N2VNSh<1, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.u32",
1420 v4i16, v4i32, NEONvqshrnu>;
1421 def VQSHRNu64 : N2VNSh<1, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.u64",
1422 v2i32, v2i64, NEONvqshrnu>;
1424 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
1425 def VQSHRUN16 : N2VNSh<1, 1, 0b001000, 0b1000, 0, 0, 1, "vqshrun.s16",
1426 v8i8, v8i16, NEONvqshrnsu>;
1427 def VQSHRUN32 : N2VNSh<1, 1, 0b010000, 0b1000, 0, 0, 1, "vqshrun.s32",
1428 v4i16, v4i32, NEONvqshrnsu>;
1429 def VQSHRUN64 : N2VNSh<1, 1, 0b100000, 0b1000, 0, 0, 1, "vqshrun.s64",
1430 v2i32, v2i64, NEONvqshrnsu>;
1432 // VQRSHL : Vector Saturating Rounding Shift
1433 defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, "vqrshl.s",
1434 int_arm_neon_vqrshifts, 0>;
1435 defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, "vqrshl.u",
1436 int_arm_neon_vqrshiftu, 0>;
1438 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
1439 def VQRSHRNs16: N2VNSh<0, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.s16",
1440 v8i8, v8i16, NEONvqrshrns>;
1441 def VQRSHRNs32: N2VNSh<0, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.s32",
1442 v4i16, v4i32, NEONvqrshrns>;
1443 def VQRSHRNs64: N2VNSh<0, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.s64",
1444 v2i32, v2i64, NEONvqrshrns>;
1445 def VQRSHRNu16: N2VNSh<1, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.u16",
1446 v8i8, v8i16, NEONvqrshrnu>;
1447 def VQRSHRNu32: N2VNSh<1, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.u32",
1448 v4i16, v4i32, NEONvqrshrnu>;
1449 def VQRSHRNu64: N2VNSh<1, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.u64",
1450 v2i32, v2i64, NEONvqrshrnu>;
1452 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
1453 def VQRSHRUN16: N2VNSh<1, 1, 0b001000, 0b1000, 0, 1, 1, "vqrshrun.s16",
1454 v8i8, v8i16, NEONvqrshrnsu>;
1455 def VQRSHRUN32: N2VNSh<1, 1, 0b010000, 0b1000, 0, 1, 1, "vqrshrun.s32",
1456 v4i16, v4i32, NEONvqrshrnsu>;
1457 def VQRSHRUN64: N2VNSh<1, 1, 0b100000, 0b1000, 0, 1, 1, "vqrshrun.s64",
1458 v2i32, v2i64, NEONvqrshrnsu>;
1460 // VSRA : Vector Shift Right and Accumulate
1461 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra.s", NEONvshrs>;
1462 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra.u", NEONvshru>;
1463 // VRSRA : Vector Rounding Shift Right and Accumulate
1464 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra.s", NEONvrshrs>;
1465 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra.u", NEONvrshru>;
1467 // VSLI : Vector Shift Left and Insert
1468 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli.", NEONvsli>;
1469 // VSRI : Vector Shift Right and Insert
1470 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri.", NEONvsri>;
1472 // Vector Absolute and Saturating Absolute.
1474 // VABS : Vector Absolute Value
1475 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0, "vabs.s",
1477 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
1478 v2f32, v2f32, int_arm_neon_vabs>;
1479 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
1480 v4f32, v4f32, int_arm_neon_vabs>;
1482 // VQABS : Vector Saturating Absolute Value
1483 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0, "vqabs.s",
1484 int_arm_neon_vqabs>;
1488 def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
1489 def vneg_conv : PatFrag<(ops node:$in), (sub immAllZerosV_bc, node:$in)>;
1491 class VNEGD<bits<2> size, string OpcodeStr, ValueType Ty>
1492 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
1494 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1495 [(set DPR:$dst, (Ty (vneg DPR:$src)))]>;
1496 class VNEGQ<bits<2> size, string OpcodeStr, ValueType Ty>
1497 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
1499 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1500 [(set QPR:$dst, (Ty (vneg QPR:$src)))]>;
1502 // VNEG : Vector Negate
1503 def VNEGs8d : VNEGD<0b00, "vneg.s8", v8i8>;
1504 def VNEGs16d : VNEGD<0b01, "vneg.s16", v4i16>;
1505 def VNEGs32d : VNEGD<0b10, "vneg.s32", v2i32>;
1506 def VNEGs8q : VNEGQ<0b00, "vneg.s8", v16i8>;
1507 def VNEGs16q : VNEGQ<0b01, "vneg.s16", v8i16>;
1508 def VNEGs32q : VNEGQ<0b10, "vneg.s32", v4i32>;
1510 // VNEG : Vector Negate (floating-point)
1511 def VNEGf32d : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
1512 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1513 "vneg.f32\t$dst, $src", "",
1514 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
1515 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
1516 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1517 "vneg.f32\t$dst, $src", "",
1518 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
1520 def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>;
1521 def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>;
1522 def : Pat<(v2i32 (vneg_conv DPR:$src)), (VNEGs32d DPR:$src)>;
1523 def : Pat<(v16i8 (vneg_conv QPR:$src)), (VNEGs8q QPR:$src)>;
1524 def : Pat<(v8i16 (vneg_conv QPR:$src)), (VNEGs16q QPR:$src)>;
1525 def : Pat<(v4i32 (vneg_conv QPR:$src)), (VNEGs32q QPR:$src)>;
1527 // VQNEG : Vector Saturating Negate
1528 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0, "vqneg.s",
1529 int_arm_neon_vqneg>;
1531 // Vector Bit Counting Operations.
1533 // VCLS : Vector Count Leading Sign Bits
1534 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0, "vcls.s",
1536 // VCLZ : Vector Count Leading Zeros
1537 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0, "vclz.i",
1539 // VCNT : Vector Count One Bits
1540 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
1541 v8i8, v8i8, int_arm_neon_vcnt>;
1542 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
1543 v16i8, v16i8, int_arm_neon_vcnt>;
1545 // Vector Move Operations.
1547 // VMOV : Vector Move (Register)
1549 def VMOVD : N3V<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
1550 NoItinerary, "vmov\t$dst, $src", "", []>;
1551 def VMOVQ : N3V<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
1552 NoItinerary, "vmov\t$dst, $src", "", []>;
1554 // VMOV : Vector Move (Immediate)
1556 // VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm.
1557 def VMOV_get_imm8 : SDNodeXForm<build_vector, [{
1558 return ARM::getVMOVImm(N, 1, *CurDAG);
1560 def vmovImm8 : PatLeaf<(build_vector), [{
1561 return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0;
1564 // VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm.
1565 def VMOV_get_imm16 : SDNodeXForm<build_vector, [{
1566 return ARM::getVMOVImm(N, 2, *CurDAG);
1568 def vmovImm16 : PatLeaf<(build_vector), [{
1569 return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0;
1570 }], VMOV_get_imm16>;
1572 // VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm.
1573 def VMOV_get_imm32 : SDNodeXForm<build_vector, [{
1574 return ARM::getVMOVImm(N, 4, *CurDAG);
1576 def vmovImm32 : PatLeaf<(build_vector), [{
1577 return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0;
1578 }], VMOV_get_imm32>;
1580 // VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm.
1581 def VMOV_get_imm64 : SDNodeXForm<build_vector, [{
1582 return ARM::getVMOVImm(N, 8, *CurDAG);
1584 def vmovImm64 : PatLeaf<(build_vector), [{
1585 return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0;
1586 }], VMOV_get_imm64>;
1588 // Note: Some of the cmode bits in the following VMOV instructions need to
1589 // be encoded based on the immed values.
1591 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
1592 (ins i8imm:$SIMM), NoItinerary,
1593 "vmov.i8\t$dst, $SIMM", "",
1594 [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>;
1595 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
1596 (ins i8imm:$SIMM), NoItinerary,
1597 "vmov.i8\t$dst, $SIMM", "",
1598 [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>;
1600 def VMOVv4i16 : N1ModImm<1, 0b000, 0b1000, 0, 0, 0, 1, (outs DPR:$dst),
1601 (ins i16imm:$SIMM), NoItinerary,
1602 "vmov.i16\t$dst, $SIMM", "",
1603 [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>;
1604 def VMOVv8i16 : N1ModImm<1, 0b000, 0b1000, 0, 1, 0, 1, (outs QPR:$dst),
1605 (ins i16imm:$SIMM), NoItinerary,
1606 "vmov.i16\t$dst, $SIMM", "",
1607 [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>;
1609 def VMOVv2i32 : N1ModImm<1, 0b000, 0b0000, 0, 0, 0, 1, (outs DPR:$dst),
1610 (ins i32imm:$SIMM), NoItinerary,
1611 "vmov.i32\t$dst, $SIMM", "",
1612 [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>;
1613 def VMOVv4i32 : N1ModImm<1, 0b000, 0b0000, 0, 1, 0, 1, (outs QPR:$dst),
1614 (ins i32imm:$SIMM), NoItinerary,
1615 "vmov.i32\t$dst, $SIMM", "",
1616 [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>;
1618 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
1619 (ins i64imm:$SIMM), NoItinerary,
1620 "vmov.i64\t$dst, $SIMM", "",
1621 [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>;
1622 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
1623 (ins i64imm:$SIMM), NoItinerary,
1624 "vmov.i64\t$dst, $SIMM", "",
1625 [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>;
1627 // VMOV : Vector Get Lane (move scalar to ARM core register)
1629 def VGETLNs8 : NVGetLane<0b11100101, 0b1011, 0b00,
1630 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
1631 NoItinerary, "vmov", ".s8\t$dst, $src[$lane]",
1632 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
1634 def VGETLNs16 : NVGetLane<0b11100001, 0b1011, 0b01,
1635 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
1636 NoItinerary, "vmov", ".s16\t$dst, $src[$lane]",
1637 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
1639 def VGETLNu8 : NVGetLane<0b11101101, 0b1011, 0b00,
1640 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
1641 NoItinerary, "vmov", ".u8\t$dst, $src[$lane]",
1642 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
1644 def VGETLNu16 : NVGetLane<0b11101001, 0b1011, 0b01,
1645 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
1646 NoItinerary, "vmov", ".u16\t$dst, $src[$lane]",
1647 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
1649 def VGETLNi32 : NVGetLane<0b11100001, 0b1011, 0b00,
1650 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
1651 NoItinerary, "vmov", ".32\t$dst, $src[$lane]",
1652 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
1654 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
1655 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
1656 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
1657 (DSubReg_i8_reg imm:$lane))),
1658 (SubReg_i8_lane imm:$lane))>;
1659 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
1660 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
1661 (DSubReg_i16_reg imm:$lane))),
1662 (SubReg_i16_lane imm:$lane))>;
1663 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
1664 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
1665 (DSubReg_i8_reg imm:$lane))),
1666 (SubReg_i8_lane imm:$lane))>;
1667 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
1668 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
1669 (DSubReg_i16_reg imm:$lane))),
1670 (SubReg_i16_lane imm:$lane))>;
1671 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
1672 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
1673 (DSubReg_i32_reg imm:$lane))),
1674 (SubReg_i32_lane imm:$lane))>;
1675 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
1676 (EXTRACT_SUBREG DPR:$src1, (SSubReg_f32_reg imm:$src2))>;
1677 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
1678 (EXTRACT_SUBREG QPR:$src1, (SSubReg_f32_reg imm:$src2))>;
1679 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
1680 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
1681 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
1682 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
1685 // VMOV : Vector Set Lane (move ARM core register to scalar)
1687 let Constraints = "$src1 = $dst" in {
1688 def VSETLNi8 : NVSetLane<0b11100100, 0b1011, 0b00, (outs DPR:$dst),
1689 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
1690 NoItinerary, "vmov", ".8\t$dst[$lane], $src2",
1691 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
1692 GPR:$src2, imm:$lane))]>;
1693 def VSETLNi16 : NVSetLane<0b11100000, 0b1011, 0b01, (outs DPR:$dst),
1694 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
1695 NoItinerary, "vmov", ".16\t$dst[$lane], $src2",
1696 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
1697 GPR:$src2, imm:$lane))]>;
1698 def VSETLNi32 : NVSetLane<0b11100000, 0b1011, 0b00, (outs DPR:$dst),
1699 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
1700 NoItinerary, "vmov", ".32\t$dst[$lane], $src2",
1701 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
1702 GPR:$src2, imm:$lane))]>;
1704 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
1705 (v16i8 (INSERT_SUBREG QPR:$src1,
1706 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
1707 (DSubReg_i8_reg imm:$lane))),
1708 GPR:$src2, (SubReg_i8_lane imm:$lane)),
1709 (DSubReg_i8_reg imm:$lane)))>;
1710 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
1711 (v8i16 (INSERT_SUBREG QPR:$src1,
1712 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
1713 (DSubReg_i16_reg imm:$lane))),
1714 GPR:$src2, (SubReg_i16_lane imm:$lane)),
1715 (DSubReg_i16_reg imm:$lane)))>;
1716 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
1717 (v4i32 (INSERT_SUBREG QPR:$src1,
1718 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
1719 (DSubReg_i32_reg imm:$lane))),
1720 GPR:$src2, (SubReg_i32_lane imm:$lane)),
1721 (DSubReg_i32_reg imm:$lane)))>;
1723 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
1724 (INSERT_SUBREG QPR:$src1, SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
1726 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
1727 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
1728 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
1729 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
1731 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
1732 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
1733 def : Pat<(v2f64 (scalar_to_vector DPR:$src)),
1734 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, arm_dsubreg_0)>;
1735 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
1736 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
1738 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
1739 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
1740 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
1741 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
1742 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
1743 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
1745 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
1746 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1747 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
1749 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
1750 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1751 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
1753 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
1754 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1755 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
1758 // VDUP : Vector Duplicate (from ARM core register to all elements)
1760 class VDUPD<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
1761 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
1762 NoItinerary, "vdup", !strconcat(asmSize, "\t$dst, $src"),
1763 [(set DPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
1764 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
1765 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
1766 NoItinerary, "vdup", !strconcat(asmSize, "\t$dst, $src"),
1767 [(set QPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
1769 def VDUP8d : VDUPD<0b11101100, 0b00, ".8", v8i8>;
1770 def VDUP16d : VDUPD<0b11101000, 0b01, ".16", v4i16>;
1771 def VDUP32d : VDUPD<0b11101000, 0b00, ".32", v2i32>;
1772 def VDUP8q : VDUPQ<0b11101110, 0b00, ".8", v16i8>;
1773 def VDUP16q : VDUPQ<0b11101010, 0b01, ".16", v8i16>;
1774 def VDUP32q : VDUPQ<0b11101010, 0b00, ".32", v4i32>;
1776 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
1777 NoItinerary, "vdup", ".32\t$dst, $src",
1778 [(set DPR:$dst, (v2f32 (NEONvdup
1779 (f32 (bitconvert GPR:$src)))))]>;
1780 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
1781 NoItinerary, "vdup", ".32\t$dst, $src",
1782 [(set QPR:$dst, (v4f32 (NEONvdup
1783 (f32 (bitconvert GPR:$src)))))]>;
1785 // VDUP : Vector Duplicate Lane (from scalar to all elements)
1787 class VDUPLND<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, ValueType Ty>
1788 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
1789 (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane), NoItinerary,
1790 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
1791 [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
1793 class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr,
1794 ValueType ResTy, ValueType OpTy>
1795 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
1796 (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane), NoItinerary,
1797 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
1798 [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src), imm:$lane)))]>;
1800 def VDUPLN8d : VDUPLND<0b00, 0b01, "vdup.8", v8i8>;
1801 def VDUPLN16d : VDUPLND<0b00, 0b10, "vdup.16", v4i16>;
1802 def VDUPLN32d : VDUPLND<0b01, 0b00, "vdup.32", v2i32>;
1803 def VDUPLNfd : VDUPLND<0b01, 0b00, "vdup.32", v2f32>;
1804 def VDUPLN8q : VDUPLNQ<0b00, 0b01, "vdup.8", v16i8, v8i8>;
1805 def VDUPLN16q : VDUPLNQ<0b00, 0b10, "vdup.16", v8i16, v4i16>;
1806 def VDUPLN32q : VDUPLNQ<0b01, 0b00, "vdup.32", v4i32, v2i32>;
1807 def VDUPLNfq : VDUPLNQ<0b01, 0b00, "vdup.32", v4f32, v2f32>;
1809 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
1810 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
1811 (DSubReg_i8_reg imm:$lane))),
1812 (SubReg_i8_lane imm:$lane)))>;
1813 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
1814 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
1815 (DSubReg_i16_reg imm:$lane))),
1816 (SubReg_i16_lane imm:$lane)))>;
1817 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
1818 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
1819 (DSubReg_i32_reg imm:$lane))),
1820 (SubReg_i32_lane imm:$lane)))>;
1821 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
1822 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src,
1823 (DSubReg_i32_reg imm:$lane))),
1824 (SubReg_i32_lane imm:$lane)))>;
1826 def VDUPfdf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 0, 0,
1827 (outs DPR:$dst), (ins SPR:$src),
1828 NoItinerary, "vdup.32\t$dst, ${src:lane}", "",
1829 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
1831 def VDUPfqf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 1, 0,
1832 (outs QPR:$dst), (ins SPR:$src),
1833 NoItinerary, "vdup.32\t$dst, ${src:lane}", "",
1834 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
1836 // VMOVN : Vector Narrowing Move
1837 defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, "vmovn.i",
1838 int_arm_neon_vmovn>;
1839 // VQMOVN : Vector Saturating Narrowing Move
1840 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, "vqmovn.s",
1841 int_arm_neon_vqmovns>;
1842 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, "vqmovn.u",
1843 int_arm_neon_vqmovnu>;
1844 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, "vqmovun.s",
1845 int_arm_neon_vqmovnsu>;
1846 // VMOVL : Vector Lengthening Move
1847 defm VMOVLs : N2VLInt_QHS<0,1,0b1010,0,0,1, "vmovl.s", int_arm_neon_vmovls>;
1848 defm VMOVLu : N2VLInt_QHS<1,1,0b1010,0,0,1, "vmovl.u", int_arm_neon_vmovlu>;
1850 // Vector Conversions.
1852 // VCVT : Vector Convert Between Floating-Point and Integers
1853 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
1854 v2i32, v2f32, fp_to_sint>;
1855 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
1856 v2i32, v2f32, fp_to_uint>;
1857 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
1858 v2f32, v2i32, sint_to_fp>;
1859 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
1860 v2f32, v2i32, uint_to_fp>;
1862 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
1863 v4i32, v4f32, fp_to_sint>;
1864 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
1865 v4i32, v4f32, fp_to_uint>;
1866 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
1867 v4f32, v4i32, sint_to_fp>;
1868 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
1869 v4f32, v4i32, uint_to_fp>;
1871 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
1872 // Note: Some of the opcode bits in the following VCVT instructions need to
1873 // be encoded based on the immed values.
1874 def VCVTf2xsd : N2VCvtD<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
1875 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
1876 def VCVTf2xud : N2VCvtD<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
1877 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
1878 def VCVTxs2fd : N2VCvtD<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
1879 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
1880 def VCVTxu2fd : N2VCvtD<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
1881 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
1883 def VCVTf2xsq : N2VCvtQ<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
1884 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
1885 def VCVTf2xuq : N2VCvtQ<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
1886 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
1887 def VCVTxs2fq : N2VCvtQ<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
1888 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
1889 def VCVTxu2fq : N2VCvtQ<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
1890 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
1894 // VREV64 : Vector Reverse elements within 64-bit doublewords
1896 class VREV64D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1897 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
1898 (ins DPR:$src), NoItinerary,
1899 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1900 [(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>;
1901 class VREV64Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1902 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
1903 (ins QPR:$src), NoItinerary,
1904 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1905 [(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>;
1907 def VREV64d8 : VREV64D<0b00, "vrev64.8", v8i8>;
1908 def VREV64d16 : VREV64D<0b01, "vrev64.16", v4i16>;
1909 def VREV64d32 : VREV64D<0b10, "vrev64.32", v2i32>;
1910 def VREV64df : VREV64D<0b10, "vrev64.32", v2f32>;
1912 def VREV64q8 : VREV64Q<0b00, "vrev64.8", v16i8>;
1913 def VREV64q16 : VREV64Q<0b01, "vrev64.16", v8i16>;
1914 def VREV64q32 : VREV64Q<0b10, "vrev64.32", v4i32>;
1915 def VREV64qf : VREV64Q<0b10, "vrev64.32", v4f32>;
1917 // VREV32 : Vector Reverse elements within 32-bit words
1919 class VREV32D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1920 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
1921 (ins DPR:$src), NoItinerary,
1922 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1923 [(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>;
1924 class VREV32Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1925 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
1926 (ins QPR:$src), NoItinerary,
1927 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1928 [(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>;
1930 def VREV32d8 : VREV32D<0b00, "vrev32.8", v8i8>;
1931 def VREV32d16 : VREV32D<0b01, "vrev32.16", v4i16>;
1933 def VREV32q8 : VREV32Q<0b00, "vrev32.8", v16i8>;
1934 def VREV32q16 : VREV32Q<0b01, "vrev32.16", v8i16>;
1936 // VREV16 : Vector Reverse elements within 16-bit halfwords
1938 class VREV16D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1939 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
1940 (ins DPR:$src), NoItinerary,
1941 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1942 [(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>;
1943 class VREV16Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1944 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
1945 (ins QPR:$src), NoItinerary,
1946 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1947 [(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>;
1949 def VREV16d8 : VREV16D<0b00, "vrev16.8", v8i8>;
1950 def VREV16q8 : VREV16Q<0b00, "vrev16.8", v16i8>;
1952 // Other Vector Shuffles.
1954 // VEXT : Vector Extract
1956 class VEXTd<string OpcodeStr, ValueType Ty>
1957 : N3V<0,1,0b11,0b0000,0,0, (outs DPR:$dst),
1958 (ins DPR:$lhs, DPR:$rhs, i32imm:$index), NoItinerary,
1959 !strconcat(OpcodeStr, "\t$dst, $lhs, $rhs, $index"), "",
1960 [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
1961 (Ty DPR:$rhs), imm:$index)))]>;
1963 class VEXTq<string OpcodeStr, ValueType Ty>
1964 : N3V<0,1,0b11,0b0000,1,0, (outs QPR:$dst),
1965 (ins QPR:$lhs, QPR:$rhs, i32imm:$index), NoItinerary,
1966 !strconcat(OpcodeStr, "\t$dst, $lhs, $rhs, $index"), "",
1967 [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
1968 (Ty QPR:$rhs), imm:$index)))]>;
1970 def VEXTd8 : VEXTd<"vext.8", v8i8>;
1971 def VEXTd16 : VEXTd<"vext.16", v4i16>;
1972 def VEXTd32 : VEXTd<"vext.32", v2i32>;
1973 def VEXTdf : VEXTd<"vext.32", v2f32>;
1975 def VEXTq8 : VEXTq<"vext.8", v16i8>;
1976 def VEXTq16 : VEXTq<"vext.16", v8i16>;
1977 def VEXTq32 : VEXTq<"vext.32", v4i32>;
1978 def VEXTqf : VEXTq<"vext.32", v4f32>;
1980 // VTRN : Vector Transpose
1982 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn.8">;
1983 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn.16">;
1984 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn.32">;
1986 def VTRNq8 : N2VQShuffle<0b00, 0b00001, "vtrn.8">;
1987 def VTRNq16 : N2VQShuffle<0b01, 0b00001, "vtrn.16">;
1988 def VTRNq32 : N2VQShuffle<0b10, 0b00001, "vtrn.32">;
1990 // VUZP : Vector Unzip (Deinterleave)
1992 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp.8">;
1993 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp.16">;
1994 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp.32">;
1996 def VUZPq8 : N2VQShuffle<0b00, 0b00010, "vuzp.8">;
1997 def VUZPq16 : N2VQShuffle<0b01, 0b00010, "vuzp.16">;
1998 def VUZPq32 : N2VQShuffle<0b10, 0b00010, "vuzp.32">;
2000 // VZIP : Vector Zip (Interleave)
2002 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip.8">;
2003 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip.16">;
2004 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip.32">;
2006 def VZIPq8 : N2VQShuffle<0b00, 0b00011, "vzip.8">;
2007 def VZIPq16 : N2VQShuffle<0b01, 0b00011, "vzip.16">;
2008 def VZIPq32 : N2VQShuffle<0b10, 0b00011, "vzip.32">;
2010 // Vector Table Lookup and Table Extension.
2012 // VTBL : Vector Table Lookup
2014 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$dst),
2015 (ins DPR:$tbl1, DPR:$src), NoItinerary,
2016 "vtbl.8\t$dst, \\{$tbl1\\}, $src", "",
2017 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>;
2019 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst),
2020 (ins DPR:$tbl1, DPR:$tbl2, DPR:$src), NoItinerary,
2021 "vtbl.8\t$dst, \\{$tbl1,$tbl2\\}, $src", "",
2022 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl2
2023 DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
2025 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst),
2026 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), NoItinerary,
2027 "vtbl.8\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "",
2028 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl3
2029 DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
2031 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst),
2032 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), NoItinerary,
2033 "vtbl.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "",
2034 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl4 DPR:$tbl1, DPR:$tbl2,
2035 DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
2037 // VTBX : Vector Table Extension
2039 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst),
2040 (ins DPR:$orig, DPR:$tbl1, DPR:$src), NoItinerary,
2041 "vtbx.8\t$dst, \\{$tbl1\\}, $src", "$orig = $dst",
2042 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1
2043 DPR:$orig, DPR:$tbl1, DPR:$src)))]>;
2045 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst),
2046 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), NoItinerary,
2047 "vtbx.8\t$dst, \\{$tbl1,$tbl2\\}, $src", "$orig = $dst",
2048 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx2
2049 DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
2051 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst),
2052 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), NoItinerary,
2053 "vtbx.8\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "$orig = $dst",
2054 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx3 DPR:$orig, DPR:$tbl1,
2055 DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
2057 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1,
2058 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), NoItinerary,
2059 "vtbx.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "$orig = $dst",
2060 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx4 DPR:$orig, DPR:$tbl1,
2061 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
2063 //===----------------------------------------------------------------------===//
2064 // NEON instructions for single-precision FP math
2065 //===----------------------------------------------------------------------===//
2067 // These need separate instructions because they must use DPR_VFP2 register
2068 // class which have SPR sub-registers.
2070 // Vector Add Operations used for single-precision FP
2071 let neverHasSideEffects = 1 in
2072 def VADDfd_sfp : N3VDs<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd,1>;
2073 def : N3VDsPat<fadd, VADDfd_sfp>;
2075 // Vector Sub Operations used for single-precision FP
2076 let neverHasSideEffects = 1 in
2077 def VSUBfd_sfp : N3VDs<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub,0>;
2078 def : N3VDsPat<fsub, VSUBfd_sfp>;
2080 // Vector Multiply Operations used for single-precision FP
2081 let neverHasSideEffects = 1 in
2082 def VMULfd_sfp : N3VDs<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul,1>;
2083 def : N3VDsPat<fmul, VMULfd_sfp>;
2085 // Vector Multiply-Accumulate/Subtract used for single-precision FP
2086 let neverHasSideEffects = 1 in
2087 def VMLAfd_sfp : N3VDMulOps<0, 0, 0b00, 0b1101, 1, "vmla.f32", v2f32,fmul,fadd>;
2088 def : N3VDMulOpsPat<fmul, fadd, VMLAfd_sfp>;
2090 let neverHasSideEffects = 1 in
2091 def VMLSfd_sfp : N3VDMulOps<0, 0, 0b10, 0b1101, 1, "vmls.f32", v2f32,fmul,fsub>;
2092 def : N3VDMulOpsPat<fmul, fsub, VMLSfd_sfp>;
2094 // Vector Absolute used for single-precision FP
2095 let neverHasSideEffects = 1 in
2096 def VABSfd_sfp : N2VDInts<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
2097 v2f32, v2f32, int_arm_neon_vabs>;
2098 def : N2VDIntsPat<fabs, VABSfd_sfp>;
2100 // Vector Negate used for single-precision FP
2101 let neverHasSideEffects = 1 in
2102 def VNEGf32d_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
2103 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NoItinerary,
2104 "vneg.f32\t$dst, $src", "", []>;
2105 def : N2VDIntsPat<fneg, VNEGf32d_sfp>;
2107 // Vector Convert between single-precision FP and integer
2108 let neverHasSideEffects = 1 in
2109 def VCVTf2sd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
2110 v2i32, v2f32, fp_to_sint>;
2111 def : N2VDsPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
2113 let neverHasSideEffects = 1 in
2114 def VCVTf2ud_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
2115 v2i32, v2f32, fp_to_uint>;
2116 def : N2VDsPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
2118 let neverHasSideEffects = 1 in
2119 def VCVTs2fd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
2120 v2f32, v2i32, sint_to_fp>;
2121 def : N2VDsPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
2123 let neverHasSideEffects = 1 in
2124 def VCVTu2fd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
2125 v2f32, v2i32, uint_to_fp>;
2126 def : N2VDsPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
2128 //===----------------------------------------------------------------------===//
2129 // Non-Instruction Patterns
2130 //===----------------------------------------------------------------------===//
2133 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
2134 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
2135 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
2136 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
2137 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
2138 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
2139 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
2140 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
2141 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
2142 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
2143 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
2144 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
2145 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
2146 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
2147 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
2148 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
2149 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
2150 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
2151 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
2152 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
2153 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
2154 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
2155 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
2156 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
2157 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
2158 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
2159 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
2160 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
2161 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
2162 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
2164 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
2165 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
2166 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
2167 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
2168 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
2169 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
2170 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
2171 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
2172 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
2173 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
2174 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
2175 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
2176 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
2177 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
2178 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
2179 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
2180 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
2181 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
2182 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
2183 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
2184 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
2185 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
2186 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
2187 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
2188 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
2189 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
2190 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
2191 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
2192 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
2193 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;
projects / oota-llvm.git / blob