1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
20 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
27 // Types for vector shift by immediates. The "SHX" version is for long and
28 // narrow operations where the source and destination vectors have different
29 // types. The "SHINS" version is for shift and insert operations.
30 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
32 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
34 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
37 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
45 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
49 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
56 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
60 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
63 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
65 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
68 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
70 // VDUPLANE can produce a quad-register result from a double-register source,
71 // so the result is not constrained to match the source.
72 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
73 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
76 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
77 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
78 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
80 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
81 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
82 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
83 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
85 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
88 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
89 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
90 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
92 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
94 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
95 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
97 //===----------------------------------------------------------------------===//
98 // NEON operand definitions
99 //===----------------------------------------------------------------------===//
101 def h8imm : Operand<i8> {
102 let PrintMethod = "printHex8ImmOperand";
104 def h16imm : Operand<i16> {
105 let PrintMethod = "printHex16ImmOperand";
107 def h32imm : Operand<i32> {
108 let PrintMethod = "printHex32ImmOperand";
110 def h64imm : Operand<i64> {
111 let PrintMethod = "printHex64ImmOperand";
114 //===----------------------------------------------------------------------===//
115 // NEON load / store instructions
116 //===----------------------------------------------------------------------===//
118 // Use vldmia to load a Q register as a D register pair.
119 def VLDRQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr), IIC_fpLoadm,
120 "vldmia", "$addr, ${dst:dregpair}",
121 [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]> {
122 let Inst{27-25} = 0b110;
123 let Inst{24} = 0; // P bit
124 let Inst{23} = 1; // U bit
126 let Inst{11-8} = 0b1011;
129 // Use vstmia to store a Q register as a D register pair.
130 def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr), IIC_fpStorem,
131 "vstmia", "$addr, ${src:dregpair}",
132 [(store (v2f64 QPR:$src), addrmode4:$addr)]> {
133 let Inst{27-25} = 0b110;
134 let Inst{24} = 0; // P bit
135 let Inst{23} = 1; // U bit
137 let Inst{11-8} = 0b1011;
140 // VLD1 : Vector Load (multiple single elements)
141 class VLD1D<bits<4> op7_4, string Dt, ValueType Ty>
142 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst), (ins addrmode6:$addr), IIC_VLD1,
143 "vld1", Dt, "\\{$dst\\}, $addr", "",
144 [(set DPR:$dst, (Ty (int_arm_neon_vld1 addrmode6:$addr)))]>;
145 class VLD1Q<bits<4> op7_4, string Dt, ValueType Ty>
146 : NLdSt<0,0b10,0b1010,op7_4, (outs QPR:$dst), (ins addrmode6:$addr), IIC_VLD1,
147 "vld1", Dt, "${dst:dregpair}, $addr", "",
148 [(set QPR:$dst, (Ty (int_arm_neon_vld1 addrmode6:$addr)))]>;
150 def VLD1d8 : VLD1D<0b0000, "8", v8i8>;
151 def VLD1d16 : VLD1D<0b0100, "16", v4i16>;
152 def VLD1d32 : VLD1D<0b1000, "32", v2i32>;
153 def VLD1df : VLD1D<0b1000, "32", v2f32>;
154 def VLD1d64 : VLD1D<0b1100, "64", v1i64>;
156 def VLD1q8 : VLD1Q<0b0000, "8", v16i8>;
157 def VLD1q16 : VLD1Q<0b0100, "16", v8i16>;
158 def VLD1q32 : VLD1Q<0b1000, "32", v4i32>;
159 def VLD1qf : VLD1Q<0b1000, "32", v4f32>;
160 def VLD1q64 : VLD1Q<0b1100, "64", v2i64>;
164 // ...with address register writeback:
165 class VLD1DWB<bits<4> op7_4, string Dt>
166 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst, GPR:$wb),
167 (ins addrmode6:$addr), IIC_VLD1,
168 "vld1", Dt, "\\{$dst\\}, $addr",
169 "$addr.addr = $wb", []>;
170 class VLD1QWB<bits<4> op7_4, string Dt>
171 : NLdSt<0,0b10,0b1010,op7_4, (outs QPR:$dst, GPR:$wb),
172 (ins addrmode6:$addr), IIC_VLD1,
173 "vld1", Dt, "${dst:dregpair}, $addr",
174 "$addr.addr = $wb", []>;
176 def VLD1d8_UPD : VLD1DWB<0b0000, "8">;
177 def VLD1d16_UPD : VLD1DWB<0b0100, "16">;
178 def VLD1d32_UPD : VLD1DWB<0b1000, "32">;
179 def VLD1d64_UPD : VLD1DWB<0b1100, "64">;
181 def VLD1q8_UPD : VLD1QWB<0b0000, "8">;
182 def VLD1q16_UPD : VLD1QWB<0b0100, "16">;
183 def VLD1q32_UPD : VLD1QWB<0b1000, "32">;
184 def VLD1q64_UPD : VLD1QWB<0b1100, "64">;
187 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
189 // These (dreg triple/quadruple) are for disassembly only.
190 class VLD1D3<bits<4> op7_4, string Dt>
191 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
192 (ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
193 "\\{$dst1, $dst2, $dst3\\}, $addr", "",
194 [/* For disassembly only; pattern left blank */]>;
195 class VLD1D4<bits<4> op7_4, string Dt>
196 : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
197 (ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
198 "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "",
199 [/* For disassembly only; pattern left blank */]>;
201 def VLD1d8T : VLD1D3<0b0000, "8">;
202 def VLD1d16T : VLD1D3<0b0100, "16">;
203 def VLD1d32T : VLD1D3<0b1000, "32">;
204 // VLD1d64T : implemented as VLD3d64
206 def VLD1d8Q : VLD1D4<0b0000, "8">;
207 def VLD1d16Q : VLD1D4<0b0100, "16">;
208 def VLD1d32Q : VLD1D4<0b1000, "32">;
209 // VLD1d64Q : implemented as VLD4d64
211 // ...with address register writeback:
212 class VLD1D3WB<bits<4> op7_4, string Dt>
213 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
214 (ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
215 "\\{$dst1, $dst2, $dst3\\}, $addr", "$addr.addr = $wb",
216 [/* For disassembly only; pattern left blank */]>;
217 class VLD1D4WB<bits<4> op7_4, string Dt>
218 : NLdSt<0,0b10,0b0010,op7_4,
219 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
220 (ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
221 "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "$addr.addr = $wb",
222 [/* For disassembly only; pattern left blank */]>;
224 def VLD1d8T_UPD : VLD1D3WB<0b0000, "8">;
225 def VLD1d16T_UPD : VLD1D3WB<0b0100, "16">;
226 def VLD1d32T_UPD : VLD1D3WB<0b1000, "32">;
227 // VLD1d64T_UPD : implemented as VLD3d64_UPD
229 def VLD1d8Q_UPD : VLD1D4WB<0b0000, "8">;
230 def VLD1d16Q_UPD : VLD1D4WB<0b0100, "16">;
231 def VLD1d32Q_UPD : VLD1D4WB<0b1000, "32">;
232 // VLD1d64Q_UPD : implemented as VLD4d64_UPD
234 // VLD2 : Vector Load (multiple 2-element structures)
235 class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
236 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2),
237 (ins addrmode6:$addr), IIC_VLD2,
238 "vld2", Dt, "\\{$dst1, $dst2\\}, $addr", "", []>;
239 class VLD2Q<bits<4> op7_4, string Dt>
240 : NLdSt<0, 0b10, 0b0011, op7_4,
241 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
242 (ins addrmode6:$addr), IIC_VLD2,
243 "vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
245 def VLD2d8 : VLD2D<0b1000, 0b0000, "8">;
246 def VLD2d16 : VLD2D<0b1000, 0b0100, "16">;
247 def VLD2d32 : VLD2D<0b1000, 0b1000, "32">;
248 def VLD2d64 : NLdSt<0,0b10,0b1010,0b1100, (outs DPR:$dst1, DPR:$dst2),
249 (ins addrmode6:$addr), IIC_VLD1,
250 "vld1", "64", "\\{$dst1, $dst2\\}, $addr", "", []>;
252 def VLD2q8 : VLD2Q<0b0000, "8">;
253 def VLD2q16 : VLD2Q<0b0100, "16">;
254 def VLD2q32 : VLD2Q<0b1000, "32">;
256 // ...with address register writeback:
257 class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
258 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb),
259 (ins addrmode6:$addr), IIC_VLD2,
260 "vld2", Dt, "\\{$dst1, $dst2\\}, $addr",
261 "$addr.addr = $wb", []>;
262 class VLD2QWB<bits<4> op7_4, string Dt>
263 : NLdSt<0, 0b10, 0b0011, op7_4,
264 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
265 (ins addrmode6:$addr), IIC_VLD2,
266 "vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr",
267 "$addr.addr = $wb", []>;
269 def VLD2d8_UPD : VLD2DWB<0b1000, 0b0000, "8">;
270 def VLD2d16_UPD : VLD2DWB<0b1000, 0b0100, "16">;
271 def VLD2d32_UPD : VLD2DWB<0b1000, 0b1000, "32">;
272 def VLD2d64_UPD : NLdSt<0,0b10,0b1010,0b1100,
273 (outs DPR:$dst1, DPR:$dst2, GPR:$wb),
274 (ins addrmode6:$addr), IIC_VLD1,
275 "vld1", "64", "\\{$dst1, $dst2\\}, $addr",
276 "$addr.addr = $wb", []>;
278 def VLD2q8_UPD : VLD2QWB<0b0000, "8">;
279 def VLD2q16_UPD : VLD2QWB<0b0100, "16">;
280 def VLD2q32_UPD : VLD2QWB<0b1000, "32">;
282 // ...with double-spaced registers (for disassembly only):
283 def VLD2b8 : VLD2D<0b1001, 0b0000, "8">;
284 def VLD2b16 : VLD2D<0b1001, 0b0100, "16">;
285 def VLD2b32 : VLD2D<0b1001, 0b1000, "32">;
286 def VLD2b8_UPD : VLD2DWB<0b1001, 0b0000, "8">;
287 def VLD2b16_UPD : VLD2DWB<0b1001, 0b0100, "16">;
288 def VLD2b32_UPD : VLD2DWB<0b1001, 0b1000, "32">;
290 // VLD3 : Vector Load (multiple 3-element structures)
291 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
292 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
293 (ins addrmode6:$addr), IIC_VLD3,
294 "vld3", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
296 def VLD3d8 : VLD3D<0b0100, 0b0000, "8">;
297 def VLD3d16 : VLD3D<0b0100, 0b0100, "16">;
298 def VLD3d32 : VLD3D<0b0100, 0b1000, "32">;
299 def VLD3d64 : NLdSt<0,0b10,0b0110,0b1100,
300 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
301 (ins addrmode6:$addr), IIC_VLD1,
302 "vld1", "64", "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
304 // ...with address register writeback:
305 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
306 : NLdSt<0, 0b10, op11_8, op7_4,
307 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
308 (ins addrmode6:$addr), IIC_VLD3,
309 "vld3", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr",
310 "$addr.addr = $wb", []>;
312 def VLD3d8_UPD : VLD3DWB<0b0100, 0b0000, "8">;
313 def VLD3d16_UPD : VLD3DWB<0b0100, 0b0100, "16">;
314 def VLD3d32_UPD : VLD3DWB<0b0100, 0b1000, "32">;
315 def VLD3d64_UPD : NLdSt<0,0b10,0b0110,0b1100,
316 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
317 (ins addrmode6:$addr), IIC_VLD1,
318 "vld1", "64", "\\{$dst1, $dst2, $dst3\\}, $addr",
319 "$addr.addr = $wb", []>;
321 // ...with double-spaced registers (non-updating versions for disassembly only):
322 def VLD3q8 : VLD3D<0b0101, 0b0000, "8">;
323 def VLD3q16 : VLD3D<0b0101, 0b0100, "16">;
324 def VLD3q32 : VLD3D<0b0101, 0b1000, "32">;
325 def VLD3q8_UPD : VLD3DWB<0b0101, 0b0000, "8">;
326 def VLD3q16_UPD : VLD3DWB<0b0101, 0b0100, "16">;
327 def VLD3q32_UPD : VLD3DWB<0b0101, 0b1000, "32">;
329 // ...alternate versions to be allocated odd register numbers:
330 def VLD3q8odd_UPD : VLD3DWB<0b0101, 0b0000, "8">;
331 def VLD3q16odd_UPD : VLD3DWB<0b0101, 0b0100, "16">;
332 def VLD3q32odd_UPD : VLD3DWB<0b0101, 0b1000, "32">;
334 // VLD4 : Vector Load (multiple 4-element structures)
335 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
336 : NLdSt<0, 0b10, op11_8, op7_4,
337 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
338 (ins addrmode6:$addr), IIC_VLD4,
339 "vld4", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
341 def VLD4d8 : VLD4D<0b0000, 0b0000, "8">;
342 def VLD4d16 : VLD4D<0b0000, 0b0100, "16">;
343 def VLD4d32 : VLD4D<0b0000, 0b1000, "32">;
344 def VLD4d64 : NLdSt<0,0b10,0b0010,0b1100,
345 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
346 (ins addrmode6:$addr), IIC_VLD1,
347 "vld1", "64", "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr",
350 // ...with address register writeback:
351 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
352 : NLdSt<0, 0b10, op11_8, op7_4,
353 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
354 (ins addrmode6:$addr), IIC_VLD4,
355 "vld4", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr",
356 "$addr.addr = $wb", []>;
358 def VLD4d8_UPD : VLD4DWB<0b0000, 0b0000, "8">;
359 def VLD4d16_UPD : VLD4DWB<0b0000, 0b0100, "16">;
360 def VLD4d32_UPD : VLD4DWB<0b0000, 0b1000, "32">;
361 def VLD4d64_UPD : NLdSt<0,0b10,0b0010,0b1100,
362 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4,
364 (ins addrmode6:$addr), IIC_VLD1,
366 "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr",
367 "$addr.addr = $wb", []>;
369 // ...with double-spaced registers (non-updating versions for disassembly only):
370 def VLD4q8 : VLD4D<0b0001, 0b0000, "8">;
371 def VLD4q16 : VLD4D<0b0001, 0b0100, "16">;
372 def VLD4q32 : VLD4D<0b0001, 0b1000, "32">;
373 def VLD4q8_UPD : VLD4DWB<0b0001, 0b0000, "8">;
374 def VLD4q16_UPD : VLD4DWB<0b0001, 0b0100, "16">;
375 def VLD4q32_UPD : VLD4DWB<0b0001, 0b1000, "32">;
377 // ...alternate versions to be allocated odd register numbers:
378 def VLD4q8odd_UPD : VLD4DWB<0b0001, 0b0000, "8">;
379 def VLD4q16odd_UPD : VLD4DWB<0b0001, 0b0100, "16">;
380 def VLD4q32odd_UPD : VLD4DWB<0b0001, 0b1000, "32">;
382 // VLD1LN : Vector Load (single element to one lane)
383 // FIXME: Not yet implemented.
385 // VLD2LN : Vector Load (single 2-element structure to one lane)
386 class VLD2LN<bits<4> op11_8, string Dt>
387 : NLdSt<1,0b10,op11_8,{?,?,?,?}, (outs DPR:$dst1, DPR:$dst2),
388 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
389 IIC_VLD2, "vld2", Dt, "\\{$dst1[$lane], $dst2[$lane]\\}, $addr",
390 "$src1 = $dst1, $src2 = $dst2", []>;
392 // vld2 to single-spaced registers.
393 def VLD2LNd8 : VLD2LN<0b0001, "8">;
394 def VLD2LNd16 : VLD2LN<0b0101, "16"> { let Inst{5} = 0; }
395 def VLD2LNd32 : VLD2LN<0b1001, "32"> { let Inst{6} = 0; }
397 // vld2 to double-spaced even registers.
398 def VLD2LNq16 : VLD2LN<0b0101, "16"> { let Inst{5} = 1; }
399 def VLD2LNq32 : VLD2LN<0b1001, "32"> { let Inst{6} = 1; }
401 // vld2 to double-spaced odd registers.
402 def VLD2LNq16odd : VLD2LN<0b0101, "16"> { let Inst{5} = 1; }
403 def VLD2LNq32odd : VLD2LN<0b1001, "32"> { let Inst{6} = 1; }
405 // VLD3LN : Vector Load (single 3-element structure to one lane)
406 class VLD3LN<bits<4> op11_8, string Dt>
407 : NLdSt<1,0b10,op11_8,{?,?,?,?}, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
408 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
409 nohash_imm:$lane), IIC_VLD3, "vld3", Dt,
410 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr",
411 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
413 // vld3 to single-spaced registers.
414 def VLD3LNd8 : VLD3LN<0b0010, "8"> { let Inst{4} = 0; }
415 def VLD3LNd16 : VLD3LN<0b0110, "16"> { let Inst{5-4} = 0b00; }
416 def VLD3LNd32 : VLD3LN<0b1010, "32"> { let Inst{6-4} = 0b000; }
418 // vld3 to double-spaced even registers.
419 def VLD3LNq16 : VLD3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
420 def VLD3LNq32 : VLD3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
422 // vld3 to double-spaced odd registers.
423 def VLD3LNq16odd : VLD3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
424 def VLD3LNq32odd : VLD3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
426 // VLD4LN : Vector Load (single 4-element structure to one lane)
427 class VLD4LN<bits<4> op11_8, string Dt>
428 : NLdSt<1,0b10,op11_8,{?,?,?,?},
429 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
430 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
431 nohash_imm:$lane), IIC_VLD4, "vld4", Dt,
432 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $addr",
433 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>;
435 // vld4 to single-spaced registers.
436 def VLD4LNd8 : VLD4LN<0b0011, "8">;
437 def VLD4LNd16 : VLD4LN<0b0111, "16"> { let Inst{5} = 0; }
438 def VLD4LNd32 : VLD4LN<0b1011, "32"> { let Inst{6} = 0; }
440 // vld4 to double-spaced even registers.
441 def VLD4LNq16 : VLD4LN<0b0111, "16"> { let Inst{5} = 1; }
442 def VLD4LNq32 : VLD4LN<0b1011, "32"> { let Inst{6} = 1; }
444 // vld4 to double-spaced odd registers.
445 def VLD4LNq16odd : VLD4LN<0b0111, "16"> { let Inst{5} = 1; }
446 def VLD4LNq32odd : VLD4LN<0b1011, "32"> { let Inst{6} = 1; }
448 // VLD1DUP : Vector Load (single element to all lanes)
449 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
450 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
451 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
452 // FIXME: Not yet implemented.
453 } // mayLoad = 1, hasExtraDefRegAllocReq = 1
455 // VST1 : Vector Store (multiple single elements)
456 class VST1D<bits<4> op7_4, string Dt, ValueType Ty>
457 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$src), IIC_VST,
458 "vst1", Dt, "\\{$src\\}, $addr", "",
459 [(int_arm_neon_vst1 addrmode6:$addr, (Ty DPR:$src))]>;
460 class VST1Q<bits<4> op7_4, string Dt, ValueType Ty>
461 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$addr, QPR:$src), IIC_VST,
462 "vst1", Dt, "${src:dregpair}, $addr", "",
463 [(int_arm_neon_vst1 addrmode6:$addr, (Ty QPR:$src))]>;
465 let hasExtraSrcRegAllocReq = 1 in {
466 def VST1d8 : VST1D<0b0000, "8", v8i8>;
467 def VST1d16 : VST1D<0b0100, "16", v4i16>;
468 def VST1d32 : VST1D<0b1000, "32", v2i32>;
469 def VST1df : VST1D<0b1000, "32", v2f32>;
470 def VST1d64 : VST1D<0b1100, "64", v1i64>;
472 def VST1q8 : VST1Q<0b0000, "8", v16i8>;
473 def VST1q16 : VST1Q<0b0100, "16", v8i16>;
474 def VST1q32 : VST1Q<0b1000, "32", v4i32>;
475 def VST1qf : VST1Q<0b1000, "32", v4f32>;
476 def VST1q64 : VST1Q<0b1100, "64", v2i64>;
477 } // hasExtraSrcRegAllocReq
479 // These (dreg triple/quadruple) are for disassembly only.
480 class VST1D3<bits<4> op7_4, string Dt>
481 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
482 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
483 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr", "",
484 [/* For disassembly only; pattern left blank */]>;
485 class VST1D4<bits<4> op7_4, string Dt>
486 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
487 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
488 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr", "",
489 [/* For disassembly only; pattern left blank */]>;
491 def VST1d8T : VST1D3<0b0000, "8">;
492 def VST1d16T : VST1D3<0b0100, "16">;
493 def VST1d32T : VST1D3<0b1000, "32">;
494 // VST1d64T : implemented as VST3d64
496 def VST1d8Q : VST1D4<0b0000, "8">;
497 def VST1d16Q : VST1D4<0b0100, "16">;
498 def VST1d32Q : VST1D4<0b1000, "32">;
499 // VST1d64Q : implemented as VST4d64
501 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
503 // VST2 : Vector Store (multiple 2-element structures)
504 class VST2D<bits<4> op7_4, string Dt>
505 : NLdSt<0,0b00,0b1000,op7_4, (outs),
506 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
507 "vst2", Dt, "\\{$src1, $src2\\}, $addr", "", []>;
508 class VST2Q<bits<4> op7_4, string Dt>
509 : NLdSt<0,0b00,0b0011,op7_4, (outs),
510 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
511 IIC_VST, "vst2", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
514 def VST2d8 : VST2D<0b0000, "8">;
515 def VST2d16 : VST2D<0b0100, "16">;
516 def VST2d32 : VST2D<0b1000, "32">;
517 def VST2d64 : NLdSt<0,0b00,0b1010,0b1100, (outs),
518 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
519 "vst1", "64", "\\{$src1, $src2\\}, $addr", "", []>;
521 def VST2q8 : VST2Q<0b0000, "8">;
522 def VST2q16 : VST2Q<0b0100, "16">;
523 def VST2q32 : VST2Q<0b1000, "32">;
525 // These (double-spaced dreg pair) are for disassembly only.
526 class VST2Ddbl<bits<4> op7_4, string Dt>
527 : NLdSt<0, 0b00, 0b1001, op7_4, (outs),
528 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
529 "vst2", Dt, "\\{$src1, $src2\\}, $addr", "", []>;
531 def VST2d8D : VST2Ddbl<0b0000, "8">;
532 def VST2d16D : VST2Ddbl<0b0100, "16">;
533 def VST2d32D : VST2Ddbl<0b1000, "32">;
535 // VST3 : Vector Store (multiple 3-element structures)
536 class VST3D<bits<4> op7_4, string Dt>
537 : NLdSt<0,0b00,0b0100,op7_4, (outs),
538 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
539 "vst3", Dt, "\\{$src1, $src2, $src3\\}, $addr", "", []>;
540 class VST3WB<bits<4> op7_4, string Dt>
541 : NLdSt<0,0b00,0b0101,op7_4, (outs GPR:$wb),
542 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
543 "vst3", Dt, "\\{$src1, $src2, $src3\\}, $addr",
544 "$addr.addr = $wb", []>;
546 def VST3d8 : VST3D<0b0000, "8">;
547 def VST3d16 : VST3D<0b0100, "16">;
548 def VST3d32 : VST3D<0b1000, "32">;
549 def VST3d64 : NLdSt<0,0b00,0b0110,0b1100, (outs),
550 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
552 "vst1", "64", "\\{$src1, $src2, $src3\\}, $addr", "", []>;
554 // vst3 to double-spaced even registers.
555 def VST3q8_UPD : VST3WB<0b0000, "8">;
556 def VST3q16_UPD : VST3WB<0b0100, "16">;
557 def VST3q32_UPD : VST3WB<0b1000, "32">;
559 // vst3 to double-spaced odd registers.
560 def VST3q8odd_UPD : VST3WB<0b0000, "8">;
561 def VST3q16odd_UPD : VST3WB<0b0100, "16">;
562 def VST3q32odd_UPD : VST3WB<0b1000, "32">;
564 // VST4 : Vector Store (multiple 4-element structures)
565 class VST4D<bits<4> op7_4, string Dt>
566 : NLdSt<0,0b00,0b0000,op7_4, (outs),
567 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
568 IIC_VST, "vst4", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
570 class VST4WB<bits<4> op7_4, string Dt>
571 : NLdSt<0,0b00,0b0001,op7_4, (outs GPR:$wb),
572 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
573 IIC_VST, "vst4", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
574 "$addr.addr = $wb", []>;
576 def VST4d8 : VST4D<0b0000, "8">;
577 def VST4d16 : VST4D<0b0100, "16">;
578 def VST4d32 : VST4D<0b1000, "32">;
579 def VST4d64 : NLdSt<0,0b00,0b0010,0b1100, (outs),
580 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
582 "vst1", "64", "\\{$src1, $src2, $src3, $src4\\}, $addr",
585 // vst4 to double-spaced even registers.
586 def VST4q8_UPD : VST4WB<0b0000, "8">;
587 def VST4q16_UPD : VST4WB<0b0100, "16">;
588 def VST4q32_UPD : VST4WB<0b1000, "32">;
590 // vst4 to double-spaced odd registers.
591 def VST4q8odd_UPD : VST4WB<0b0000, "8">;
592 def VST4q16odd_UPD : VST4WB<0b0100, "16">;
593 def VST4q32odd_UPD : VST4WB<0b1000, "32">;
595 // VST1LN : Vector Store (single element from one lane)
596 // FIXME: Not yet implemented.
598 // VST2LN : Vector Store (single 2-element structure from one lane)
599 class VST2LN<bits<4> op11_8, string Dt>
600 : NLdSt<1,0b00,op11_8,{?,?,?,?}, (outs),
601 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
602 IIC_VST, "vst2", Dt, "\\{$src1[$lane], $src2[$lane]\\}, $addr",
605 // vst2 to single-spaced registers.
606 def VST2LNd8 : VST2LN<0b0001, "8">;
607 def VST2LNd16 : VST2LN<0b0101, "16"> { let Inst{5} = 0; }
608 def VST2LNd32 : VST2LN<0b1001, "32"> { let Inst{6} = 0; }
610 // vst2 to double-spaced even registers.
611 def VST2LNq16 : VST2LN<0b0101, "16"> { let Inst{5} = 1; }
612 def VST2LNq32 : VST2LN<0b1001, "32"> { let Inst{6} = 1; }
614 // vst2 to double-spaced odd registers.
615 def VST2LNq16odd : VST2LN<0b0101, "16"> { let Inst{5} = 1; }
616 def VST2LNq32odd : VST2LN<0b1001, "32"> { let Inst{6} = 1; }
618 // VST3LN : Vector Store (single 3-element structure from one lane)
619 class VST3LN<bits<4> op11_8, string Dt>
620 : NLdSt<1,0b00,op11_8,{?,?,?,?}, (outs),
621 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
622 nohash_imm:$lane), IIC_VST, "vst3", Dt,
623 "\\{$src1[$lane], $src2[$lane], $src3[$lane]\\}, $addr", "", []>;
625 // vst3 to single-spaced registers.
626 def VST3LNd8 : VST3LN<0b0010, "8"> { let Inst{4} = 0; }
627 def VST3LNd16 : VST3LN<0b0110, "16"> { let Inst{5-4} = 0b00; }
628 def VST3LNd32 : VST3LN<0b1010, "32"> { let Inst{6-4} = 0b000; }
630 // vst3 to double-spaced even registers.
631 def VST3LNq16 : VST3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
632 def VST3LNq32 : VST3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
634 // vst3 to double-spaced odd registers.
635 def VST3LNq16odd : VST3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
636 def VST3LNq32odd : VST3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
638 // VST4LN : Vector Store (single 4-element structure from one lane)
639 class VST4LN<bits<4> op11_8, string Dt>
640 : NLdSt<1,0b00,op11_8,{?,?,?,?}, (outs),
641 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
642 nohash_imm:$lane), IIC_VST, "vst4", Dt,
643 "\\{$src1[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr",
646 // vst4 to single-spaced registers.
647 def VST4LNd8 : VST4LN<0b0011, "8">;
648 def VST4LNd16 : VST4LN<0b0111, "16"> { let Inst{5} = 0; }
649 def VST4LNd32 : VST4LN<0b1011, "32"> { let Inst{6} = 0; }
651 // vst4 to double-spaced even registers.
652 def VST4LNq16 : VST4LN<0b0111, "16"> { let Inst{5} = 1; }
653 def VST4LNq32 : VST4LN<0b1011, "32"> { let Inst{6} = 1; }
655 // vst4 to double-spaced odd registers.
656 def VST4LNq16odd : VST4LN<0b0111, "16"> { let Inst{5} = 1; }
657 def VST4LNq32odd : VST4LN<0b1011, "32"> { let Inst{6} = 1; }
659 } // mayStore = 1, hasExtraSrcRegAllocReq = 1
662 //===----------------------------------------------------------------------===//
663 // NEON pattern fragments
664 //===----------------------------------------------------------------------===//
666 // Extract D sub-registers of Q registers.
667 // (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6)
668 def DSubReg_i8_reg : SDNodeXForm<imm, [{
669 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
671 def DSubReg_i16_reg : SDNodeXForm<imm, [{
672 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
674 def DSubReg_i32_reg : SDNodeXForm<imm, [{
675 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
677 def DSubReg_f64_reg : SDNodeXForm<imm, [{
678 return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
680 def DSubReg_f64_other_reg : SDNodeXForm<imm, [{
681 return CurDAG->getTargetConstant(5 + (1 - N->getZExtValue()), MVT::i32);
684 // Extract S sub-registers of Q/D registers.
685 // (arm_ssubreg_0 is 1; arm_ssubreg_1 is 2; etc.)
686 def SSubReg_f32_reg : SDNodeXForm<imm, [{
687 return CurDAG->getTargetConstant(1 + N->getZExtValue(), MVT::i32);
690 // Translate lane numbers from Q registers to D subregs.
691 def SubReg_i8_lane : SDNodeXForm<imm, [{
692 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
694 def SubReg_i16_lane : SDNodeXForm<imm, [{
695 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
697 def SubReg_i32_lane : SDNodeXForm<imm, [{
698 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
701 //===----------------------------------------------------------------------===//
702 // Instruction Classes
703 //===----------------------------------------------------------------------===//
705 // Basic 2-register operations: single-, double- and quad-register.
706 class N2VS<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
707 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
708 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
709 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
710 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
711 IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
712 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
713 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
714 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
715 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
716 (ins DPR:$src), IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "",
717 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
718 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
719 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
720 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
721 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
722 (ins QPR:$src), IIC_VUNAQ, OpcodeStr, Dt, "$dst, $src", "",
723 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
725 // Basic 2-register intrinsics, both double- and quad-register.
726 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
727 bits<2> op17_16, bits<5> op11_7, bit op4,
728 InstrItinClass itin, string OpcodeStr, string Dt,
729 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
730 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
731 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
732 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
733 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
734 bits<2> op17_16, bits<5> op11_7, bit op4,
735 InstrItinClass itin, string OpcodeStr, string Dt,
736 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
737 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
738 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
739 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
741 // Narrow 2-register intrinsics.
742 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
743 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
744 InstrItinClass itin, string OpcodeStr, string Dt,
745 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
746 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
747 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
748 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
750 // Long 2-register intrinsics (currently only used for VMOVL).
751 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
752 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
753 InstrItinClass itin, string OpcodeStr, string Dt,
754 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
755 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$dst),
756 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
757 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>;
759 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
760 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
761 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
762 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
763 OpcodeStr, Dt, "$dst1, $dst2",
764 "$src1 = $dst1, $src2 = $dst2", []>;
765 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
766 InstrItinClass itin, string OpcodeStr, string Dt>
767 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
768 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$dst1, $dst2",
769 "$src1 = $dst1, $src2 = $dst2", []>;
771 // Basic 3-register operations: single-, double- and quad-register.
772 class N3VS<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
773 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
774 SDNode OpNode, bit Commutable>
775 : N3V<op24, op23, op21_20, op11_8, 0, op4,
776 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), IIC_VBIND,
777 OpcodeStr, Dt, "$dst, $src1, $src2", "", []> {
778 let isCommutable = Commutable;
781 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
782 InstrItinClass itin, string OpcodeStr, string Dt,
783 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
784 : N3V<op24, op23, op21_20, op11_8, 0, op4,
785 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
786 OpcodeStr, Dt, "$dst, $src1, $src2", "",
787 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
788 let isCommutable = Commutable;
790 // Same as N3VD but no data type.
791 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
792 InstrItinClass itin, string OpcodeStr,
793 ValueType ResTy, ValueType OpTy,
794 SDNode OpNode, bit Commutable>
795 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
796 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
797 OpcodeStr, "$dst, $src1, $src2", "",
798 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]>{
799 let isCommutable = Commutable;
801 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
802 InstrItinClass itin, string OpcodeStr, string Dt,
803 ValueType Ty, SDNode ShOp>
804 : N3V<0, 1, op21_20, op11_8, 1, 0,
805 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
806 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
808 (Ty (ShOp (Ty DPR:$src1),
809 (Ty (NEONvduplane (Ty DPR_VFP2:$src2), imm:$lane)))))]>{
810 let isCommutable = 0;
812 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
813 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
814 : N3V<0, 1, op21_20, op11_8, 1, 0,
815 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
816 IIC_VMULi16D, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
818 (Ty (ShOp (Ty DPR:$src1),
819 (Ty (NEONvduplane (Ty DPR_8:$src2), imm:$lane)))))]> {
820 let isCommutable = 0;
823 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
824 InstrItinClass itin, string OpcodeStr, string Dt,
825 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
826 : N3V<op24, op23, op21_20, op11_8, 1, op4,
827 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
828 OpcodeStr, Dt, "$dst, $src1, $src2", "",
829 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
830 let isCommutable = Commutable;
832 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
833 InstrItinClass itin, string OpcodeStr,
834 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
835 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
836 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
837 OpcodeStr, "$dst, $src1, $src2", "",
838 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]>{
839 let isCommutable = Commutable;
841 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
842 InstrItinClass itin, string OpcodeStr, string Dt,
843 ValueType ResTy, ValueType OpTy, SDNode ShOp>
844 : N3V<1, 1, op21_20, op11_8, 1, 0,
845 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
846 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
847 [(set (ResTy QPR:$dst),
848 (ResTy (ShOp (ResTy QPR:$src1),
849 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
851 let isCommutable = 0;
853 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
854 ValueType ResTy, ValueType OpTy, SDNode ShOp>
855 : N3V<1, 1, op21_20, op11_8, 1, 0,
856 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
857 IIC_VMULi16Q, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
858 [(set (ResTy QPR:$dst),
859 (ResTy (ShOp (ResTy QPR:$src1),
860 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
862 let isCommutable = 0;
865 // Basic 3-register intrinsics, both double- and quad-register.
866 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
867 InstrItinClass itin, string OpcodeStr, string Dt,
868 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
869 : N3V<op24, op23, op21_20, op11_8, 0, op4,
870 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
871 OpcodeStr, Dt, "$dst, $src1, $src2", "",
872 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
873 let isCommutable = Commutable;
875 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
876 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
877 : N3V<0, 1, op21_20, op11_8, 1, 0,
878 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
879 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
881 (Ty (IntOp (Ty DPR:$src1),
882 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
884 let isCommutable = 0;
886 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
887 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
888 : N3V<0, 1, op21_20, op11_8, 1, 0,
889 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
890 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
892 (Ty (IntOp (Ty DPR:$src1),
893 (Ty (NEONvduplane (Ty DPR_8:$src2),
895 let isCommutable = 0;
898 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
899 InstrItinClass itin, string OpcodeStr, string Dt,
900 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
901 : N3V<op24, op23, op21_20, op11_8, 1, op4,
902 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
903 OpcodeStr, Dt, "$dst, $src1, $src2", "",
904 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
905 let isCommutable = Commutable;
907 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
908 string OpcodeStr, string Dt,
909 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
910 : N3V<1, 1, op21_20, op11_8, 1, 0,
911 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
912 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
913 [(set (ResTy QPR:$dst),
914 (ResTy (IntOp (ResTy QPR:$src1),
915 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
917 let isCommutable = 0;
919 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
920 string OpcodeStr, string Dt,
921 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
922 : N3V<1, 1, op21_20, op11_8, 1, 0,
923 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
924 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
925 [(set (ResTy QPR:$dst),
926 (ResTy (IntOp (ResTy QPR:$src1),
927 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
929 let isCommutable = 0;
932 // Multiply-Add/Sub operations: single-, double- and quad-register.
933 class N3VSMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
934 InstrItinClass itin, string OpcodeStr, string Dt,
935 ValueType Ty, SDNode MulOp, SDNode OpNode>
936 : N3V<op24, op23, op21_20, op11_8, 0, op4,
937 (outs DPR_VFP2:$dst),
938 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), itin,
939 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst", []>;
941 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
942 InstrItinClass itin, string OpcodeStr, string Dt,
943 ValueType Ty, SDNode MulOp, SDNode OpNode>
944 : N3V<op24, op23, op21_20, op11_8, 0, op4,
945 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), itin,
946 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
947 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
948 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
949 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
950 string OpcodeStr, string Dt,
951 ValueType Ty, SDNode MulOp, SDNode ShOp>
952 : N3V<0, 1, op21_20, op11_8, 1, 0,
954 (ins DPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
955 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
957 (Ty (ShOp (Ty DPR:$src1),
958 (Ty (MulOp DPR:$src2,
959 (Ty (NEONvduplane (Ty DPR_VFP2:$src3),
961 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
962 string OpcodeStr, string Dt,
963 ValueType Ty, SDNode MulOp, SDNode ShOp>
964 : N3V<0, 1, op21_20, op11_8, 1, 0,
966 (ins DPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
967 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
969 (Ty (ShOp (Ty DPR:$src1),
970 (Ty (MulOp DPR:$src2,
971 (Ty (NEONvduplane (Ty DPR_8:$src3),
974 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
975 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
976 SDNode MulOp, SDNode OpNode>
977 : N3V<op24, op23, op21_20, op11_8, 1, op4,
978 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), itin,
979 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
980 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
981 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
982 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
983 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
984 SDNode MulOp, SDNode ShOp>
985 : N3V<1, 1, op21_20, op11_8, 1, 0,
987 (ins QPR:$src1, QPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
988 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
989 [(set (ResTy QPR:$dst),
990 (ResTy (ShOp (ResTy QPR:$src1),
991 (ResTy (MulOp QPR:$src2,
992 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src3),
994 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
995 string OpcodeStr, string Dt,
996 ValueType ResTy, ValueType OpTy,
997 SDNode MulOp, SDNode ShOp>
998 : N3V<1, 1, op21_20, op11_8, 1, 0,
1000 (ins QPR:$src1, QPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
1001 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1002 [(set (ResTy QPR:$dst),
1003 (ResTy (ShOp (ResTy QPR:$src1),
1004 (ResTy (MulOp QPR:$src2,
1005 (ResTy (NEONvduplane (OpTy DPR_8:$src3),
1008 // Neon 3-argument intrinsics, both double- and quad-register.
1009 // The destination register is also used as the first source operand register.
1010 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1011 InstrItinClass itin, string OpcodeStr, string Dt,
1012 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1013 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1014 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), itin,
1015 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1016 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
1017 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
1018 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1019 InstrItinClass itin, string OpcodeStr, string Dt,
1020 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1021 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1022 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), itin,
1023 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1024 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
1025 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
1027 // Neon Long 3-argument intrinsic. The destination register is
1028 // a quad-register and is also used as the first source operand register.
1029 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1030 InstrItinClass itin, string OpcodeStr, string Dt,
1031 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
1032 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1033 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), itin,
1034 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1036 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
1037 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1038 string OpcodeStr, string Dt,
1039 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1040 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1042 (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
1043 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1044 [(set (ResTy QPR:$dst),
1045 (ResTy (IntOp (ResTy QPR:$src1),
1047 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src3),
1049 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1050 InstrItinClass itin, string OpcodeStr, string Dt,
1051 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1052 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1054 (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
1055 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1056 [(set (ResTy QPR:$dst),
1057 (ResTy (IntOp (ResTy QPR:$src1),
1059 (OpTy (NEONvduplane (OpTy DPR_8:$src3),
1062 // Narrowing 3-register intrinsics.
1063 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1064 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
1065 Intrinsic IntOp, bit Commutable>
1066 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1067 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VBINi4D,
1068 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1069 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
1070 let isCommutable = Commutable;
1073 // Long 3-register intrinsics.
1074 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1075 InstrItinClass itin, string OpcodeStr, string Dt,
1076 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
1077 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1078 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
1079 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1080 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
1081 let isCommutable = Commutable;
1083 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1084 string OpcodeStr, string Dt,
1085 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1086 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1087 (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1088 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1089 [(set (ResTy QPR:$dst),
1090 (ResTy (IntOp (OpTy DPR:$src1),
1091 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1093 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1094 InstrItinClass itin, string OpcodeStr, string Dt,
1095 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1096 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1097 (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1098 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1099 [(set (ResTy QPR:$dst),
1100 (ResTy (IntOp (OpTy DPR:$src1),
1101 (OpTy (NEONvduplane (OpTy DPR_8:$src2),
1104 // Wide 3-register intrinsics.
1105 class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1106 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
1107 Intrinsic IntOp, bit Commutable>
1108 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1109 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), IIC_VSUBiD,
1110 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1111 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
1112 let isCommutable = Commutable;
1115 // Pairwise long 2-register intrinsics, both double- and quad-register.
1116 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1117 bits<2> op17_16, bits<5> op11_7, bit op4,
1118 string OpcodeStr, string Dt,
1119 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1120 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
1121 (ins DPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
1122 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
1123 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1124 bits<2> op17_16, bits<5> op11_7, bit op4,
1125 string OpcodeStr, string Dt,
1126 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1127 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
1128 (ins QPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
1129 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
1131 // Pairwise long 2-register accumulate intrinsics,
1132 // both double- and quad-register.
1133 // The destination register is also used as the first source operand register.
1134 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1135 bits<2> op17_16, bits<5> op11_7, bit op4,
1136 string OpcodeStr, string Dt,
1137 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1138 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
1139 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), IIC_VPALiD,
1140 OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
1141 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
1142 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1143 bits<2> op17_16, bits<5> op11_7, bit op4,
1144 string OpcodeStr, string Dt,
1145 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1146 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
1147 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VPALiQ,
1148 OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
1149 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
1151 // Shift by immediate,
1152 // both double- and quad-register.
1153 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1154 InstrItinClass itin, string OpcodeStr, string Dt,
1155 ValueType Ty, SDNode OpNode>
1156 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1157 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), itin,
1158 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1159 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
1160 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1161 InstrItinClass itin, string OpcodeStr, string Dt,
1162 ValueType Ty, SDNode OpNode>
1163 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1164 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), itin,
1165 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1166 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
1168 // Long shift by immediate.
1169 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1170 string OpcodeStr, string Dt,
1171 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1172 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1173 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VSHLiD,
1174 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1175 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
1176 (i32 imm:$SIMM))))]>;
1178 // Narrow shift by immediate.
1179 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1180 InstrItinClass itin, string OpcodeStr, string Dt,
1181 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1182 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1183 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), itin,
1184 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1185 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
1186 (i32 imm:$SIMM))))]>;
1188 // Shift right by immediate and accumulate,
1189 // both double- and quad-register.
1190 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1191 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1192 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1193 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), IIC_VPALiD,
1194 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1195 [(set DPR:$dst, (Ty (add DPR:$src1,
1196 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
1197 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1198 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1199 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1200 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), IIC_VPALiD,
1201 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1202 [(set QPR:$dst, (Ty (add QPR:$src1,
1203 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
1205 // Shift by immediate and insert,
1206 // both double- and quad-register.
1207 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1208 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1209 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1210 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), IIC_VSHLiD,
1211 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1212 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
1213 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1214 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1215 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1216 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), IIC_VSHLiQ,
1217 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1218 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
1220 // Convert, with fractional bits immediate,
1221 // both double- and quad-register.
1222 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1223 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1225 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1226 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VUNAD,
1227 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1228 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
1229 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1230 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1232 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1233 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), IIC_VUNAQ,
1234 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1235 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
1237 //===----------------------------------------------------------------------===//
1239 //===----------------------------------------------------------------------===//
1241 // Abbreviations used in multiclass suffixes:
1242 // Q = quarter int (8 bit) elements
1243 // H = half int (16 bit) elements
1244 // S = single int (32 bit) elements
1245 // D = double int (64 bit) elements
1247 // Neon 2-register vector operations -- for disassembly only.
1249 // First with only element sizes of 8, 16 and 32 bits:
1250 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1251 bits<5> op11_7, bit op4, string opc, string Dt,
1253 // 64-bit vector types.
1254 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
1255 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1256 opc, !strconcat(Dt, "8"), asm, "", []>;
1257 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
1258 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1259 opc, !strconcat(Dt, "16"), asm, "", []>;
1260 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
1261 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1262 opc, !strconcat(Dt, "32"), asm, "", []>;
1263 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
1264 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1265 opc, "f32", asm, "", []> {
1266 let Inst{10} = 1; // overwrite F = 1
1269 // 128-bit vector types.
1270 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
1271 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1272 opc, !strconcat(Dt, "8"), asm, "", []>;
1273 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
1274 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1275 opc, !strconcat(Dt, "16"), asm, "", []>;
1276 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
1277 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1278 opc, !strconcat(Dt, "32"), asm, "", []>;
1279 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
1280 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1281 opc, "f32", asm, "", []> {
1282 let Inst{10} = 1; // overwrite F = 1
1286 // Neon 3-register vector operations.
1288 // First with only element sizes of 8, 16 and 32 bits:
1289 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1290 InstrItinClass itinD16, InstrItinClass itinD32,
1291 InstrItinClass itinQ16, InstrItinClass itinQ32,
1292 string OpcodeStr, string Dt,
1293 SDNode OpNode, bit Commutable = 0> {
1294 // 64-bit vector types.
1295 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
1296 OpcodeStr, !strconcat(Dt, "8"),
1297 v8i8, v8i8, OpNode, Commutable>;
1298 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
1299 OpcodeStr, !strconcat(Dt, "16"),
1300 v4i16, v4i16, OpNode, Commutable>;
1301 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
1302 OpcodeStr, !strconcat(Dt, "32"),
1303 v2i32, v2i32, OpNode, Commutable>;
1305 // 128-bit vector types.
1306 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
1307 OpcodeStr, !strconcat(Dt, "8"),
1308 v16i8, v16i8, OpNode, Commutable>;
1309 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
1310 OpcodeStr, !strconcat(Dt, "16"),
1311 v8i16, v8i16, OpNode, Commutable>;
1312 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
1313 OpcodeStr, !strconcat(Dt, "32"),
1314 v4i32, v4i32, OpNode, Commutable>;
1317 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, string Dt, SDNode ShOp> {
1318 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
1320 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, !strconcat(Dt,"32"),
1322 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
1323 v8i16, v4i16, ShOp>;
1324 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, !strconcat(Dt,"32"),
1325 v4i32, v2i32, ShOp>;
1328 // ....then also with element size 64 bits:
1329 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1330 InstrItinClass itinD, InstrItinClass itinQ,
1331 string OpcodeStr, string Dt,
1332 SDNode OpNode, bit Commutable = 0>
1333 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
1334 OpcodeStr, Dt, OpNode, Commutable> {
1335 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
1336 OpcodeStr, !strconcat(Dt, "64"),
1337 v1i64, v1i64, OpNode, Commutable>;
1338 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
1339 OpcodeStr, !strconcat(Dt, "64"),
1340 v2i64, v2i64, OpNode, Commutable>;
1344 // Neon Narrowing 2-register vector intrinsics,
1345 // source operand element sizes of 16, 32 and 64 bits:
1346 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1347 bits<5> op11_7, bit op6, bit op4,
1348 InstrItinClass itin, string OpcodeStr, string Dt,
1350 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
1351 itin, OpcodeStr, !strconcat(Dt, "16"),
1352 v8i8, v8i16, IntOp>;
1353 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
1354 itin, OpcodeStr, !strconcat(Dt, "32"),
1355 v4i16, v4i32, IntOp>;
1356 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
1357 itin, OpcodeStr, !strconcat(Dt, "64"),
1358 v2i32, v2i64, IntOp>;
1362 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
1363 // source operand element sizes of 16, 32 and 64 bits:
1364 multiclass N2VLInt_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
1365 string OpcodeStr, string Dt, Intrinsic IntOp> {
1366 def v8i16 : N2VLInt<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1367 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
1368 def v4i32 : N2VLInt<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1369 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
1370 def v2i64 : N2VLInt<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1371 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1375 // Neon 3-register vector intrinsics.
1377 // First with only element sizes of 16 and 32 bits:
1378 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1379 InstrItinClass itinD16, InstrItinClass itinD32,
1380 InstrItinClass itinQ16, InstrItinClass itinQ32,
1381 string OpcodeStr, string Dt,
1382 Intrinsic IntOp, bit Commutable = 0> {
1383 // 64-bit vector types.
1384 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, itinD16,
1385 OpcodeStr, !strconcat(Dt, "16"),
1386 v4i16, v4i16, IntOp, Commutable>;
1387 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, itinD32,
1388 OpcodeStr, !strconcat(Dt, "32"),
1389 v2i32, v2i32, IntOp, Commutable>;
1391 // 128-bit vector types.
1392 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, itinQ16,
1393 OpcodeStr, !strconcat(Dt, "16"),
1394 v8i16, v8i16, IntOp, Commutable>;
1395 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, itinQ32,
1396 OpcodeStr, !strconcat(Dt, "32"),
1397 v4i32, v4i32, IntOp, Commutable>;
1400 multiclass N3VIntSL_HS<bits<4> op11_8,
1401 InstrItinClass itinD16, InstrItinClass itinD32,
1402 InstrItinClass itinQ16, InstrItinClass itinQ32,
1403 string OpcodeStr, string Dt, Intrinsic IntOp> {
1404 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
1405 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
1406 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
1407 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
1408 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
1409 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
1410 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
1411 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
1414 // ....then also with element size of 8 bits:
1415 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1416 InstrItinClass itinD16, InstrItinClass itinD32,
1417 InstrItinClass itinQ16, InstrItinClass itinQ32,
1418 string OpcodeStr, string Dt,
1419 Intrinsic IntOp, bit Commutable = 0>
1420 : N3VInt_HS<op24, op23, op11_8, op4, itinD16, itinD32, itinQ16, itinQ32,
1421 OpcodeStr, Dt, IntOp, Commutable> {
1422 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, itinD16,
1423 OpcodeStr, !strconcat(Dt, "8"),
1424 v8i8, v8i8, IntOp, Commutable>;
1425 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, itinQ16,
1426 OpcodeStr, !strconcat(Dt, "8"),
1427 v16i8, v16i8, IntOp, Commutable>;
1430 // ....then also with element size of 64 bits:
1431 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1432 InstrItinClass itinD16, InstrItinClass itinD32,
1433 InstrItinClass itinQ16, InstrItinClass itinQ32,
1434 string OpcodeStr, string Dt,
1435 Intrinsic IntOp, bit Commutable = 0>
1436 : N3VInt_QHS<op24, op23, op11_8, op4, itinD16, itinD32, itinQ16, itinQ32,
1437 OpcodeStr, Dt, IntOp, Commutable> {
1438 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, itinD32,
1439 OpcodeStr, !strconcat(Dt, "64"),
1440 v1i64, v1i64, IntOp, Commutable>;
1441 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, itinQ32,
1442 OpcodeStr, !strconcat(Dt, "64"),
1443 v2i64, v2i64, IntOp, Commutable>;
1447 // Neon Narrowing 3-register vector intrinsics,
1448 // source operand element sizes of 16, 32 and 64 bits:
1449 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1450 string OpcodeStr, string Dt,
1451 Intrinsic IntOp, bit Commutable = 0> {
1452 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
1453 OpcodeStr, !strconcat(Dt, "16"),
1454 v8i8, v8i16, IntOp, Commutable>;
1455 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
1456 OpcodeStr, !strconcat(Dt, "32"),
1457 v4i16, v4i32, IntOp, Commutable>;
1458 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
1459 OpcodeStr, !strconcat(Dt, "64"),
1460 v2i32, v2i64, IntOp, Commutable>;
1464 // Neon Long 3-register vector intrinsics.
1466 // First with only element sizes of 16 and 32 bits:
1467 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1468 InstrItinClass itin, string OpcodeStr, string Dt,
1469 Intrinsic IntOp, bit Commutable = 0> {
1470 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin,
1471 OpcodeStr, !strconcat(Dt, "16"),
1472 v4i32, v4i16, IntOp, Commutable>;
1473 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin,
1474 OpcodeStr, !strconcat(Dt, "32"),
1475 v2i64, v2i32, IntOp, Commutable>;
1478 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
1479 InstrItinClass itin, string OpcodeStr, string Dt,
1481 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
1482 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
1483 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
1484 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1487 // ....then also with element size of 8 bits:
1488 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1489 InstrItinClass itin, string OpcodeStr, string Dt,
1490 Intrinsic IntOp, bit Commutable = 0>
1491 : N3VLInt_HS<op24, op23, op11_8, op4, itin, OpcodeStr, Dt,
1492 IntOp, Commutable> {
1493 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin,
1494 OpcodeStr, !strconcat(Dt, "8"),
1495 v8i16, v8i8, IntOp, Commutable>;
1499 // Neon Wide 3-register vector intrinsics,
1500 // source operand element sizes of 8, 16 and 32 bits:
1501 multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1502 string OpcodeStr, string Dt,
1503 Intrinsic IntOp, bit Commutable = 0> {
1504 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4,
1505 OpcodeStr, !strconcat(Dt, "8"),
1506 v8i16, v8i8, IntOp, Commutable>;
1507 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4,
1508 OpcodeStr, !strconcat(Dt, "16"),
1509 v4i32, v4i16, IntOp, Commutable>;
1510 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4,
1511 OpcodeStr, !strconcat(Dt, "32"),
1512 v2i64, v2i32, IntOp, Commutable>;
1516 // Neon Multiply-Op vector operations,
1517 // element sizes of 8, 16 and 32 bits:
1518 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1519 InstrItinClass itinD16, InstrItinClass itinD32,
1520 InstrItinClass itinQ16, InstrItinClass itinQ32,
1521 string OpcodeStr, string Dt, SDNode OpNode> {
1522 // 64-bit vector types.
1523 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
1524 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
1525 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
1526 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
1527 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
1528 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
1530 // 128-bit vector types.
1531 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
1532 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
1533 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
1534 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
1535 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
1536 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
1539 multiclass N3VMulOpSL_HS<bits<4> op11_8,
1540 InstrItinClass itinD16, InstrItinClass itinD32,
1541 InstrItinClass itinQ16, InstrItinClass itinQ32,
1542 string OpcodeStr, string Dt, SDNode ShOp> {
1543 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
1544 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
1545 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
1546 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
1547 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
1548 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
1550 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
1551 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
1555 // Neon 3-argument intrinsics,
1556 // element sizes of 8, 16 and 32 bits:
1557 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1558 string OpcodeStr, string Dt, Intrinsic IntOp> {
1559 // 64-bit vector types.
1560 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16D,
1561 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
1562 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D,
1563 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
1564 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi32D,
1565 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
1567 // 128-bit vector types.
1568 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16Q,
1569 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
1570 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16Q,
1571 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
1572 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi32Q,
1573 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
1577 // Neon Long 3-argument intrinsics.
1579 // First with only element sizes of 16 and 32 bits:
1580 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1581 string OpcodeStr, string Dt, Intrinsic IntOp> {
1582 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D,
1583 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
1584 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi16D,
1585 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1588 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
1589 string OpcodeStr, string Dt, Intrinsic IntOp> {
1590 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
1591 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
1592 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
1593 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1596 // ....then also with element size of 8 bits:
1597 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1598 string OpcodeStr, string Dt, Intrinsic IntOp>
1599 : N3VLInt3_HS<op24, op23, op11_8, op4, OpcodeStr, Dt, IntOp> {
1600 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16D,
1601 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
1605 // Neon 2-register vector intrinsics,
1606 // element sizes of 8, 16 and 32 bits:
1607 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1608 bits<5> op11_7, bit op4,
1609 InstrItinClass itinD, InstrItinClass itinQ,
1610 string OpcodeStr, string Dt, Intrinsic IntOp> {
1611 // 64-bit vector types.
1612 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1613 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
1614 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1615 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
1616 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1617 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
1619 // 128-bit vector types.
1620 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1621 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
1622 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1623 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
1624 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1625 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
1629 // Neon Pairwise long 2-register intrinsics,
1630 // element sizes of 8, 16 and 32 bits:
1631 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1632 bits<5> op11_7, bit op4,
1633 string OpcodeStr, string Dt, Intrinsic IntOp> {
1634 // 64-bit vector types.
1635 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1636 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
1637 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1638 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
1639 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1640 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
1642 // 128-bit vector types.
1643 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1644 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
1645 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1646 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
1647 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1648 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
1652 // Neon Pairwise long 2-register accumulate intrinsics,
1653 // element sizes of 8, 16 and 32 bits:
1654 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1655 bits<5> op11_7, bit op4,
1656 string OpcodeStr, string Dt, Intrinsic IntOp> {
1657 // 64-bit vector types.
1658 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1659 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
1660 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1661 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
1662 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1663 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
1665 // 128-bit vector types.
1666 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1667 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
1668 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1669 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
1670 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1671 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
1675 // Neon 2-register vector shift by immediate,
1676 // element sizes of 8, 16, 32 and 64 bits:
1677 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1678 InstrItinClass itin, string OpcodeStr, string Dt,
1680 // 64-bit vector types.
1681 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
1682 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
1683 let Inst{21-19} = 0b001; // imm6 = 001xxx
1685 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
1686 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
1687 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1689 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
1690 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
1691 let Inst{21} = 0b1; // imm6 = 1xxxxx
1693 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, itin,
1694 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
1697 // 128-bit vector types.
1698 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
1699 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
1700 let Inst{21-19} = 0b001; // imm6 = 001xxx
1702 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
1703 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
1704 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1706 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
1707 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
1708 let Inst{21} = 0b1; // imm6 = 1xxxxx
1710 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, itin,
1711 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
1716 // Neon Shift-Accumulate vector operations,
1717 // element sizes of 8, 16, 32 and 64 bits:
1718 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1719 string OpcodeStr, string Dt, SDNode ShOp> {
1720 // 64-bit vector types.
1721 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1722 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
1723 let Inst{21-19} = 0b001; // imm6 = 001xxx
1725 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1726 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
1727 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1729 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1730 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
1731 let Inst{21} = 0b1; // imm6 = 1xxxxx
1733 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4,
1734 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
1737 // 128-bit vector types.
1738 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1739 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
1740 let Inst{21-19} = 0b001; // imm6 = 001xxx
1742 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1743 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
1744 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1746 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1747 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
1748 let Inst{21} = 0b1; // imm6 = 1xxxxx
1750 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4,
1751 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
1756 // Neon Shift-Insert vector operations,
1757 // element sizes of 8, 16, 32 and 64 bits:
1758 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1759 string OpcodeStr, SDNode ShOp> {
1760 // 64-bit vector types.
1761 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4,
1762 OpcodeStr, "8", v8i8, ShOp> {
1763 let Inst{21-19} = 0b001; // imm6 = 001xxx
1765 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4,
1766 OpcodeStr, "16", v4i16, ShOp> {
1767 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1769 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4,
1770 OpcodeStr, "32", v2i32, ShOp> {
1771 let Inst{21} = 0b1; // imm6 = 1xxxxx
1773 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4,
1774 OpcodeStr, "64", v1i64, ShOp>;
1777 // 128-bit vector types.
1778 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4,
1779 OpcodeStr, "8", v16i8, ShOp> {
1780 let Inst{21-19} = 0b001; // imm6 = 001xxx
1782 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4,
1783 OpcodeStr, "16", v8i16, ShOp> {
1784 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1786 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4,
1787 OpcodeStr, "32", v4i32, ShOp> {
1788 let Inst{21} = 0b1; // imm6 = 1xxxxx
1790 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4,
1791 OpcodeStr, "64", v2i64, ShOp>;
1795 // Neon Shift Long operations,
1796 // element sizes of 8, 16, 32 bits:
1797 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
1798 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
1799 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1800 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode> {
1801 let Inst{21-19} = 0b001; // imm6 = 001xxx
1803 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1804 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode> {
1805 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1807 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1808 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode> {
1809 let Inst{21} = 0b1; // imm6 = 1xxxxx
1813 // Neon Shift Narrow operations,
1814 // element sizes of 16, 32, 64 bits:
1815 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
1816 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
1818 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
1819 OpcodeStr, !strconcat(Dt, "16"), v8i8, v8i16, OpNode> {
1820 let Inst{21-19} = 0b001; // imm6 = 001xxx
1822 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
1823 OpcodeStr, !strconcat(Dt, "32"), v4i16, v4i32, OpNode> {
1824 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1826 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
1827 OpcodeStr, !strconcat(Dt, "64"), v2i32, v2i64, OpNode> {
1828 let Inst{21} = 0b1; // imm6 = 1xxxxx
1832 //===----------------------------------------------------------------------===//
1833 // Instruction Definitions.
1834 //===----------------------------------------------------------------------===//
1836 // Vector Add Operations.
1838 // VADD : Vector Add (integer and floating-point)
1839 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
1841 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
1842 v2f32, v2f32, fadd, 1>;
1843 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
1844 v4f32, v4f32, fadd, 1>;
1845 // VADDL : Vector Add Long (Q = D + D)
1846 defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, IIC_VSHLiD, "vaddl", "s",
1847 int_arm_neon_vaddls, 1>;
1848 defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, IIC_VSHLiD, "vaddl", "u",
1849 int_arm_neon_vaddlu, 1>;
1850 // VADDW : Vector Add Wide (Q = Q + D)
1851 defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw", "s", int_arm_neon_vaddws, 0>;
1852 defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw", "u", int_arm_neon_vaddwu, 0>;
1853 // VHADD : Vector Halving Add
1854 defm VHADDs : N3VInt_QHS<0,0,0b0000,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1855 IIC_VBINi4Q, "vhadd", "s", int_arm_neon_vhadds, 1>;
1856 defm VHADDu : N3VInt_QHS<1,0,0b0000,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1857 IIC_VBINi4Q, "vhadd", "u", int_arm_neon_vhaddu, 1>;
1858 // VRHADD : Vector Rounding Halving Add
1859 defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1860 IIC_VBINi4Q, "vrhadd", "s", int_arm_neon_vrhadds, 1>;
1861 defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1862 IIC_VBINi4Q, "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
1863 // VQADD : Vector Saturating Add
1864 defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1865 IIC_VBINi4Q, "vqadd", "s", int_arm_neon_vqadds, 1>;
1866 defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1867 IIC_VBINi4Q, "vqadd", "u", int_arm_neon_vqaddu, 1>;
1868 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
1869 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
1870 int_arm_neon_vaddhn, 1>;
1871 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
1872 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
1873 int_arm_neon_vraddhn, 1>;
1875 // Vector Multiply Operations.
1877 // VMUL : Vector Multiply (integer, polynomial and floating-point)
1878 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
1879 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
1880 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16D, "vmul", "p8",
1881 v8i8, v8i8, int_arm_neon_vmulp, 1>;
1882 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16Q, "vmul", "p8",
1883 v16i8, v16i8, int_arm_neon_vmulp, 1>;
1884 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VBIND, "vmul", "f32",
1885 v2f32, v2f32, fmul, 1>;
1886 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VBINQ, "vmul", "f32",
1887 v4f32, v4f32, fmul, 1>;
1888 defm VMULsl : N3VSL_HS<0b1000, "vmul", "i", mul>;
1889 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
1890 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
1893 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
1894 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
1895 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
1896 (v4i16 (EXTRACT_SUBREG QPR:$src2,
1897 (DSubReg_i16_reg imm:$lane))),
1898 (SubReg_i16_lane imm:$lane)))>;
1899 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
1900 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
1901 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
1902 (v2i32 (EXTRACT_SUBREG QPR:$src2,
1903 (DSubReg_i32_reg imm:$lane))),
1904 (SubReg_i32_lane imm:$lane)))>;
1905 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
1906 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
1907 (v4f32 (VMULslfq (v4f32 QPR:$src1),
1908 (v2f32 (EXTRACT_SUBREG QPR:$src2,
1909 (DSubReg_i32_reg imm:$lane))),
1910 (SubReg_i32_lane imm:$lane)))>;
1912 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
1913 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, IIC_VMULi16D, IIC_VMULi32D,
1914 IIC_VMULi16Q, IIC_VMULi32Q,
1915 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
1916 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
1917 IIC_VMULi16Q, IIC_VMULi32Q,
1918 "vqdmulh", "s", int_arm_neon_vqdmulh>;
1919 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
1920 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
1922 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
1923 (v4i16 (EXTRACT_SUBREG QPR:$src2,
1924 (DSubReg_i16_reg imm:$lane))),
1925 (SubReg_i16_lane imm:$lane)))>;
1926 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
1927 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
1929 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
1930 (v2i32 (EXTRACT_SUBREG QPR:$src2,
1931 (DSubReg_i32_reg imm:$lane))),
1932 (SubReg_i32_lane imm:$lane)))>;
1934 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
1935 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, IIC_VMULi16D, IIC_VMULi32D,
1936 IIC_VMULi16Q, IIC_VMULi32Q,
1937 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
1938 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
1939 IIC_VMULi16Q, IIC_VMULi32Q,
1940 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
1941 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
1942 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
1944 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
1945 (v4i16 (EXTRACT_SUBREG QPR:$src2,
1946 (DSubReg_i16_reg imm:$lane))),
1947 (SubReg_i16_lane imm:$lane)))>;
1948 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
1949 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
1951 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
1952 (v2i32 (EXTRACT_SUBREG QPR:$src2,
1953 (DSubReg_i32_reg imm:$lane))),
1954 (SubReg_i32_lane imm:$lane)))>;
1956 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
1957 defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, IIC_VMULi16D, "vmull", "s",
1958 int_arm_neon_vmulls, 1>;
1959 defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, IIC_VMULi16D, "vmull", "u",
1960 int_arm_neon_vmullu, 1>;
1961 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
1962 v8i16, v8i8, int_arm_neon_vmullp, 1>;
1963 defm VMULLsls : N3VLIntSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s",
1964 int_arm_neon_vmulls>;
1965 defm VMULLslu : N3VLIntSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u",
1966 int_arm_neon_vmullu>;
1968 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
1969 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, "vqdmull", "s",
1970 int_arm_neon_vqdmull, 1>;
1971 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D, "vqdmull", "s",
1972 int_arm_neon_vqdmull>;
1974 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
1976 // VMLA : Vector Multiply Accumulate (integer and floating-point)
1977 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
1978 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
1979 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
1981 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
1983 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
1984 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
1985 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
1987 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
1988 v4f32, v2f32, fmul, fadd>;
1990 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
1991 (mul (v8i16 QPR:$src2),
1992 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
1993 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
1994 (v4i16 (EXTRACT_SUBREG QPR:$src3,
1995 (DSubReg_i16_reg imm:$lane))),
1996 (SubReg_i16_lane imm:$lane)))>;
1998 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
1999 (mul (v4i32 QPR:$src2),
2000 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
2001 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
2002 (v2i32 (EXTRACT_SUBREG QPR:$src3,
2003 (DSubReg_i32_reg imm:$lane))),
2004 (SubReg_i32_lane imm:$lane)))>;
2006 def : Pat<(v4f32 (fadd (v4f32 QPR:$src1),
2007 (fmul (v4f32 QPR:$src2),
2008 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
2009 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
2011 (v2f32 (EXTRACT_SUBREG QPR:$src3,
2012 (DSubReg_i32_reg imm:$lane))),
2013 (SubReg_i32_lane imm:$lane)))>;
2015 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
2016 defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal", "s", int_arm_neon_vmlals>;
2017 defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal", "u", int_arm_neon_vmlalu>;
2019 defm VMLALsls : N3VLInt3SL_HS<0, 0b0010, "vmlal", "s", int_arm_neon_vmlals>;
2020 defm VMLALslu : N3VLInt3SL_HS<1, 0b0010, "vmlal", "u", int_arm_neon_vmlalu>;
2022 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
2023 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal", "s",
2024 int_arm_neon_vqdmlal>;
2025 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
2027 // VMLS : Vector Multiply Subtract (integer and floating-point)
2028 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
2029 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
2030 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
2032 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
2034 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
2035 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
2036 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
2038 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
2039 v4f32, v2f32, fmul, fsub>;
2041 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
2042 (mul (v8i16 QPR:$src2),
2043 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
2044 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
2045 (v4i16 (EXTRACT_SUBREG QPR:$src3,
2046 (DSubReg_i16_reg imm:$lane))),
2047 (SubReg_i16_lane imm:$lane)))>;
2049 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
2050 (mul (v4i32 QPR:$src2),
2051 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
2052 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
2053 (v2i32 (EXTRACT_SUBREG QPR:$src3,
2054 (DSubReg_i32_reg imm:$lane))),
2055 (SubReg_i32_lane imm:$lane)))>;
2057 def : Pat<(v4f32 (fsub (v4f32 QPR:$src1),
2058 (fmul (v4f32 QPR:$src2),
2059 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
2060 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
2061 (v2f32 (EXTRACT_SUBREG QPR:$src3,
2062 (DSubReg_i32_reg imm:$lane))),
2063 (SubReg_i32_lane imm:$lane)))>;
2065 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
2066 defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl", "s", int_arm_neon_vmlsls>;
2067 defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl", "u", int_arm_neon_vmlslu>;
2069 defm VMLSLsls : N3VLInt3SL_HS<0, 0b0110, "vmlsl", "s", int_arm_neon_vmlsls>;
2070 defm VMLSLslu : N3VLInt3SL_HS<1, 0b0110, "vmlsl", "u", int_arm_neon_vmlslu>;
2072 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
2073 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl", "s",
2074 int_arm_neon_vqdmlsl>;
2075 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
2077 // Vector Subtract Operations.
2079 // VSUB : Vector Subtract (integer and floating-point)
2080 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
2081 "vsub", "i", sub, 0>;
2082 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
2083 v2f32, v2f32, fsub, 0>;
2084 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
2085 v4f32, v4f32, fsub, 0>;
2086 // VSUBL : Vector Subtract Long (Q = D - D)
2087 defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, IIC_VSHLiD, "vsubl", "s",
2088 int_arm_neon_vsubls, 1>;
2089 defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, IIC_VSHLiD, "vsubl", "u",
2090 int_arm_neon_vsublu, 1>;
2091 // VSUBW : Vector Subtract Wide (Q = Q - D)
2092 defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw", "s", int_arm_neon_vsubws, 0>;
2093 defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw", "u", int_arm_neon_vsubwu, 0>;
2094 // VHSUB : Vector Halving Subtract
2095 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D,
2096 IIC_VBINi4Q, IIC_VBINi4Q,
2097 "vhsub", "s", int_arm_neon_vhsubs, 0>;
2098 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D,
2099 IIC_VBINi4Q, IIC_VBINi4Q,
2100 "vhsub", "u", int_arm_neon_vhsubu, 0>;
2101 // VQSUB : Vector Saturing Subtract
2102 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D,
2103 IIC_VBINi4Q, IIC_VBINi4Q,
2104 "vqsub", "s", int_arm_neon_vqsubs, 0>;
2105 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D,
2106 IIC_VBINi4Q, IIC_VBINi4Q,
2107 "vqsub", "u", int_arm_neon_vqsubu, 0>;
2108 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
2109 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
2110 int_arm_neon_vsubhn, 0>;
2111 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
2112 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
2113 int_arm_neon_vrsubhn, 0>;
2115 // Vector Comparisons.
2117 // VCEQ : Vector Compare Equal
2118 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2119 IIC_VBINi4Q, "vceq", "i", NEONvceq, 1>;
2120 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
2122 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
2124 // For disassembly only.
2125 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
2128 // VCGE : Vector Compare Greater Than or Equal
2129 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2130 IIC_VBINi4Q, "vcge", "s", NEONvcge, 0>;
2131 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2132 IIC_VBINi4Q, "vcge", "u", NEONvcgeu, 0>;
2133 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32",
2134 v2i32, v2f32, NEONvcge, 0>;
2135 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
2137 // For disassembly only.
2138 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
2140 // For disassembly only.
2141 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
2144 // VCGT : Vector Compare Greater Than
2145 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2146 IIC_VBINi4Q, "vcgt", "s", NEONvcgt, 0>;
2147 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2148 IIC_VBINi4Q, "vcgt", "u", NEONvcgtu, 0>;
2149 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
2151 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
2153 // For disassembly only.
2154 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
2156 // For disassembly only.
2157 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
2160 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
2161 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, IIC_VBIND, "vacge", "f32",
2162 v2i32, v2f32, int_arm_neon_vacged, 0>;
2163 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, IIC_VBINQ, "vacge", "f32",
2164 v4i32, v4f32, int_arm_neon_vacgeq, 0>;
2165 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
2166 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, IIC_VBIND, "vacgt", "f32",
2167 v2i32, v2f32, int_arm_neon_vacgtd, 0>;
2168 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, IIC_VBINQ, "vacgt", "f32",
2169 v4i32, v4f32, int_arm_neon_vacgtq, 0>;
2170 // VTST : Vector Test Bits
2171 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2172 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
2174 // Vector Bitwise Operations.
2176 // VAND : Vector Bitwise AND
2177 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
2178 v2i32, v2i32, and, 1>;
2179 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
2180 v4i32, v4i32, and, 1>;
2182 // VEOR : Vector Bitwise Exclusive OR
2183 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
2184 v2i32, v2i32, xor, 1>;
2185 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
2186 v4i32, v4i32, xor, 1>;
2188 // VORR : Vector Bitwise OR
2189 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
2190 v2i32, v2i32, or, 1>;
2191 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
2192 v4i32, v4i32, or, 1>;
2194 // VBIC : Vector Bitwise Bit Clear (AND NOT)
2195 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
2196 (ins DPR:$src1, DPR:$src2), IIC_VBINiD,
2197 "vbic", "$dst, $src1, $src2", "",
2198 [(set DPR:$dst, (v2i32 (and DPR:$src1,
2199 (vnot_conv DPR:$src2))))]>;
2200 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
2201 (ins QPR:$src1, QPR:$src2), IIC_VBINiQ,
2202 "vbic", "$dst, $src1, $src2", "",
2203 [(set QPR:$dst, (v4i32 (and QPR:$src1,
2204 (vnot_conv QPR:$src2))))]>;
2206 // VORN : Vector Bitwise OR NOT
2207 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
2208 (ins DPR:$src1, DPR:$src2), IIC_VBINiD,
2209 "vorn", "$dst, $src1, $src2", "",
2210 [(set DPR:$dst, (v2i32 (or DPR:$src1,
2211 (vnot_conv DPR:$src2))))]>;
2212 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
2213 (ins QPR:$src1, QPR:$src2), IIC_VBINiQ,
2214 "vorn", "$dst, $src1, $src2", "",
2215 [(set QPR:$dst, (v4i32 (or QPR:$src1,
2216 (vnot_conv QPR:$src2))))]>;
2218 // VMVN : Vector Bitwise NOT
2219 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
2220 (outs DPR:$dst), (ins DPR:$src), IIC_VSHLiD,
2221 "vmvn", "$dst, $src", "",
2222 [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>;
2223 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
2224 (outs QPR:$dst), (ins QPR:$src), IIC_VSHLiD,
2225 "vmvn", "$dst, $src", "",
2226 [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>;
2227 def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>;
2228 def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>;
2230 // VBSL : Vector Bitwise Select
2231 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
2232 (ins DPR:$src1, DPR:$src2, DPR:$src3), IIC_VCNTiD,
2233 "vbsl", "$dst, $src2, $src3", "$src1 = $dst",
2235 (v2i32 (or (and DPR:$src2, DPR:$src1),
2236 (and DPR:$src3, (vnot_conv DPR:$src1)))))]>;
2237 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
2238 (ins QPR:$src1, QPR:$src2, QPR:$src3), IIC_VCNTiQ,
2239 "vbsl", "$dst, $src2, $src3", "$src1 = $dst",
2241 (v4i32 (or (and QPR:$src2, QPR:$src1),
2242 (and QPR:$src3, (vnot_conv QPR:$src1)))))]>;
2244 // VBIF : Vector Bitwise Insert if False
2245 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
2246 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
2247 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
2248 IIC_VBINiD, "vbif", "$dst, $src2, $src3", "$src1 = $dst",
2249 [/* For disassembly only; pattern left blank */]>;
2250 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
2251 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
2252 IIC_VBINiQ, "vbif", "$dst, $src2, $src3", "$src1 = $dst",
2253 [/* For disassembly only; pattern left blank */]>;
2255 // VBIT : Vector Bitwise Insert if True
2256 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
2257 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
2258 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
2259 IIC_VBINiD, "vbit", "$dst, $src2, $src3", "$src1 = $dst",
2260 [/* For disassembly only; pattern left blank */]>;
2261 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
2262 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
2263 IIC_VBINiQ, "vbit", "$dst, $src2, $src3", "$src1 = $dst",
2264 [/* For disassembly only; pattern left blank */]>;
2266 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
2267 // for equivalent operations with different register constraints; it just
2270 // Vector Absolute Differences.
2272 // VABD : Vector Absolute Difference
2273 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D,
2274 IIC_VBINi4Q, IIC_VBINi4Q,
2275 "vabd", "s", int_arm_neon_vabds, 0>;
2276 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D,
2277 IIC_VBINi4Q, IIC_VBINi4Q,
2278 "vabd", "u", int_arm_neon_vabdu, 0>;
2279 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, IIC_VBIND,
2280 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 0>;
2281 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, IIC_VBINQ,
2282 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 0>;
2284 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
2285 defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, IIC_VBINi4Q,
2286 "vabdl", "s", int_arm_neon_vabdls, 0>;
2287 defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, IIC_VBINi4Q,
2288 "vabdl", "u", int_arm_neon_vabdlu, 0>;
2290 // VABA : Vector Absolute Difference and Accumulate
2291 defm VABAs : N3VInt3_QHS<0,0,0b0111,1, "vaba", "s", int_arm_neon_vabas>;
2292 defm VABAu : N3VInt3_QHS<1,0,0b0111,1, "vaba", "u", int_arm_neon_vabau>;
2294 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
2295 defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, "vabal", "s", int_arm_neon_vabals>;
2296 defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal", "u", int_arm_neon_vabalu>;
2298 // Vector Maximum and Minimum.
2300 // VMAX : Vector Maximum
2301 defm VMAXs : N3VInt_QHS<0,0,0b0110,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2302 IIC_VBINi4Q, "vmax", "s", int_arm_neon_vmaxs, 1>;
2303 defm VMAXu : N3VInt_QHS<1,0,0b0110,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2304 IIC_VBINi4Q, "vmax", "u", int_arm_neon_vmaxu, 1>;
2305 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, IIC_VBIND, "vmax", "f32",
2306 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
2307 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, IIC_VBINQ, "vmax", "f32",
2308 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
2310 // VMIN : Vector Minimum
2311 defm VMINs : N3VInt_QHS<0,0,0b0110,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2312 IIC_VBINi4Q, "vmin", "s", int_arm_neon_vmins, 1>;
2313 defm VMINu : N3VInt_QHS<1,0,0b0110,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2314 IIC_VBINi4Q, "vmin", "u", int_arm_neon_vminu, 1>;
2315 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, IIC_VBIND, "vmin", "f32",
2316 v2f32, v2f32, int_arm_neon_vmins, 1>;
2317 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, IIC_VBINQ, "vmin", "f32",
2318 v4f32, v4f32, int_arm_neon_vmins, 1>;
2320 // Vector Pairwise Operations.
2322 // VPADD : Vector Pairwise Add
2323 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, IIC_VBINiD, "vpadd", "i8",
2324 v8i8, v8i8, int_arm_neon_vpadd, 0>;
2325 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, IIC_VBINiD, "vpadd", "i16",
2326 v4i16, v4i16, int_arm_neon_vpadd, 0>;
2327 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, IIC_VBINiD, "vpadd", "i32",
2328 v2i32, v2i32, int_arm_neon_vpadd, 0>;
2329 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, IIC_VBIND, "vpadd", "f32",
2330 v2f32, v2f32, int_arm_neon_vpadd, 0>;
2332 // VPADDL : Vector Pairwise Add Long
2333 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
2334 int_arm_neon_vpaddls>;
2335 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
2336 int_arm_neon_vpaddlu>;
2338 // VPADAL : Vector Pairwise Add and Accumulate Long
2339 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
2340 int_arm_neon_vpadals>;
2341 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
2342 int_arm_neon_vpadalu>;
2344 // VPMAX : Vector Pairwise Maximum
2345 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, IIC_VBINi4D, "vpmax", "s8",
2346 v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
2347 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, IIC_VBINi4D, "vpmax", "s16",
2348 v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
2349 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, IIC_VBINi4D, "vpmax", "s32",
2350 v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
2351 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, IIC_VBINi4D, "vpmax", "u8",
2352 v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
2353 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, IIC_VBINi4D, "vpmax", "u16",
2354 v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
2355 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, IIC_VBINi4D, "vpmax", "u32",
2356 v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
2357 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, IIC_VBINi4D, "vpmax", "f32",
2358 v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
2360 // VPMIN : Vector Pairwise Minimum
2361 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, IIC_VBINi4D, "vpmin", "s8",
2362 v8i8, v8i8, int_arm_neon_vpmins, 0>;
2363 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, IIC_VBINi4D, "vpmin", "s16",
2364 v4i16, v4i16, int_arm_neon_vpmins, 0>;
2365 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, IIC_VBINi4D, "vpmin", "s32",
2366 v2i32, v2i32, int_arm_neon_vpmins, 0>;
2367 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, IIC_VBINi4D, "vpmin", "u8",
2368 v8i8, v8i8, int_arm_neon_vpminu, 0>;
2369 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, IIC_VBINi4D, "vpmin", "u16",
2370 v4i16, v4i16, int_arm_neon_vpminu, 0>;
2371 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, IIC_VBINi4D, "vpmin", "u32",
2372 v2i32, v2i32, int_arm_neon_vpminu, 0>;
2373 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, IIC_VBINi4D, "vpmin", "f32",
2374 v2f32, v2f32, int_arm_neon_vpmins, 0>;
2376 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
2378 // VRECPE : Vector Reciprocal Estimate
2379 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
2380 IIC_VUNAD, "vrecpe", "u32",
2381 v2i32, v2i32, int_arm_neon_vrecpe>;
2382 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
2383 IIC_VUNAQ, "vrecpe", "u32",
2384 v4i32, v4i32, int_arm_neon_vrecpe>;
2385 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
2386 IIC_VUNAD, "vrecpe", "f32",
2387 v2f32, v2f32, int_arm_neon_vrecpe>;
2388 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
2389 IIC_VUNAQ, "vrecpe", "f32",
2390 v4f32, v4f32, int_arm_neon_vrecpe>;
2392 // VRECPS : Vector Reciprocal Step
2393 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1,
2394 IIC_VRECSD, "vrecps", "f32",
2395 v2f32, v2f32, int_arm_neon_vrecps, 1>;
2396 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1,
2397 IIC_VRECSQ, "vrecps", "f32",
2398 v4f32, v4f32, int_arm_neon_vrecps, 1>;
2400 // VRSQRTE : Vector Reciprocal Square Root Estimate
2401 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
2402 IIC_VUNAD, "vrsqrte", "u32",
2403 v2i32, v2i32, int_arm_neon_vrsqrte>;
2404 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
2405 IIC_VUNAQ, "vrsqrte", "u32",
2406 v4i32, v4i32, int_arm_neon_vrsqrte>;
2407 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
2408 IIC_VUNAD, "vrsqrte", "f32",
2409 v2f32, v2f32, int_arm_neon_vrsqrte>;
2410 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
2411 IIC_VUNAQ, "vrsqrte", "f32",
2412 v4f32, v4f32, int_arm_neon_vrsqrte>;
2414 // VRSQRTS : Vector Reciprocal Square Root Step
2415 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1,
2416 IIC_VRECSD, "vrsqrts", "f32",
2417 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
2418 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1,
2419 IIC_VRECSQ, "vrsqrts", "f32",
2420 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
2424 // VSHL : Vector Shift
2425 defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
2426 IIC_VSHLiQ, "vshl", "s", int_arm_neon_vshifts, 0>;
2427 defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
2428 IIC_VSHLiQ, "vshl", "u", int_arm_neon_vshiftu, 0>;
2429 // VSHL : Vector Shift Left (Immediate)
2430 defm VSHLi : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
2431 // VSHR : Vector Shift Right (Immediate)
2432 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", NEONvshrs>;
2433 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", NEONvshru>;
2435 // VSHLL : Vector Shift Left Long
2436 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
2437 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
2439 // VSHLL : Vector Shift Left Long (with maximum shift count)
2440 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
2441 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
2442 ValueType OpTy, SDNode OpNode>
2443 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
2444 ResTy, OpTy, OpNode> {
2445 let Inst{21-16} = op21_16;
2447 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
2448 v8i16, v8i8, NEONvshlli>;
2449 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
2450 v4i32, v4i16, NEONvshlli>;
2451 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
2452 v2i64, v2i32, NEONvshlli>;
2454 // VSHRN : Vector Shift Right and Narrow
2455 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
2458 // VRSHL : Vector Rounding Shift
2459 defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2460 IIC_VSHLi4Q, "vrshl", "s", int_arm_neon_vrshifts,0>;
2461 defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2462 IIC_VSHLi4Q, "vrshl", "u", int_arm_neon_vrshiftu,0>;
2463 // VRSHR : Vector Rounding Shift Right
2464 defm VRSHRs : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs>;
2465 defm VRSHRu : N2VSh_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", NEONvrshru>;
2467 // VRSHRN : Vector Rounding Shift Right and Narrow
2468 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
2471 // VQSHL : Vector Saturating Shift
2472 defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2473 IIC_VSHLi4Q, "vqshl", "s", int_arm_neon_vqshifts,0>;
2474 defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2475 IIC_VSHLi4Q, "vqshl", "u", int_arm_neon_vqshiftu,0>;
2476 // VQSHL : Vector Saturating Shift Left (Immediate)
2477 defm VQSHLsi : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s", NEONvqshls>;
2478 defm VQSHLui : N2VSh_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u", NEONvqshlu>;
2479 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
2480 defm VQSHLsu : N2VSh_QHSD<1,1,0b0110,1, IIC_VSHLi4D, "vqshlu","s",NEONvqshlsu>;
2482 // VQSHRN : Vector Saturating Shift Right and Narrow
2483 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
2485 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
2488 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
2489 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
2492 // VQRSHL : Vector Saturating Rounding Shift
2493 defm VQRSHLs : N3VInt_QHSD<0,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2494 IIC_VSHLi4Q, "vqrshl", "s",
2495 int_arm_neon_vqrshifts, 0>;
2496 defm VQRSHLu : N3VInt_QHSD<1,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2497 IIC_VSHLi4Q, "vqrshl", "u",
2498 int_arm_neon_vqrshiftu, 0>;
2500 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
2501 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
2503 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
2506 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
2507 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
2510 // VSRA : Vector Shift Right and Accumulate
2511 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
2512 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
2513 // VRSRA : Vector Rounding Shift Right and Accumulate
2514 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
2515 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
2517 // VSLI : Vector Shift Left and Insert
2518 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli", NEONvsli>;
2519 // VSRI : Vector Shift Right and Insert
2520 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri", NEONvsri>;
2522 // Vector Absolute and Saturating Absolute.
2524 // VABS : Vector Absolute Value
2525 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
2526 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
2528 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2529 IIC_VUNAD, "vabs", "f32",
2530 v2f32, v2f32, int_arm_neon_vabs>;
2531 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2532 IIC_VUNAQ, "vabs", "f32",
2533 v4f32, v4f32, int_arm_neon_vabs>;
2535 // VQABS : Vector Saturating Absolute Value
2536 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
2537 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
2538 int_arm_neon_vqabs>;
2542 def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
2543 def vneg_conv : PatFrag<(ops node:$in), (sub immAllZerosV_bc, node:$in)>;
2545 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
2546 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
2547 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
2548 [(set DPR:$dst, (Ty (vneg DPR:$src)))]>;
2549 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
2550 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
2551 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
2552 [(set QPR:$dst, (Ty (vneg QPR:$src)))]>;
2554 // VNEG : Vector Negate
2555 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
2556 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
2557 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
2558 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
2559 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
2560 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
2562 // VNEG : Vector Negate (floating-point)
2563 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
2564 (outs DPR:$dst), (ins DPR:$src), IIC_VUNAD,
2565 "vneg", "f32", "$dst, $src", "",
2566 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
2567 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
2568 (outs QPR:$dst), (ins QPR:$src), IIC_VUNAQ,
2569 "vneg", "f32", "$dst, $src", "",
2570 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
2572 def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>;
2573 def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>;
2574 def : Pat<(v2i32 (vneg_conv DPR:$src)), (VNEGs32d DPR:$src)>;
2575 def : Pat<(v16i8 (vneg_conv QPR:$src)), (VNEGs8q QPR:$src)>;
2576 def : Pat<(v8i16 (vneg_conv QPR:$src)), (VNEGs16q QPR:$src)>;
2577 def : Pat<(v4i32 (vneg_conv QPR:$src)), (VNEGs32q QPR:$src)>;
2579 // VQNEG : Vector Saturating Negate
2580 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
2581 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
2582 int_arm_neon_vqneg>;
2584 // Vector Bit Counting Operations.
2586 // VCLS : Vector Count Leading Sign Bits
2587 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
2588 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
2590 // VCLZ : Vector Count Leading Zeros
2591 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
2592 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
2594 // VCNT : Vector Count One Bits
2595 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
2596 IIC_VCNTiD, "vcnt", "8",
2597 v8i8, v8i8, int_arm_neon_vcnt>;
2598 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
2599 IIC_VCNTiQ, "vcnt", "8",
2600 v16i8, v16i8, int_arm_neon_vcnt>;
2602 // Vector Swap -- for disassembly only.
2603 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
2604 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
2605 "vswp", "$dst, $src", "", []>;
2606 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
2607 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
2608 "vswp", "$dst, $src", "", []>;
2610 // Vector Move Operations.
2612 // VMOV : Vector Move (Register)
2614 def VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
2615 IIC_VMOVD, "vmov", "$dst, $src", "", []>;
2616 def VMOVQ : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
2617 IIC_VMOVD, "vmov", "$dst, $src", "", []>;
2619 // VMOV : Vector Move (Immediate)
2621 // VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm.
2622 def VMOV_get_imm8 : SDNodeXForm<build_vector, [{
2623 return ARM::getVMOVImm(N, 1, *CurDAG);
2625 def vmovImm8 : PatLeaf<(build_vector), [{
2626 return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0;
2629 // VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm.
2630 def VMOV_get_imm16 : SDNodeXForm<build_vector, [{
2631 return ARM::getVMOVImm(N, 2, *CurDAG);
2633 def vmovImm16 : PatLeaf<(build_vector), [{
2634 return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0;
2635 }], VMOV_get_imm16>;
2637 // VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm.
2638 def VMOV_get_imm32 : SDNodeXForm<build_vector, [{
2639 return ARM::getVMOVImm(N, 4, *CurDAG);
2641 def vmovImm32 : PatLeaf<(build_vector), [{
2642 return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0;
2643 }], VMOV_get_imm32>;
2645 // VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm.
2646 def VMOV_get_imm64 : SDNodeXForm<build_vector, [{
2647 return ARM::getVMOVImm(N, 8, *CurDAG);
2649 def vmovImm64 : PatLeaf<(build_vector), [{
2650 return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0;
2651 }], VMOV_get_imm64>;
2653 // Note: Some of the cmode bits in the following VMOV instructions need to
2654 // be encoded based on the immed values.
2656 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
2657 (ins h8imm:$SIMM), IIC_VMOVImm,
2658 "vmov", "i8", "$dst, $SIMM", "",
2659 [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>;
2660 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
2661 (ins h8imm:$SIMM), IIC_VMOVImm,
2662 "vmov", "i8", "$dst, $SIMM", "",
2663 [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>;
2665 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,?}, 0, 0, {?}, 1, (outs DPR:$dst),
2666 (ins h16imm:$SIMM), IIC_VMOVImm,
2667 "vmov", "i16", "$dst, $SIMM", "",
2668 [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>;
2669 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,?}, 0, 1, {?}, 1, (outs QPR:$dst),
2670 (ins h16imm:$SIMM), IIC_VMOVImm,
2671 "vmov", "i16", "$dst, $SIMM", "",
2672 [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>;
2674 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, {?}, 1, (outs DPR:$dst),
2675 (ins h32imm:$SIMM), IIC_VMOVImm,
2676 "vmov", "i32", "$dst, $SIMM", "",
2677 [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>;
2678 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, {?}, 1, (outs QPR:$dst),
2679 (ins h32imm:$SIMM), IIC_VMOVImm,
2680 "vmov", "i32", "$dst, $SIMM", "",
2681 [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>;
2683 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
2684 (ins h64imm:$SIMM), IIC_VMOVImm,
2685 "vmov", "i64", "$dst, $SIMM", "",
2686 [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>;
2687 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
2688 (ins h64imm:$SIMM), IIC_VMOVImm,
2689 "vmov", "i64", "$dst, $SIMM", "",
2690 [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>;
2692 // VMOV : Vector Get Lane (move scalar to ARM core register)
2694 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
2695 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2696 IIC_VMOVSI, "vmov", "s8", "$dst, $src[$lane]",
2697 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
2699 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
2700 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2701 IIC_VMOVSI, "vmov", "s16", "$dst, $src[$lane]",
2702 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
2704 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
2705 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2706 IIC_VMOVSI, "vmov", "u8", "$dst, $src[$lane]",
2707 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
2709 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
2710 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2711 IIC_VMOVSI, "vmov", "u16", "$dst, $src[$lane]",
2712 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
2714 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
2715 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2716 IIC_VMOVSI, "vmov", "32", "$dst, $src[$lane]",
2717 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
2719 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
2720 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
2721 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
2722 (DSubReg_i8_reg imm:$lane))),
2723 (SubReg_i8_lane imm:$lane))>;
2724 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
2725 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
2726 (DSubReg_i16_reg imm:$lane))),
2727 (SubReg_i16_lane imm:$lane))>;
2728 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
2729 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
2730 (DSubReg_i8_reg imm:$lane))),
2731 (SubReg_i8_lane imm:$lane))>;
2732 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
2733 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
2734 (DSubReg_i16_reg imm:$lane))),
2735 (SubReg_i16_lane imm:$lane))>;
2736 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
2737 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
2738 (DSubReg_i32_reg imm:$lane))),
2739 (SubReg_i32_lane imm:$lane))>;
2740 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
2741 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
2742 (SSubReg_f32_reg imm:$src2))>;
2743 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
2744 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
2745 (SSubReg_f32_reg imm:$src2))>;
2746 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
2747 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
2748 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
2749 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
2752 // VMOV : Vector Set Lane (move ARM core register to scalar)
2754 let Constraints = "$src1 = $dst" in {
2755 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$dst),
2756 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2757 IIC_VMOVISL, "vmov", "8", "$dst[$lane], $src2",
2758 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
2759 GPR:$src2, imm:$lane))]>;
2760 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$dst),
2761 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2762 IIC_VMOVISL, "vmov", "16", "$dst[$lane], $src2",
2763 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
2764 GPR:$src2, imm:$lane))]>;
2765 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$dst),
2766 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2767 IIC_VMOVISL, "vmov", "32", "$dst[$lane], $src2",
2768 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
2769 GPR:$src2, imm:$lane))]>;
2771 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
2772 (v16i8 (INSERT_SUBREG QPR:$src1,
2773 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
2774 (DSubReg_i8_reg imm:$lane))),
2775 GPR:$src2, (SubReg_i8_lane imm:$lane))),
2776 (DSubReg_i8_reg imm:$lane)))>;
2777 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
2778 (v8i16 (INSERT_SUBREG QPR:$src1,
2779 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
2780 (DSubReg_i16_reg imm:$lane))),
2781 GPR:$src2, (SubReg_i16_lane imm:$lane))),
2782 (DSubReg_i16_reg imm:$lane)))>;
2783 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
2784 (v4i32 (INSERT_SUBREG QPR:$src1,
2785 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
2786 (DSubReg_i32_reg imm:$lane))),
2787 GPR:$src2, (SubReg_i32_lane imm:$lane))),
2788 (DSubReg_i32_reg imm:$lane)))>;
2790 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
2791 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
2792 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
2793 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
2794 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
2795 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
2797 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
2798 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
2799 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
2800 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
2802 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
2803 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
2804 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
2805 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, arm_dsubreg_0)>;
2806 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
2807 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
2809 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
2810 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2811 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
2812 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2813 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
2814 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2816 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
2817 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
2818 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2820 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
2821 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
2822 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2824 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
2825 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
2826 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2829 // VDUP : Vector Duplicate (from ARM core register to all elements)
2831 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
2832 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
2833 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
2834 [(set DPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
2835 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
2836 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
2837 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
2838 [(set QPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
2840 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
2841 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
2842 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
2843 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
2844 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
2845 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
2847 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
2848 IIC_VMOVIS, "vdup", "32", "$dst, $src",
2849 [(set DPR:$dst, (v2f32 (NEONvdup
2850 (f32 (bitconvert GPR:$src)))))]>;
2851 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
2852 IIC_VMOVIS, "vdup", "32", "$dst, $src",
2853 [(set QPR:$dst, (v4f32 (NEONvdup
2854 (f32 (bitconvert GPR:$src)))))]>;
2856 // VDUP : Vector Duplicate Lane (from scalar to all elements)
2858 class VDUPLND<bits<2> op19_18, bits<2> op17_16,
2859 string OpcodeStr, string Dt, ValueType Ty>
2860 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
2861 (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD,
2862 OpcodeStr, Dt, "$dst, $src[$lane]", "",
2863 [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
2865 class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, string Dt,
2866 ValueType ResTy, ValueType OpTy>
2867 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
2868 (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD,
2869 OpcodeStr, Dt, "$dst, $src[$lane]", "",
2870 [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src), imm:$lane)))]>;
2872 // Inst{19-16} is partially specified depending on the element size.
2874 def VDUPLN8d : VDUPLND<{?,?}, {?,1}, "vdup", "8", v8i8>;
2875 def VDUPLN16d : VDUPLND<{?,?}, {1,0}, "vdup", "16", v4i16>;
2876 def VDUPLN32d : VDUPLND<{?,1}, {0,0}, "vdup", "32", v2i32>;
2877 def VDUPLNfd : VDUPLND<{?,1}, {0,0}, "vdup", "32", v2f32>;
2878 def VDUPLN8q : VDUPLNQ<{?,?}, {?,1}, "vdup", "8", v16i8, v8i8>;
2879 def VDUPLN16q : VDUPLNQ<{?,?}, {1,0}, "vdup", "16", v8i16, v4i16>;
2880 def VDUPLN32q : VDUPLNQ<{?,1}, {0,0}, "vdup", "32", v4i32, v2i32>;
2881 def VDUPLNfq : VDUPLNQ<{?,1}, {0,0}, "vdup", "32", v4f32, v2f32>;
2883 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
2884 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
2885 (DSubReg_i8_reg imm:$lane))),
2886 (SubReg_i8_lane imm:$lane)))>;
2887 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
2888 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
2889 (DSubReg_i16_reg imm:$lane))),
2890 (SubReg_i16_lane imm:$lane)))>;
2891 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
2892 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
2893 (DSubReg_i32_reg imm:$lane))),
2894 (SubReg_i32_lane imm:$lane)))>;
2895 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
2896 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src,
2897 (DSubReg_i32_reg imm:$lane))),
2898 (SubReg_i32_lane imm:$lane)))>;
2900 def VDUPfdf : N2V<0b11, 0b11, {?,1}, {0,0}, 0b11000, 0, 0,
2901 (outs DPR:$dst), (ins SPR:$src),
2902 IIC_VMOVD, "vdup", "32", "$dst, ${src:lane}", "",
2903 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
2905 def VDUPfqf : N2V<0b11, 0b11, {?,1}, {0,0}, 0b11000, 1, 0,
2906 (outs QPR:$dst), (ins SPR:$src),
2907 IIC_VMOVD, "vdup", "32", "$dst, ${src:lane}", "",
2908 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
2910 def : Pat<(v2i64 (NEONvduplane (v2i64 QPR:$src), imm:$lane)),
2911 (INSERT_SUBREG QPR:$src,
2912 (i64 (EXTRACT_SUBREG QPR:$src,
2913 (DSubReg_f64_reg imm:$lane))),
2914 (DSubReg_f64_other_reg imm:$lane))>;
2915 def : Pat<(v2f64 (NEONvduplane (v2f64 QPR:$src), imm:$lane)),
2916 (INSERT_SUBREG QPR:$src,
2917 (f64 (EXTRACT_SUBREG QPR:$src,
2918 (DSubReg_f64_reg imm:$lane))),
2919 (DSubReg_f64_other_reg imm:$lane))>;
2921 // VMOVN : Vector Narrowing Move
2922 defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVD,
2923 "vmovn", "i", int_arm_neon_vmovn>;
2924 // VQMOVN : Vector Saturating Narrowing Move
2925 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
2926 "vqmovn", "s", int_arm_neon_vqmovns>;
2927 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
2928 "vqmovn", "u", int_arm_neon_vqmovnu>;
2929 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
2930 "vqmovun", "s", int_arm_neon_vqmovnsu>;
2931 // VMOVL : Vector Lengthening Move
2932 defm VMOVLs : N2VLInt_QHS<0b01,0b10100,0,1, "vmovl", "s",
2933 int_arm_neon_vmovls>;
2934 defm VMOVLu : N2VLInt_QHS<0b11,0b10100,0,1, "vmovl", "u",
2935 int_arm_neon_vmovlu>;
2937 // Vector Conversions.
2939 // VCVT : Vector Convert Between Floating-Point and Integers
2940 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
2941 v2i32, v2f32, fp_to_sint>;
2942 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
2943 v2i32, v2f32, fp_to_uint>;
2944 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
2945 v2f32, v2i32, sint_to_fp>;
2946 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
2947 v2f32, v2i32, uint_to_fp>;
2949 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
2950 v4i32, v4f32, fp_to_sint>;
2951 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
2952 v4i32, v4f32, fp_to_uint>;
2953 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
2954 v4f32, v4i32, sint_to_fp>;
2955 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
2956 v4f32, v4i32, uint_to_fp>;
2958 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
2959 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
2960 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
2961 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
2962 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
2963 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
2964 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
2965 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
2966 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
2968 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
2969 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
2970 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
2971 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
2972 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
2973 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
2974 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
2975 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
2979 // VREV64 : Vector Reverse elements within 64-bit doublewords
2981 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
2982 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
2983 (ins DPR:$src), IIC_VMOVD,
2984 OpcodeStr, Dt, "$dst, $src", "",
2985 [(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>;
2986 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
2987 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
2988 (ins QPR:$src), IIC_VMOVD,
2989 OpcodeStr, Dt, "$dst, $src", "",
2990 [(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>;
2992 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
2993 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
2994 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
2995 def VREV64df : VREV64D<0b10, "vrev64", "32", v2f32>;
2997 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
2998 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
2999 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
3000 def VREV64qf : VREV64Q<0b10, "vrev64", "32", v4f32>;
3002 // VREV32 : Vector Reverse elements within 32-bit words
3004 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3005 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
3006 (ins DPR:$src), IIC_VMOVD,
3007 OpcodeStr, Dt, "$dst, $src", "",
3008 [(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>;
3009 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3010 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
3011 (ins QPR:$src), IIC_VMOVD,
3012 OpcodeStr, Dt, "$dst, $src", "",
3013 [(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>;
3015 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
3016 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
3018 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
3019 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
3021 // VREV16 : Vector Reverse elements within 16-bit halfwords
3023 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3024 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
3025 (ins DPR:$src), IIC_VMOVD,
3026 OpcodeStr, Dt, "$dst, $src", "",
3027 [(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>;
3028 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3029 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
3030 (ins QPR:$src), IIC_VMOVD,
3031 OpcodeStr, Dt, "$dst, $src", "",
3032 [(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>;
3034 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
3035 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
3037 // Other Vector Shuffles.
3039 // VEXT : Vector Extract
3041 class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
3042 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$dst),
3043 (ins DPR:$lhs, DPR:$rhs, i32imm:$index), IIC_VEXTD,
3044 OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
3045 [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
3046 (Ty DPR:$rhs), imm:$index)))]>;
3048 class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
3049 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$dst),
3050 (ins QPR:$lhs, QPR:$rhs, i32imm:$index), IIC_VEXTQ,
3051 OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
3052 [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
3053 (Ty QPR:$rhs), imm:$index)))]>;
3055 def VEXTd8 : VEXTd<"vext", "8", v8i8>;
3056 def VEXTd16 : VEXTd<"vext", "16", v4i16>;
3057 def VEXTd32 : VEXTd<"vext", "32", v2i32>;
3058 def VEXTdf : VEXTd<"vext", "32", v2f32>;
3060 def VEXTq8 : VEXTq<"vext", "8", v16i8>;
3061 def VEXTq16 : VEXTq<"vext", "16", v8i16>;
3062 def VEXTq32 : VEXTq<"vext", "32", v4i32>;
3063 def VEXTqf : VEXTq<"vext", "32", v4f32>;
3065 // VTRN : Vector Transpose
3067 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
3068 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
3069 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
3071 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
3072 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
3073 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
3075 // VUZP : Vector Unzip (Deinterleave)
3077 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
3078 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
3079 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
3081 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
3082 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
3083 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
3085 // VZIP : Vector Zip (Interleave)
3087 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
3088 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
3089 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
3091 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
3092 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
3093 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
3095 // Vector Table Lookup and Table Extension.
3097 // VTBL : Vector Table Lookup
3099 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$dst),
3100 (ins DPR:$tbl1, DPR:$src), IIC_VTB1,
3101 "vtbl", "8", "$dst, \\{$tbl1\\}, $src", "",
3102 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>;
3103 let hasExtraSrcRegAllocReq = 1 in {
3105 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst),
3106 (ins DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTB2,
3107 "vtbl", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "",
3108 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl2
3109 DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
3111 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst),
3112 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), IIC_VTB3,
3113 "vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src", "",
3114 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl3
3115 DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
3117 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst),
3118 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), IIC_VTB4,
3119 "vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src", "",
3120 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl4 DPR:$tbl1, DPR:$tbl2,
3121 DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
3122 } // hasExtraSrcRegAllocReq = 1
3124 // VTBX : Vector Table Extension
3126 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst),
3127 (ins DPR:$orig, DPR:$tbl1, DPR:$src), IIC_VTBX1,
3128 "vtbx", "8", "$dst, \\{$tbl1\\}, $src", "$orig = $dst",
3129 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1
3130 DPR:$orig, DPR:$tbl1, DPR:$src)))]>;
3131 let hasExtraSrcRegAllocReq = 1 in {
3133 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst),
3134 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTBX2,
3135 "vtbx", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "$orig = $dst",
3136 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx2
3137 DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
3139 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst),
3140 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), IIC_VTBX3,
3141 "vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src", "$orig = $dst",
3142 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx3 DPR:$orig, DPR:$tbl1,
3143 DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
3145 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1,
3146 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), IIC_VTBX4,
3147 "vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src",
3149 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx4 DPR:$orig, DPR:$tbl1,
3150 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
3151 } // hasExtraSrcRegAllocReq = 1
3153 //===----------------------------------------------------------------------===//
3154 // NEON instructions for single-precision FP math
3155 //===----------------------------------------------------------------------===//
3157 class N2VSPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
3158 : NEONFPPat<(ResTy (OpNode SPR:$a)),
3159 (EXTRACT_SUBREG (OpTy (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)),
3160 SPR:$a, arm_ssubreg_0))),
3163 class N3VSPat<SDNode OpNode, NeonI Inst>
3164 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
3165 (EXTRACT_SUBREG (v2f32
3166 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3167 SPR:$a, arm_ssubreg_0),
3168 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3169 SPR:$b, arm_ssubreg_0))),
3172 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
3173 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
3174 (EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3175 SPR:$acc, arm_ssubreg_0),
3176 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3177 SPR:$a, arm_ssubreg_0),
3178 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3179 SPR:$b, arm_ssubreg_0)),
3182 // These need separate instructions because they must use DPR_VFP2 register
3183 // class which have SPR sub-registers.
3185 // Vector Add Operations used for single-precision FP
3186 let neverHasSideEffects = 1 in
3187 def VADDfd_sfp : N3VS<0,0,0b00,0b1101,0, "vadd", "f32", v2f32, v2f32, fadd, 1>;
3188 def : N3VSPat<fadd, VADDfd_sfp>;
3190 // Vector Sub Operations used for single-precision FP
3191 let neverHasSideEffects = 1 in
3192 def VSUBfd_sfp : N3VS<0,0,0b10,0b1101,0, "vsub", "f32", v2f32, v2f32, fsub, 0>;
3193 def : N3VSPat<fsub, VSUBfd_sfp>;
3195 // Vector Multiply Operations used for single-precision FP
3196 let neverHasSideEffects = 1 in
3197 def VMULfd_sfp : N3VS<1,0,0b00,0b1101,1, "vmul", "f32", v2f32, v2f32, fmul, 1>;
3198 def : N3VSPat<fmul, VMULfd_sfp>;
3200 // Vector Multiply-Accumulate/Subtract used for single-precision FP
3201 // vml[as].f32 can cause 4-8 cycle stalls in following ASIMD instructions, so
3202 // we want to avoid them for now. e.g., alternating vmla/vadd instructions.
3204 //let neverHasSideEffects = 1 in
3205 //def VMLAfd_sfp : N3VSMulOp<0,0,0b00,0b1101,1, IIC_VMACD, "vmla", "f32",
3206 // v2f32, fmul, fadd>;
3207 //def : N3VSMulOpPat<fmul, fadd, VMLAfd_sfp>;
3209 //let neverHasSideEffects = 1 in
3210 //def VMLSfd_sfp : N3VSMulOp<0,0,0b10,0b1101,1, IIC_VMACD, "vmls", "f32",
3211 // v2f32, fmul, fsub>;
3212 //def : N3VSMulOpPat<fmul, fsub, VMLSfd_sfp>;
3214 // Vector Absolute used for single-precision FP
3215 let neverHasSideEffects = 1 in
3216 def VABSfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01110, 0, 0,
3217 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
3218 "vabs", "f32", "$dst, $src", "", []>;
3219 def : N2VSPat<fabs, f32, v2f32, VABSfd_sfp>;
3221 // Vector Negate used for single-precision FP
3222 let neverHasSideEffects = 1 in
3223 def VNEGfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
3224 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
3225 "vneg", "f32", "$dst, $src", "", []>;
3226 def : N2VSPat<fneg, f32, v2f32, VNEGfd_sfp>;
3228 // Vector Maximum used for single-precision FP
3229 let neverHasSideEffects = 1 in
3230 def VMAXfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$dst),
3231 (ins DPR_VFP2:$src1, DPR_VFP2:$src2), IIC_VBIND,
3232 "vmax", "f32", "$dst, $src1, $src2", "", []>;
3233 def : N3VSPat<NEONfmax, VMAXfd_sfp>;
3235 // Vector Minimum used for single-precision FP
3236 let neverHasSideEffects = 1 in
3237 def VMINfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$dst),
3238 (ins DPR_VFP2:$src1, DPR_VFP2:$src2), IIC_VBIND,
3239 "vmin", "f32", "$dst, $src1, $src2", "", []>;
3240 def : N3VSPat<NEONfmin, VMINfd_sfp>;
3242 // Vector Convert between single-precision FP and integer
3243 let neverHasSideEffects = 1 in
3244 def VCVTf2sd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3245 v2i32, v2f32, fp_to_sint>;
3246 def : N2VSPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
3248 let neverHasSideEffects = 1 in
3249 def VCVTf2ud_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3250 v2i32, v2f32, fp_to_uint>;
3251 def : N2VSPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
3253 let neverHasSideEffects = 1 in
3254 def VCVTs2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3255 v2f32, v2i32, sint_to_fp>;
3256 def : N2VSPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
3258 let neverHasSideEffects = 1 in
3259 def VCVTu2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3260 v2f32, v2i32, uint_to_fp>;
3261 def : N2VSPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
3263 //===----------------------------------------------------------------------===//
3264 // Non-Instruction Patterns
3265 //===----------------------------------------------------------------------===//
3268 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
3269 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
3270 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
3271 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
3272 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
3273 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
3274 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
3275 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
3276 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
3277 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
3278 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
3279 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
3280 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
3281 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
3282 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
3283 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
3284 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
3285 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
3286 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
3287 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
3288 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
3289 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
3290 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
3291 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
3292 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
3293 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
3294 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
3295 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
3296 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
3297 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
3299 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
3300 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
3301 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
3302 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
3303 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
3304 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
3305 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
3306 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
3307 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
3308 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
3309 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
3310 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
3311 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
3312 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
3313 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
3314 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
3315 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
3316 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
3317 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
3318 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
3319 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
3320 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
3321 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
3322 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
3323 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
3324 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
3325 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
3326 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
3327 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
3328 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;