1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
25 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
29 def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
33 def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
36 def SDT_ARMBrJT : SDTypeProfile<0, 3,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
40 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
42 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
44 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
46 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
47 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
48 SDTCisVT<5, OtherVT>]>;
50 def SDT_ARMAnd : SDTypeProfile<1, 2,
51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
54 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
56 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
57 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
59 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
60 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
62 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
64 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
66 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
69 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
71 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def SDT_ARMVMAXNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>;
75 def SDT_ARMVMINNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>;
77 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
80 SDTCisInt<0>, SDTCisVT<1, i32>]>;
82 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
83 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
90 def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>,
91 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
92 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >;
93 def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>;
94 def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>;
97 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
98 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
99 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
100 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
102 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
103 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
104 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
105 [SDNPHasChain, SDNPSideEffect,
106 SDNPOptInGlue, SDNPOutGlue]>;
107 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
109 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
110 SDNPMayStore, SDNPMayLoad]>;
112 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
113 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
115 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
116 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
118 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
119 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
122 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
123 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
125 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
128 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
129 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
131 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
133 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
136 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
139 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
142 def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
145 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
146 [SDNPOutGlue, SDNPCommutative]>;
148 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
150 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
151 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
152 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
154 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
156 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
157 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
158 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
160 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
161 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
162 SDT_ARMEH_SJLJ_Setjmp,
163 [SDNPHasChain, SDNPSideEffect]>;
164 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
165 SDT_ARMEH_SJLJ_Longjmp,
166 [SDNPHasChain, SDNPSideEffect]>;
168 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
169 [SDNPHasChain, SDNPSideEffect]>;
170 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
171 [SDNPHasChain, SDNPSideEffect]>;
172 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
173 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
175 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
177 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
178 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
180 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
182 def ARMvmaxnm : SDNode<"ARMISD::VMAXNM", SDT_ARMVMAXNM, []>;
183 def ARMvminnm : SDNode<"ARMISD::VMINNM", SDT_ARMVMINNM, []>;
185 //===----------------------------------------------------------------------===//
186 // ARM Instruction Predicate Definitions.
188 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
189 AssemblerPredicate<"HasV4TOps", "armv4t">;
190 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
191 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
192 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
193 AssemblerPredicate<"HasV5TEOps", "armv5te">;
194 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
195 AssemblerPredicate<"HasV6Ops", "armv6">;
196 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
197 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
198 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
199 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
200 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
201 AssemblerPredicate<"HasV7Ops", "armv7">;
202 def HasV8 : Predicate<"Subtarget->hasV8Ops()">,
203 AssemblerPredicate<"HasV8Ops", "armv8">;
204 def PreV8 : Predicate<"!Subtarget->hasV8Ops()">,
205 AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">;
206 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
207 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
208 AssemblerPredicate<"FeatureVFP2", "VFP2">;
209 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
210 AssemblerPredicate<"FeatureVFP3", "VFP3">;
211 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
212 AssemblerPredicate<"FeatureVFP4", "VFP4">;
213 def HasV8FP : Predicate<"Subtarget->hasV8FP()">,
214 AssemblerPredicate<"FeatureV8FP", "V8FP">;
215 def HasNEON : Predicate<"Subtarget->hasNEON()">,
216 AssemblerPredicate<"FeatureNEON", "NEON">;
217 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
218 AssemblerPredicate<"FeatureFP16","half-float">;
219 def HasDivide : Predicate<"Subtarget->hasDivide()">,
220 AssemblerPredicate<"FeatureHWDiv", "divide">;
221 def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
222 AssemblerPredicate<"FeatureHWDivARM">;
223 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
224 AssemblerPredicate<"FeatureT2XtPk",
226 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
227 AssemblerPredicate<"FeatureDSPThumb2",
229 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
230 AssemblerPredicate<"FeatureDB",
232 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
233 AssemblerPredicate<"FeatureMP",
235 def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">,
236 AssemblerPredicate<"FeatureTrustZone",
238 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
239 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
240 def IsThumb : Predicate<"Subtarget->isThumb()">,
241 AssemblerPredicate<"ModeThumb", "thumb">;
242 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
243 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
244 AssemblerPredicate<"ModeThumb,FeatureThumb2",
246 def IsMClass : Predicate<"Subtarget->isMClass()">,
247 AssemblerPredicate<"FeatureMClass", "armv7m">;
248 def IsARClass : Predicate<"!Subtarget->isMClass()">,
249 AssemblerPredicate<"!FeatureMClass",
251 def IsARM : Predicate<"!Subtarget->isThumb()">,
252 AssemblerPredicate<"!ModeThumb", "arm-mode">;
253 def IsIOS : Predicate<"Subtarget->isTargetIOS()">;
254 def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">;
255 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
256 def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">,
257 AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
258 def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">;
260 // FIXME: Eventually this will be just "hasV6T2Ops".
261 def UseMovt : Predicate<"Subtarget->useMovt()">;
262 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
263 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
264 def UseMulOps : Predicate<"Subtarget->useMulOps()">;
266 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
267 // But only select them if more precision in FP computation is allowed.
268 // Do not use them for Darwin platforms.
269 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
270 " FPOpFusion::Fast) && "
271 "!Subtarget->isTargetDarwin()">;
272 def DontUseFusedMAC : Predicate<"!(TM.Options.AllowFPOpFusion =="
273 " FPOpFusion::Fast &&"
274 " Subtarget->hasVFP4()) || "
275 "Subtarget->isTargetDarwin()">;
277 // VGETLNi32 is microcoded on Swift - prefer VMOV.
278 def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">;
279 def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">;
281 // VDUP.32 is microcoded on Swift - prefer VMOV.
282 def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">;
283 def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">;
285 // Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as
286 // this allows more effective execution domain optimization. See
287 // setExecutionDomain().
288 def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">;
289 def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">;
291 def IsLE : Predicate<"getTargetLowering()->isLittleEndian()">;
292 def IsBE : Predicate<"getTargetLowering()->isBigEndian()">;
294 //===----------------------------------------------------------------------===//
295 // ARM Flag Definitions.
297 class RegConstraint<string C> {
298 string Constraints = C;
301 //===----------------------------------------------------------------------===//
302 // ARM specific transformation functions and pattern fragments.
305 // imm_neg_XFORM - Return the negation of an i32 immediate value.
306 def imm_neg_XFORM : SDNodeXForm<imm, [{
307 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
310 // imm_not_XFORM - Return the complement of a i32 immediate value.
311 def imm_not_XFORM : SDNodeXForm<imm, [{
312 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
315 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
316 def imm16_31 : ImmLeaf<i32, [{
317 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
320 def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; }
321 def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
322 unsigned Value = -(unsigned)N->getZExtValue();
323 return Value && ARM_AM::getSOImmVal(Value) != -1;
325 let ParserMatchClass = so_imm_neg_asmoperand;
328 // Note: this pattern doesn't require an encoder method and such, as it's
329 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
330 // is handled by the destination instructions, which use so_imm.
331 def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
332 def so_imm_not : Operand<i32>, PatLeaf<(imm), [{
333 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
335 let ParserMatchClass = so_imm_not_asmoperand;
338 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
339 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
340 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
343 /// Split a 32-bit immediate into two 16 bit parts.
344 def hi16 : SDNodeXForm<imm, [{
345 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
348 def lo16AllZero : PatLeaf<(i32 imm), [{
349 // Returns true if all low 16-bits are 0.
350 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
353 class BinOpWithFlagFrag<dag res> :
354 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
355 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
356 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
358 // An 'and' node with a single use.
359 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
360 return N->hasOneUse();
363 // An 'xor' node with a single use.
364 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
365 return N->hasOneUse();
368 // An 'fmul' node with a single use.
369 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
370 return N->hasOneUse();
373 // An 'fadd' node which checks for single non-hazardous use.
374 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
375 return hasNoVMLxHazardUse(N);
378 // An 'fsub' node which checks for single non-hazardous use.
379 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
380 return hasNoVMLxHazardUse(N);
383 //===----------------------------------------------------------------------===//
384 // Operand Definitions.
387 // Immediate operands with a shared generic asm render method.
388 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
391 // FIXME: rename brtarget to t2_brtarget
392 def brtarget : Operand<OtherVT> {
393 let EncoderMethod = "getBranchTargetOpValue";
394 let OperandType = "OPERAND_PCREL";
395 let DecoderMethod = "DecodeT2BROperand";
398 // FIXME: get rid of this one?
399 def uncondbrtarget : Operand<OtherVT> {
400 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
401 let OperandType = "OPERAND_PCREL";
404 // Branch target for ARM. Handles conditional/unconditional
405 def br_target : Operand<OtherVT> {
406 let EncoderMethod = "getARMBranchTargetOpValue";
407 let OperandType = "OPERAND_PCREL";
411 // FIXME: rename bltarget to t2_bl_target?
412 def bltarget : Operand<i32> {
413 // Encoded the same as branch targets.
414 let EncoderMethod = "getBranchTargetOpValue";
415 let OperandType = "OPERAND_PCREL";
418 // Call target for ARM. Handles conditional/unconditional
419 // FIXME: rename bl_target to t2_bltarget?
420 def bl_target : Operand<i32> {
421 let EncoderMethod = "getARMBLTargetOpValue";
422 let OperandType = "OPERAND_PCREL";
425 def blx_target : Operand<i32> {
426 let EncoderMethod = "getARMBLXTargetOpValue";
427 let OperandType = "OPERAND_PCREL";
430 // A list of registers separated by comma. Used by load/store multiple.
431 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
432 def reglist : Operand<i32> {
433 let EncoderMethod = "getRegisterListOpValue";
434 let ParserMatchClass = RegListAsmOperand;
435 let PrintMethod = "printRegisterList";
436 let DecoderMethod = "DecodeRegListOperand";
439 def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">;
441 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
442 def dpr_reglist : Operand<i32> {
443 let EncoderMethod = "getRegisterListOpValue";
444 let ParserMatchClass = DPRRegListAsmOperand;
445 let PrintMethod = "printRegisterList";
446 let DecoderMethod = "DecodeDPRRegListOperand";
449 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
450 def spr_reglist : Operand<i32> {
451 let EncoderMethod = "getRegisterListOpValue";
452 let ParserMatchClass = SPRRegListAsmOperand;
453 let PrintMethod = "printRegisterList";
454 let DecoderMethod = "DecodeSPRRegListOperand";
457 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
458 def cpinst_operand : Operand<i32> {
459 let PrintMethod = "printCPInstOperand";
463 def pclabel : Operand<i32> {
464 let PrintMethod = "printPCLabel";
467 // ADR instruction labels.
468 def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
469 def adrlabel : Operand<i32> {
470 let EncoderMethod = "getAdrLabelOpValue";
471 let ParserMatchClass = AdrLabelAsmOperand;
472 let PrintMethod = "printAdrLabelOperand<0>";
475 def neon_vcvt_imm32 : Operand<i32> {
476 let EncoderMethod = "getNEONVcvtImm32OpValue";
477 let DecoderMethod = "DecodeVCVTImmOperand";
480 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
481 def rot_imm_XFORM: SDNodeXForm<imm, [{
482 switch (N->getZExtValue()){
484 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
485 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
486 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
487 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
490 def RotImmAsmOperand : AsmOperandClass {
492 let ParserMethod = "parseRotImm";
494 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
495 int32_t v = N->getZExtValue();
496 return v == 8 || v == 16 || v == 24; }],
498 let PrintMethod = "printRotImmOperand";
499 let ParserMatchClass = RotImmAsmOperand;
502 // shift_imm: An integer that encodes a shift amount and the type of shift
503 // (asr or lsl). The 6-bit immediate encodes as:
506 // {4-0} imm5 shift amount.
507 // asr #32 encoded as imm5 == 0.
508 def ShifterImmAsmOperand : AsmOperandClass {
509 let Name = "ShifterImm";
510 let ParserMethod = "parseShifterImm";
512 def shift_imm : Operand<i32> {
513 let PrintMethod = "printShiftImmOperand";
514 let ParserMatchClass = ShifterImmAsmOperand;
517 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
518 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
519 def so_reg_reg : Operand<i32>, // reg reg imm
520 ComplexPattern<i32, 3, "SelectRegShifterOperand",
521 [shl, srl, sra, rotr]> {
522 let EncoderMethod = "getSORegRegOpValue";
523 let PrintMethod = "printSORegRegOperand";
524 let DecoderMethod = "DecodeSORegRegOperand";
525 let ParserMatchClass = ShiftedRegAsmOperand;
526 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
529 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
530 def so_reg_imm : Operand<i32>, // reg imm
531 ComplexPattern<i32, 2, "SelectImmShifterOperand",
532 [shl, srl, sra, rotr]> {
533 let EncoderMethod = "getSORegImmOpValue";
534 let PrintMethod = "printSORegImmOperand";
535 let DecoderMethod = "DecodeSORegImmOperand";
536 let ParserMatchClass = ShiftedImmAsmOperand;
537 let MIOperandInfo = (ops GPR, i32imm);
540 // FIXME: Does this need to be distinct from so_reg?
541 def shift_so_reg_reg : Operand<i32>, // reg reg imm
542 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
543 [shl,srl,sra,rotr]> {
544 let EncoderMethod = "getSORegRegOpValue";
545 let PrintMethod = "printSORegRegOperand";
546 let DecoderMethod = "DecodeSORegRegOperand";
547 let ParserMatchClass = ShiftedRegAsmOperand;
548 let MIOperandInfo = (ops GPR, GPR, i32imm);
551 // FIXME: Does this need to be distinct from so_reg?
552 def shift_so_reg_imm : Operand<i32>, // reg reg imm
553 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
554 [shl,srl,sra,rotr]> {
555 let EncoderMethod = "getSORegImmOpValue";
556 let PrintMethod = "printSORegImmOperand";
557 let DecoderMethod = "DecodeSORegImmOperand";
558 let ParserMatchClass = ShiftedImmAsmOperand;
559 let MIOperandInfo = (ops GPR, i32imm);
563 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
564 // 8-bit immediate rotated by an arbitrary number of bits.
565 def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; }
566 def so_imm : Operand<i32>, ImmLeaf<i32, [{
567 return ARM_AM::getSOImmVal(Imm) != -1;
569 let EncoderMethod = "getSOImmOpValue";
570 let ParserMatchClass = SOImmAsmOperand;
571 let DecoderMethod = "DecodeSOImmOperand";
574 // Break so_imm's up into two pieces. This handles immediates with up to 16
575 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
576 // get the first/second pieces.
577 def so_imm2part : PatLeaf<(imm), [{
578 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
581 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
583 def arm_i32imm : PatLeaf<(imm), [{
584 if (Subtarget->hasV6T2Ops())
586 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
589 /// imm0_1 predicate - Immediate in the range [0,1].
590 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
591 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
593 /// imm0_3 predicate - Immediate in the range [0,3].
594 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
595 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
597 /// imm0_4 predicate - Immediate in the range [0,4].
598 def Imm0_4AsmOperand : ImmAsmOperand
601 let DiagnosticType = "ImmRange0_4";
603 def imm0_4 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 5; }]> {
604 let ParserMatchClass = Imm0_4AsmOperand;
605 let DecoderMethod = "DecodeImm0_4";
608 /// imm0_7 predicate - Immediate in the range [0,7].
609 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
610 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
611 return Imm >= 0 && Imm < 8;
613 let ParserMatchClass = Imm0_7AsmOperand;
616 /// imm8 predicate - Immediate is exactly 8.
617 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
618 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
619 let ParserMatchClass = Imm8AsmOperand;
622 /// imm16 predicate - Immediate is exactly 16.
623 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
624 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
625 let ParserMatchClass = Imm16AsmOperand;
628 /// imm32 predicate - Immediate is exactly 32.
629 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
630 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
631 let ParserMatchClass = Imm32AsmOperand;
634 /// imm1_7 predicate - Immediate in the range [1,7].
635 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
636 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
637 let ParserMatchClass = Imm1_7AsmOperand;
640 /// imm1_15 predicate - Immediate in the range [1,15].
641 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
642 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
643 let ParserMatchClass = Imm1_15AsmOperand;
646 /// imm1_31 predicate - Immediate in the range [1,31].
647 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
648 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
649 let ParserMatchClass = Imm1_31AsmOperand;
652 /// imm0_15 predicate - Immediate in the range [0,15].
653 def Imm0_15AsmOperand: ImmAsmOperand {
654 let Name = "Imm0_15";
655 let DiagnosticType = "ImmRange0_15";
657 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
658 return Imm >= 0 && Imm < 16;
660 let ParserMatchClass = Imm0_15AsmOperand;
663 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
664 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
665 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
666 return Imm >= 0 && Imm < 32;
668 let ParserMatchClass = Imm0_31AsmOperand;
671 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
672 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
673 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
674 return Imm >= 0 && Imm < 32;
676 let ParserMatchClass = Imm0_32AsmOperand;
679 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
680 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
681 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
682 return Imm >= 0 && Imm < 64;
684 let ParserMatchClass = Imm0_63AsmOperand;
687 /// imm0_255 predicate - Immediate in the range [0,255].
688 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
689 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
690 let ParserMatchClass = Imm0_255AsmOperand;
693 /// imm0_65535 - An immediate is in the range [0.65535].
694 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
695 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
696 return Imm >= 0 && Imm < 65536;
698 let ParserMatchClass = Imm0_65535AsmOperand;
701 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
702 def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
703 return -Imm >= 0 && -Imm < 65536;
706 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
707 // a relocatable expression.
709 // FIXME: This really needs a Thumb version separate from the ARM version.
710 // While the range is the same, and can thus use the same match class,
711 // the encoding is different so it should have a different encoder method.
712 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
713 def imm0_65535_expr : Operand<i32> {
714 let EncoderMethod = "getHiLo16ImmOpValue";
715 let ParserMatchClass = Imm0_65535ExprAsmOperand;
718 def Imm256_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm256_65535Expr"; }
719 def imm256_65535_expr : Operand<i32> {
720 let ParserMatchClass = Imm256_65535ExprAsmOperand;
723 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
724 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
725 def imm24b : Operand<i32>, ImmLeaf<i32, [{
726 return Imm >= 0 && Imm <= 0xffffff;
728 let ParserMatchClass = Imm24bitAsmOperand;
732 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
734 def BitfieldAsmOperand : AsmOperandClass {
735 let Name = "Bitfield";
736 let ParserMethod = "parseBitfield";
739 def bf_inv_mask_imm : Operand<i32>,
741 return ARM::isBitFieldInvertedMask(N->getZExtValue());
743 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
744 let PrintMethod = "printBitfieldInvMaskImmOperand";
745 let DecoderMethod = "DecodeBitfieldMaskOperand";
746 let ParserMatchClass = BitfieldAsmOperand;
749 def imm1_32_XFORM: SDNodeXForm<imm, [{
750 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
752 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
753 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
754 uint64_t Imm = N->getZExtValue();
755 return Imm > 0 && Imm <= 32;
758 let PrintMethod = "printImmPlusOneOperand";
759 let ParserMatchClass = Imm1_32AsmOperand;
762 def imm1_16_XFORM: SDNodeXForm<imm, [{
763 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
765 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
766 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
768 let PrintMethod = "printImmPlusOneOperand";
769 let ParserMatchClass = Imm1_16AsmOperand;
772 // Define ARM specific addressing modes.
773 // addrmode_imm12 := reg +/- imm12
775 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
776 class AddrMode_Imm12 : Operand<i32>,
777 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
778 // 12-bit immediate operand. Note that instructions using this encode
779 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
780 // immediate values are as normal.
782 let EncoderMethod = "getAddrModeImm12OpValue";
783 let DecoderMethod = "DecodeAddrModeImm12Operand";
784 let ParserMatchClass = MemImm12OffsetAsmOperand;
785 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
788 def addrmode_imm12 : AddrMode_Imm12 {
789 let PrintMethod = "printAddrModeImm12Operand<false>";
792 def addrmode_imm12_pre : AddrMode_Imm12 {
793 let PrintMethod = "printAddrModeImm12Operand<true>";
796 // ldst_so_reg := reg +/- reg shop imm
798 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
799 def ldst_so_reg : Operand<i32>,
800 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
801 let EncoderMethod = "getLdStSORegOpValue";
802 // FIXME: Simplify the printer
803 let PrintMethod = "printAddrMode2Operand";
804 let DecoderMethod = "DecodeSORegMemOperand";
805 let ParserMatchClass = MemRegOffsetAsmOperand;
806 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
809 // postidx_imm8 := +/- [0,255]
812 // {8} 1 is imm8 is non-negative. 0 otherwise.
813 // {7-0} [0,255] imm8 value.
814 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
815 def postidx_imm8 : Operand<i32> {
816 let PrintMethod = "printPostIdxImm8Operand";
817 let ParserMatchClass = PostIdxImm8AsmOperand;
818 let MIOperandInfo = (ops i32imm);
821 // postidx_imm8s4 := +/- [0,1020]
824 // {8} 1 is imm8 is non-negative. 0 otherwise.
825 // {7-0} [0,255] imm8 value, scaled by 4.
826 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
827 def postidx_imm8s4 : Operand<i32> {
828 let PrintMethod = "printPostIdxImm8s4Operand";
829 let ParserMatchClass = PostIdxImm8s4AsmOperand;
830 let MIOperandInfo = (ops i32imm);
834 // postidx_reg := +/- reg
836 def PostIdxRegAsmOperand : AsmOperandClass {
837 let Name = "PostIdxReg";
838 let ParserMethod = "parsePostIdxReg";
840 def postidx_reg : Operand<i32> {
841 let EncoderMethod = "getPostIdxRegOpValue";
842 let DecoderMethod = "DecodePostIdxReg";
843 let PrintMethod = "printPostIdxRegOperand";
844 let ParserMatchClass = PostIdxRegAsmOperand;
845 let MIOperandInfo = (ops GPRnopc, i32imm);
849 // addrmode2 := reg +/- imm12
850 // := reg +/- reg shop imm
852 // FIXME: addrmode2 should be refactored the rest of the way to always
853 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
854 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
855 def addrmode2 : Operand<i32>,
856 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
857 let EncoderMethod = "getAddrMode2OpValue";
858 let PrintMethod = "printAddrMode2Operand";
859 let ParserMatchClass = AddrMode2AsmOperand;
860 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
863 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
864 let Name = "PostIdxRegShifted";
865 let ParserMethod = "parsePostIdxReg";
867 def am2offset_reg : Operand<i32>,
868 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
869 [], [SDNPWantRoot]> {
870 let EncoderMethod = "getAddrMode2OffsetOpValue";
871 let PrintMethod = "printAddrMode2OffsetOperand";
872 // When using this for assembly, it's always as a post-index offset.
873 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
874 let MIOperandInfo = (ops GPRnopc, i32imm);
877 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
878 // the GPR is purely vestigal at this point.
879 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
880 def am2offset_imm : Operand<i32>,
881 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
882 [], [SDNPWantRoot]> {
883 let EncoderMethod = "getAddrMode2OffsetOpValue";
884 let PrintMethod = "printAddrMode2OffsetOperand";
885 let ParserMatchClass = AM2OffsetImmAsmOperand;
886 let MIOperandInfo = (ops GPRnopc, i32imm);
890 // addrmode3 := reg +/- reg
891 // addrmode3 := reg +/- imm8
893 // FIXME: split into imm vs. reg versions.
894 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
895 class AddrMode3 : Operand<i32>,
896 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
897 let EncoderMethod = "getAddrMode3OpValue";
898 let ParserMatchClass = AddrMode3AsmOperand;
899 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
902 def addrmode3 : AddrMode3
904 let PrintMethod = "printAddrMode3Operand<false>";
907 def addrmode3_pre : AddrMode3
909 let PrintMethod = "printAddrMode3Operand<true>";
912 // FIXME: split into imm vs. reg versions.
913 // FIXME: parser method to handle +/- register.
914 def AM3OffsetAsmOperand : AsmOperandClass {
915 let Name = "AM3Offset";
916 let ParserMethod = "parseAM3Offset";
918 def am3offset : Operand<i32>,
919 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
920 [], [SDNPWantRoot]> {
921 let EncoderMethod = "getAddrMode3OffsetOpValue";
922 let PrintMethod = "printAddrMode3OffsetOperand";
923 let ParserMatchClass = AM3OffsetAsmOperand;
924 let MIOperandInfo = (ops GPR, i32imm);
927 // ldstm_mode := {ia, ib, da, db}
929 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
930 let EncoderMethod = "getLdStmModeOpValue";
931 let PrintMethod = "printLdStmModeOperand";
934 // addrmode5 := reg +/- imm8*4
936 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
937 class AddrMode5 : Operand<i32>,
938 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
939 let EncoderMethod = "getAddrMode5OpValue";
940 let DecoderMethod = "DecodeAddrMode5Operand";
941 let ParserMatchClass = AddrMode5AsmOperand;
942 let MIOperandInfo = (ops GPR:$base, i32imm);
945 def addrmode5 : AddrMode5 {
946 let PrintMethod = "printAddrMode5Operand<false>";
949 def addrmode5_pre : AddrMode5 {
950 let PrintMethod = "printAddrMode5Operand<true>";
953 // addrmode6 := reg with optional alignment
955 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
956 def addrmode6 : Operand<i32>,
957 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
958 let PrintMethod = "printAddrMode6Operand";
959 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
960 let EncoderMethod = "getAddrMode6AddressOpValue";
961 let DecoderMethod = "DecodeAddrMode6Operand";
962 let ParserMatchClass = AddrMode6AsmOperand;
965 def am6offset : Operand<i32>,
966 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
967 [], [SDNPWantRoot]> {
968 let PrintMethod = "printAddrMode6OffsetOperand";
969 let MIOperandInfo = (ops GPR);
970 let EncoderMethod = "getAddrMode6OffsetOpValue";
971 let DecoderMethod = "DecodeGPRRegisterClass";
974 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
975 // (single element from one lane) for size 32.
976 def addrmode6oneL32 : Operand<i32>,
977 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
978 let PrintMethod = "printAddrMode6Operand";
979 let MIOperandInfo = (ops GPR:$addr, i32imm);
980 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
983 // Special version of addrmode6 to handle alignment encoding for VLD-dup
984 // instructions, specifically VLD4-dup.
985 def addrmode6dup : Operand<i32>,
986 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
987 let PrintMethod = "printAddrMode6Operand";
988 let MIOperandInfo = (ops GPR:$addr, i32imm);
989 let EncoderMethod = "getAddrMode6DupAddressOpValue";
990 // FIXME: This is close, but not quite right. The alignment specifier is
992 let ParserMatchClass = AddrMode6AsmOperand;
995 // addrmodepc := pc + reg
997 def addrmodepc : Operand<i32>,
998 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
999 let PrintMethod = "printAddrModePCOperand";
1000 let MIOperandInfo = (ops GPR, i32imm);
1003 // addr_offset_none := reg
1005 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
1006 def addr_offset_none : Operand<i32>,
1007 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
1008 let PrintMethod = "printAddrMode7Operand";
1009 let DecoderMethod = "DecodeAddrMode7Operand";
1010 let ParserMatchClass = MemNoOffsetAsmOperand;
1011 let MIOperandInfo = (ops GPR:$base);
1014 def nohash_imm : Operand<i32> {
1015 let PrintMethod = "printNoHashImmediate";
1018 def CoprocNumAsmOperand : AsmOperandClass {
1019 let Name = "CoprocNum";
1020 let ParserMethod = "parseCoprocNumOperand";
1022 def p_imm : Operand<i32> {
1023 let PrintMethod = "printPImmediate";
1024 let ParserMatchClass = CoprocNumAsmOperand;
1025 let DecoderMethod = "DecodeCoprocessor";
1028 def CoprocRegAsmOperand : AsmOperandClass {
1029 let Name = "CoprocReg";
1030 let ParserMethod = "parseCoprocRegOperand";
1032 def c_imm : Operand<i32> {
1033 let PrintMethod = "printCImmediate";
1034 let ParserMatchClass = CoprocRegAsmOperand;
1036 def CoprocOptionAsmOperand : AsmOperandClass {
1037 let Name = "CoprocOption";
1038 let ParserMethod = "parseCoprocOptionOperand";
1040 def coproc_option_imm : Operand<i32> {
1041 let PrintMethod = "printCoprocOptionImm";
1042 let ParserMatchClass = CoprocOptionAsmOperand;
1045 //===----------------------------------------------------------------------===//
1047 include "ARMInstrFormats.td"
1049 //===----------------------------------------------------------------------===//
1050 // Multiclass helpers...
1053 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
1054 /// binop that produces a value.
1055 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1056 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
1057 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1058 PatFrag opnode, bit Commutable = 0> {
1059 // The register-immediate version is re-materializable. This is useful
1060 // in particular for taking the address of a local.
1061 let isReMaterializable = 1 in {
1062 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1063 iii, opc, "\t$Rd, $Rn, $imm",
1064 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
1065 Sched<[WriteALU, ReadALU]> {
1070 let Inst{19-16} = Rn;
1071 let Inst{15-12} = Rd;
1072 let Inst{11-0} = imm;
1075 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1076 iir, opc, "\t$Rd, $Rn, $Rm",
1077 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1078 Sched<[WriteALU, ReadALU, ReadALU]> {
1083 let isCommutable = Commutable;
1084 let Inst{19-16} = Rn;
1085 let Inst{15-12} = Rd;
1086 let Inst{11-4} = 0b00000000;
1090 def rsi : AsI1<opcod, (outs GPR:$Rd),
1091 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1092 iis, opc, "\t$Rd, $Rn, $shift",
1093 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1094 Sched<[WriteALUsi, ReadALU]> {
1099 let Inst{19-16} = Rn;
1100 let Inst{15-12} = Rd;
1101 let Inst{11-5} = shift{11-5};
1103 let Inst{3-0} = shift{3-0};
1106 def rsr : AsI1<opcod, (outs GPR:$Rd),
1107 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1108 iis, opc, "\t$Rd, $Rn, $shift",
1109 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1110 Sched<[WriteALUsr, ReadALUsr]> {
1115 let Inst{19-16} = Rn;
1116 let Inst{15-12} = Rd;
1117 let Inst{11-8} = shift{11-8};
1119 let Inst{6-5} = shift{6-5};
1121 let Inst{3-0} = shift{3-0};
1125 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1126 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1127 /// it is equivalent to the AsI1_bin_irs counterpart.
1128 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1129 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1130 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1131 PatFrag opnode, bit Commutable = 0> {
1132 // The register-immediate version is re-materializable. This is useful
1133 // in particular for taking the address of a local.
1134 let isReMaterializable = 1 in {
1135 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1136 iii, opc, "\t$Rd, $Rn, $imm",
1137 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]>,
1138 Sched<[WriteALU, ReadALU]> {
1143 let Inst{19-16} = Rn;
1144 let Inst{15-12} = Rd;
1145 let Inst{11-0} = imm;
1148 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1149 iir, opc, "\t$Rd, $Rn, $Rm",
1150 [/* pattern left blank */]>,
1151 Sched<[WriteALU, ReadALU, ReadALU]> {
1155 let Inst{11-4} = 0b00000000;
1158 let Inst{15-12} = Rd;
1159 let Inst{19-16} = Rn;
1162 def rsi : AsI1<opcod, (outs GPR:$Rd),
1163 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1164 iis, opc, "\t$Rd, $Rn, $shift",
1165 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1166 Sched<[WriteALUsi, ReadALU]> {
1171 let Inst{19-16} = Rn;
1172 let Inst{15-12} = Rd;
1173 let Inst{11-5} = shift{11-5};
1175 let Inst{3-0} = shift{3-0};
1178 def rsr : AsI1<opcod, (outs GPR:$Rd),
1179 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1180 iis, opc, "\t$Rd, $Rn, $shift",
1181 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1182 Sched<[WriteALUsr, ReadALUsr]> {
1187 let Inst{19-16} = Rn;
1188 let Inst{15-12} = Rd;
1189 let Inst{11-8} = shift{11-8};
1191 let Inst{6-5} = shift{6-5};
1193 let Inst{3-0} = shift{3-0};
1197 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1199 /// These opcodes will be converted to the real non-S opcodes by
1200 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1201 let hasPostISelHook = 1, Defs = [CPSR] in {
1202 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1203 InstrItinClass iis, PatFrag opnode,
1204 bit Commutable = 0> {
1205 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1207 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>,
1208 Sched<[WriteALU, ReadALU]>;
1210 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1212 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1213 Sched<[WriteALU, ReadALU, ReadALU]> {
1214 let isCommutable = Commutable;
1216 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1217 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1219 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1220 so_reg_imm:$shift))]>,
1221 Sched<[WriteALUsi, ReadALU]>;
1223 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1224 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1226 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1227 so_reg_reg:$shift))]>,
1228 Sched<[WriteALUSsr, ReadALUsr]>;
1232 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1233 /// operands are reversed.
1234 let hasPostISelHook = 1, Defs = [CPSR] in {
1235 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1236 InstrItinClass iis, PatFrag opnode,
1237 bit Commutable = 0> {
1238 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1240 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>,
1241 Sched<[WriteALU, ReadALU]>;
1243 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1244 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1246 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1248 Sched<[WriteALUsi, ReadALU]>;
1250 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1251 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1253 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1255 Sched<[WriteALUSsr, ReadALUsr]>;
1259 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1260 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1261 /// a explicit result, only implicitly set CPSR.
1262 let isCompare = 1, Defs = [CPSR] in {
1263 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1264 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1265 PatFrag opnode, bit Commutable = 0> {
1266 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1268 [(opnode GPR:$Rn, so_imm:$imm)]>,
1269 Sched<[WriteCMP, ReadALU]> {
1274 let Inst{19-16} = Rn;
1275 let Inst{15-12} = 0b0000;
1276 let Inst{11-0} = imm;
1278 let Unpredictable{15-12} = 0b1111;
1280 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1282 [(opnode GPR:$Rn, GPR:$Rm)]>,
1283 Sched<[WriteCMP, ReadALU, ReadALU]> {
1286 let isCommutable = Commutable;
1289 let Inst{19-16} = Rn;
1290 let Inst{15-12} = 0b0000;
1291 let Inst{11-4} = 0b00000000;
1294 let Unpredictable{15-12} = 0b1111;
1296 def rsi : AI1<opcod, (outs),
1297 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1298 opc, "\t$Rn, $shift",
1299 [(opnode GPR:$Rn, so_reg_imm:$shift)]>,
1300 Sched<[WriteCMPsi, ReadALU]> {
1305 let Inst{19-16} = Rn;
1306 let Inst{15-12} = 0b0000;
1307 let Inst{11-5} = shift{11-5};
1309 let Inst{3-0} = shift{3-0};
1311 let Unpredictable{15-12} = 0b1111;
1313 def rsr : AI1<opcod, (outs),
1314 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1315 opc, "\t$Rn, $shift",
1316 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>,
1317 Sched<[WriteCMPsr, ReadALU]> {
1322 let Inst{19-16} = Rn;
1323 let Inst{15-12} = 0b0000;
1324 let Inst{11-8} = shift{11-8};
1326 let Inst{6-5} = shift{6-5};
1328 let Inst{3-0} = shift{3-0};
1330 let Unpredictable{15-12} = 0b1111;
1336 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1337 /// register and one whose operand is a register rotated by 8/16/24.
1338 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1339 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1340 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1341 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1342 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1343 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1347 let Inst{19-16} = 0b1111;
1348 let Inst{15-12} = Rd;
1349 let Inst{11-10} = rot;
1353 class AI_ext_rrot_np<bits<8> opcod, string opc>
1354 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1355 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1356 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1358 let Inst{19-16} = 0b1111;
1359 let Inst{11-10} = rot;
1362 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1363 /// register and one whose operand is a register rotated by 8/16/24.
1364 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1365 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1366 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1367 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1368 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1369 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1374 let Inst{19-16} = Rn;
1375 let Inst{15-12} = Rd;
1376 let Inst{11-10} = rot;
1377 let Inst{9-4} = 0b000111;
1381 class AI_exta_rrot_np<bits<8> opcod, string opc>
1382 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1383 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1384 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1387 let Inst{19-16} = Rn;
1388 let Inst{11-10} = rot;
1391 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1392 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1393 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1394 bit Commutable = 0> {
1395 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1396 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1397 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1398 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1400 Sched<[WriteALU, ReadALU]> {
1405 let Inst{15-12} = Rd;
1406 let Inst{19-16} = Rn;
1407 let Inst{11-0} = imm;
1409 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1410 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1411 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1413 Sched<[WriteALU, ReadALU, ReadALU]> {
1417 let Inst{11-4} = 0b00000000;
1419 let isCommutable = Commutable;
1421 let Inst{15-12} = Rd;
1422 let Inst{19-16} = Rn;
1424 def rsi : AsI1<opcod, (outs GPR:$Rd),
1425 (ins GPR:$Rn, so_reg_imm:$shift),
1426 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1427 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1429 Sched<[WriteALUsi, ReadALU]> {
1434 let Inst{19-16} = Rn;
1435 let Inst{15-12} = Rd;
1436 let Inst{11-5} = shift{11-5};
1438 let Inst{3-0} = shift{3-0};
1440 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1441 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1442 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1443 [(set GPRnopc:$Rd, CPSR,
1444 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1446 Sched<[WriteALUsr, ReadALUsr]> {
1451 let Inst{19-16} = Rn;
1452 let Inst{15-12} = Rd;
1453 let Inst{11-8} = shift{11-8};
1455 let Inst{6-5} = shift{6-5};
1457 let Inst{3-0} = shift{3-0};
1462 /// AI1_rsc_irs - Define instructions and patterns for rsc
1463 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1464 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
1465 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1466 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1467 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1468 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1470 Sched<[WriteALU, ReadALU]> {
1475 let Inst{15-12} = Rd;
1476 let Inst{19-16} = Rn;
1477 let Inst{11-0} = imm;
1479 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1480 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1481 [/* pattern left blank */]>,
1482 Sched<[WriteALU, ReadALU, ReadALU]> {
1486 let Inst{11-4} = 0b00000000;
1489 let Inst{15-12} = Rd;
1490 let Inst{19-16} = Rn;
1492 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1493 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1494 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1496 Sched<[WriteALUsi, ReadALU]> {
1501 let Inst{19-16} = Rn;
1502 let Inst{15-12} = Rd;
1503 let Inst{11-5} = shift{11-5};
1505 let Inst{3-0} = shift{3-0};
1507 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1508 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1509 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1511 Sched<[WriteALUsr, ReadALUsr]> {
1516 let Inst{19-16} = Rn;
1517 let Inst{15-12} = Rd;
1518 let Inst{11-8} = shift{11-8};
1520 let Inst{6-5} = shift{6-5};
1522 let Inst{3-0} = shift{3-0};
1527 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1528 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1529 InstrItinClass iir, PatFrag opnode> {
1530 // Note: We use the complex addrmode_imm12 rather than just an input
1531 // GPR and a constrained immediate so that we can use this to match
1532 // frame index references and avoid matching constant pool references.
1533 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1534 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1535 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1538 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1539 let Inst{19-16} = addr{16-13}; // Rn
1540 let Inst{15-12} = Rt;
1541 let Inst{11-0} = addr{11-0}; // imm12
1543 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1544 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1545 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1548 let shift{4} = 0; // Inst{4} = 0
1549 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1550 let Inst{19-16} = shift{16-13}; // Rn
1551 let Inst{15-12} = Rt;
1552 let Inst{11-0} = shift{11-0};
1557 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1558 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1559 InstrItinClass iir, PatFrag opnode> {
1560 // Note: We use the complex addrmode_imm12 rather than just an input
1561 // GPR and a constrained immediate so that we can use this to match
1562 // frame index references and avoid matching constant pool references.
1563 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1564 (ins addrmode_imm12:$addr),
1565 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1566 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1569 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1570 let Inst{19-16} = addr{16-13}; // Rn
1571 let Inst{15-12} = Rt;
1572 let Inst{11-0} = addr{11-0}; // imm12
1574 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1575 (ins ldst_so_reg:$shift),
1576 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1577 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1580 let shift{4} = 0; // Inst{4} = 0
1581 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1582 let Inst{19-16} = shift{16-13}; // Rn
1583 let Inst{15-12} = Rt;
1584 let Inst{11-0} = shift{11-0};
1590 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1591 InstrItinClass iir, PatFrag opnode> {
1592 // Note: We use the complex addrmode_imm12 rather than just an input
1593 // GPR and a constrained immediate so that we can use this to match
1594 // frame index references and avoid matching constant pool references.
1595 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1596 (ins GPR:$Rt, addrmode_imm12:$addr),
1597 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1598 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1601 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1602 let Inst{19-16} = addr{16-13}; // Rn
1603 let Inst{15-12} = Rt;
1604 let Inst{11-0} = addr{11-0}; // imm12
1606 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1607 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1608 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1611 let shift{4} = 0; // Inst{4} = 0
1612 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1613 let Inst{19-16} = shift{16-13}; // Rn
1614 let Inst{15-12} = Rt;
1615 let Inst{11-0} = shift{11-0};
1619 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1620 InstrItinClass iir, PatFrag opnode> {
1621 // Note: We use the complex addrmode_imm12 rather than just an input
1622 // GPR and a constrained immediate so that we can use this to match
1623 // frame index references and avoid matching constant pool references.
1624 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1625 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1626 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1627 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1630 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1631 let Inst{19-16} = addr{16-13}; // Rn
1632 let Inst{15-12} = Rt;
1633 let Inst{11-0} = addr{11-0}; // imm12
1635 def rs : AI2ldst<0b011, 0, isByte, (outs),
1636 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1637 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1638 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1641 let shift{4} = 0; // Inst{4} = 0
1642 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1643 let Inst{19-16} = shift{16-13}; // Rn
1644 let Inst{15-12} = Rt;
1645 let Inst{11-0} = shift{11-0};
1650 //===----------------------------------------------------------------------===//
1652 //===----------------------------------------------------------------------===//
1654 //===----------------------------------------------------------------------===//
1655 // Miscellaneous Instructions.
1658 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1659 /// the function. The first operand is the ID# for this instruction, the second
1660 /// is the index into the MachineConstantPool that this is, the third is the
1661 /// size in bytes of this constant pool entry.
1662 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1663 def CONSTPOOL_ENTRY :
1664 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1665 i32imm:$size), NoItinerary, []>;
1667 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1668 // from removing one half of the matched pairs. That breaks PEI, which assumes
1669 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1670 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1671 def ADJCALLSTACKUP :
1672 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1673 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1675 def ADJCALLSTACKDOWN :
1676 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1677 [(ARMcallseq_start timm:$amt)]>;
1680 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
1681 // (These pseudos use a hand-written selection code).
1682 let usesCustomInserter = 1, Defs = [CPSR], mayLoad = 1, mayStore = 1 in {
1683 def ATOMOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1684 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1686 def ATOMXOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1687 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1689 def ATOMADD6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1690 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1692 def ATOMSUB6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1693 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1695 def ATOMNAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1696 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1698 def ATOMAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1699 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1701 def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1702 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1704 def ATOMCMPXCHG6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1705 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2,
1706 GPR:$set1, GPR:$set2),
1708 def ATOMMIN6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1709 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1711 def ATOMUMIN6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1712 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1714 def ATOMMAX6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1715 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1717 def ATOMUMAX6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1718 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1722 def HINT : AI<(outs), (ins imm0_4:$imm), MiscFrm, NoItinerary,
1723 "hint", "\t$imm", []>, Requires<[IsARM, HasV6]> {
1725 let Inst{27-3} = 0b0011001000001111000000000;
1726 let Inst{2-0} = imm;
1729 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1730 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1731 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1732 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1733 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1735 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1736 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1741 let Inst{15-12} = Rd;
1742 let Inst{19-16} = Rn;
1743 let Inst{27-20} = 0b01101000;
1744 let Inst{7-4} = 0b1011;
1745 let Inst{11-8} = 0b1111;
1746 let Unpredictable{11-8} = 0b1111;
1749 // The 16-bit operand $val can be used by a debugger to store more information
1750 // about the breakpoint.
1751 def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1752 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1754 let Inst{3-0} = val{3-0};
1755 let Inst{19-8} = val{15-4};
1756 let Inst{27-20} = 0b00010010;
1757 let Inst{31-28} = 0xe; // AL
1758 let Inst{7-4} = 0b0111;
1761 // Change Processor State
1762 // FIXME: We should use InstAlias to handle the optional operands.
1763 class CPS<dag iops, string asm_ops>
1764 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1765 []>, Requires<[IsARM]> {
1771 let Inst{31-28} = 0b1111;
1772 let Inst{27-20} = 0b00010000;
1773 let Inst{19-18} = imod;
1774 let Inst{17} = M; // Enabled if mode is set;
1775 let Inst{16-9} = 0b00000000;
1776 let Inst{8-6} = iflags;
1778 let Inst{4-0} = mode;
1781 let DecoderMethod = "DecodeCPSInstruction" in {
1783 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1784 "$imod\t$iflags, $mode">;
1785 let mode = 0, M = 0 in
1786 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1788 let imod = 0, iflags = 0, M = 1 in
1789 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1792 // Preload signals the memory system of possible future data/instruction access.
1793 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1795 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1796 !strconcat(opc, "\t$addr"),
1797 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>,
1798 Sched<[WritePreLd]> {
1801 let Inst{31-26} = 0b111101;
1802 let Inst{25} = 0; // 0 for immediate form
1803 let Inst{24} = data;
1804 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1805 let Inst{22} = read;
1806 let Inst{21-20} = 0b01;
1807 let Inst{19-16} = addr{16-13}; // Rn
1808 let Inst{15-12} = 0b1111;
1809 let Inst{11-0} = addr{11-0}; // imm12
1812 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1813 !strconcat(opc, "\t$shift"),
1814 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>,
1815 Sched<[WritePreLd]> {
1817 let Inst{31-26} = 0b111101;
1818 let Inst{25} = 1; // 1 for register form
1819 let Inst{24} = data;
1820 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1821 let Inst{22} = read;
1822 let Inst{21-20} = 0b01;
1823 let Inst{19-16} = shift{16-13}; // Rn
1824 let Inst{15-12} = 0b1111;
1825 let Inst{11-0} = shift{11-0};
1830 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1831 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1832 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1834 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1835 "setend\t$end", []>, Requires<[IsARM]> {
1837 let Inst{31-10} = 0b1111000100000001000000;
1842 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1843 []>, Requires<[IsARM, HasV7]> {
1845 let Inst{27-4} = 0b001100100000111100001111;
1846 let Inst{3-0} = opt;
1850 * A5.4 Permanently UNDEFINED instructions.
1852 * For most targets use UDF #65006, for which the OS will generate SIGTRAP.
1853 * Other UDF encodings generate SIGILL.
1855 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb.
1857 * 1110 0111 1111 iiii iiii iiii 1111 iiii
1859 * 1101 1110 iiii iiii
1860 * It uses the following encoding:
1861 * 1110 0111 1111 1110 1101 1110 1111 0000
1862 * - In ARM: UDF #60896;
1863 * - In Thumb: UDF #254 followed by a branch-to-self.
1865 let isBarrier = 1, isTerminator = 1 in
1866 def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary,
1868 Requires<[IsARM,UseNaClTrap]> {
1869 let Inst = 0xe7fedef0;
1871 let isBarrier = 1, isTerminator = 1 in
1872 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1874 Requires<[IsARM,DontUseNaClTrap]> {
1875 let Inst = 0xe7ffdefe;
1878 // Address computation and loads and stores in PIC mode.
1879 let isNotDuplicable = 1 in {
1880 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1882 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>,
1883 Sched<[WriteALU, ReadALU]>;
1885 let AddedComplexity = 10 in {
1886 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1888 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1890 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1892 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1894 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1896 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1898 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1900 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1902 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1904 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1906 let AddedComplexity = 10 in {
1907 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1908 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1910 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1911 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1912 addrmodepc:$addr)]>;
1914 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1915 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1917 } // isNotDuplicable = 1
1920 // LEApcrel - Load a pc-relative address into a register without offending the
1922 let neverHasSideEffects = 1, isReMaterializable = 1 in
1923 // The 'adr' mnemonic encodes differently if the label is before or after
1924 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1925 // know until then which form of the instruction will be used.
1926 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1927 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>,
1928 Sched<[WriteALU, ReadALU]> {
1931 let Inst{27-25} = 0b001;
1933 let Inst{23-22} = label{13-12};
1936 let Inst{19-16} = 0b1111;
1937 let Inst{15-12} = Rd;
1938 let Inst{11-0} = label{11-0};
1941 let hasSideEffects = 1 in {
1942 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1943 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
1945 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1946 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1947 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
1950 //===----------------------------------------------------------------------===//
1951 // Control Flow Instructions.
1954 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1956 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1957 "bx", "\tlr", [(ARMretflag)]>,
1958 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
1959 let Inst{27-0} = 0b0001001011111111111100011110;
1963 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1964 "mov", "\tpc, lr", [(ARMretflag)]>,
1965 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> {
1966 let Inst{27-0} = 0b0001101000001111000000001110;
1970 // Indirect branches
1971 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1973 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1974 [(brind GPR:$dst)]>,
1975 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
1977 let Inst{31-4} = 0b1110000100101111111111110001;
1978 let Inst{3-0} = dst;
1981 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1982 "bx", "\t$dst", [/* pattern left blank */]>,
1983 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
1985 let Inst{27-4} = 0b000100101111111111110001;
1986 let Inst{3-0} = dst;
1990 // SP is marked as a use to prevent stack-pointer assignments that appear
1991 // immediately before calls from potentially appearing dead.
1993 // FIXME: Do we really need a non-predicated version? If so, it should
1994 // at least be a pseudo instruction expanding to the predicated version
1995 // at MC lowering time.
1996 Defs = [LR], Uses = [SP] in {
1997 def BL : ABXI<0b1011, (outs), (ins bl_target:$func),
1998 IIC_Br, "bl\t$func",
1999 [(ARMcall tglobaladdr:$func)]>,
2000 Requires<[IsARM]>, Sched<[WriteBrL]> {
2001 let Inst{31-28} = 0b1110;
2003 let Inst{23-0} = func;
2004 let DecoderMethod = "DecodeBranchImmInstruction";
2007 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
2008 IIC_Br, "bl", "\t$func",
2009 [(ARMcall_pred tglobaladdr:$func)]>,
2010 Requires<[IsARM]>, Sched<[WriteBrL]> {
2012 let Inst{23-0} = func;
2013 let DecoderMethod = "DecodeBranchImmInstruction";
2017 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
2018 IIC_Br, "blx\t$func",
2019 [(ARMcall GPR:$func)]>,
2020 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2022 let Inst{31-4} = 0b1110000100101111111111110011;
2023 let Inst{3-0} = func;
2026 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
2027 IIC_Br, "blx", "\t$func",
2028 [(ARMcall_pred GPR:$func)]>,
2029 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2031 let Inst{27-4} = 0b000100101111111111110011;
2032 let Inst{3-0} = func;
2036 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
2037 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2038 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2039 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>;
2042 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2043 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2044 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
2046 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
2047 // return stack predictor.
2048 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
2049 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
2050 Requires<[IsARM]>, Sched<[WriteBr]>;
2053 let isBranch = 1, isTerminator = 1 in {
2054 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2055 // a two-value operand where a dag node expects two operands. :(
2056 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
2057 IIC_Br, "b", "\t$target",
2058 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>,
2061 let Inst{23-0} = target;
2062 let DecoderMethod = "DecodeBranchImmInstruction";
2065 let isBarrier = 1 in {
2066 // B is "predicable" since it's just a Bcc with an 'always' condition.
2067 let isPredicable = 1 in
2068 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2069 // should be sufficient.
2070 // FIXME: Is B really a Barrier? That doesn't seem right.
2071 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
2072 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>,
2075 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2076 def BR_JTr : ARMPseudoInst<(outs),
2077 (ins GPR:$target, i32imm:$jt, i32imm:$id),
2079 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>,
2081 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2082 // into i12 and rs suffixed versions.
2083 def BR_JTm : ARMPseudoInst<(outs),
2084 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
2086 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
2087 imm:$id)]>, Sched<[WriteBrTbl]>;
2088 def BR_JTadd : ARMPseudoInst<(outs),
2089 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
2091 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
2092 imm:$id)]>, Sched<[WriteBrTbl]>;
2093 } // isNotDuplicable = 1, isIndirectBranch = 1
2099 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2100 "blx\t$target", []>,
2101 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2102 let Inst{31-25} = 0b1111101;
2104 let Inst{23-0} = target{24-1};
2105 let Inst{24} = target{0};
2108 // Branch and Exchange Jazelle
2109 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2110 [/* pattern left blank */]>, Sched<[WriteBr]> {
2112 let Inst{23-20} = 0b0010;
2113 let Inst{19-8} = 0xfff;
2114 let Inst{7-4} = 0b0010;
2115 let Inst{3-0} = func;
2120 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
2121 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>,
2124 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>,
2127 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
2129 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2130 Requires<[IsARM]>, Sched<[WriteBr]>;
2132 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
2134 (BX GPR:$dst)>, Sched<[WriteBr]>,
2138 // Secure Monitor Call is a system instruction.
2139 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2140 []>, Requires<[IsARM, HasTrustZone]> {
2142 let Inst{23-4} = 0b01100000000000000111;
2143 let Inst{3-0} = opt;
2146 // Supervisor Call (Software Interrupt)
2147 let isCall = 1, Uses = [SP] in {
2148 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>,
2151 let Inst{23-0} = svc;
2155 // Store Return State
2156 class SRSI<bit wb, string asm>
2157 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2158 NoItinerary, asm, "", []> {
2160 let Inst{31-28} = 0b1111;
2161 let Inst{27-25} = 0b100;
2165 let Inst{19-16} = 0b1101; // SP
2166 let Inst{15-5} = 0b00000101000;
2167 let Inst{4-0} = mode;
2170 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2171 let Inst{24-23} = 0;
2173 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2174 let Inst{24-23} = 0;
2176 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2177 let Inst{24-23} = 0b10;
2179 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2180 let Inst{24-23} = 0b10;
2182 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2183 let Inst{24-23} = 0b01;
2185 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2186 let Inst{24-23} = 0b01;
2188 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2189 let Inst{24-23} = 0b11;
2191 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2192 let Inst{24-23} = 0b11;
2195 def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>;
2196 def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>;
2198 def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>;
2199 def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>;
2201 def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>;
2202 def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>;
2204 def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>;
2205 def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>;
2207 // Return From Exception
2208 class RFEI<bit wb, string asm>
2209 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2210 NoItinerary, asm, "", []> {
2212 let Inst{31-28} = 0b1111;
2213 let Inst{27-25} = 0b100;
2217 let Inst{19-16} = Rn;
2218 let Inst{15-0} = 0xa00;
2221 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2222 let Inst{24-23} = 0;
2224 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2225 let Inst{24-23} = 0;
2227 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2228 let Inst{24-23} = 0b10;
2230 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2231 let Inst{24-23} = 0b10;
2233 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2234 let Inst{24-23} = 0b01;
2236 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2237 let Inst{24-23} = 0b01;
2239 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2240 let Inst{24-23} = 0b11;
2242 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2243 let Inst{24-23} = 0b11;
2246 //===----------------------------------------------------------------------===//
2247 // Load / Store Instructions.
2253 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2254 UnOpFrag<(load node:$Src)>>;
2255 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2256 UnOpFrag<(zextloadi8 node:$Src)>>;
2257 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2258 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2259 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2260 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2262 // Special LDR for loads from non-pc-relative constpools.
2263 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2264 isReMaterializable = 1, isCodeGenOnly = 1 in
2265 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2266 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2270 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2271 let Inst{19-16} = 0b1111;
2272 let Inst{15-12} = Rt;
2273 let Inst{11-0} = addr{11-0}; // imm12
2276 // Loads with zero extension
2277 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2278 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2279 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2281 // Loads with sign extension
2282 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2283 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2284 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2286 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2287 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2288 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2290 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2292 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
2293 (ins addrmode3:$addr), LdMiscFrm,
2294 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2295 []>, Requires<[IsARM, HasV5TE]>;
2299 multiclass AI2_ldridx<bit isByte, string opc,
2300 InstrItinClass iii, InstrItinClass iir> {
2301 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2302 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii,
2303 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2306 let Inst{23} = addr{12};
2307 let Inst{19-16} = addr{16-13};
2308 let Inst{11-0} = addr{11-0};
2309 let DecoderMethod = "DecodeLDRPreImm";
2312 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2313 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2314 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2317 let Inst{23} = addr{12};
2318 let Inst{19-16} = addr{16-13};
2319 let Inst{11-0} = addr{11-0};
2321 let DecoderMethod = "DecodeLDRPreReg";
2324 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2325 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2326 IndexModePost, LdFrm, iir,
2327 opc, "\t$Rt, $addr, $offset",
2328 "$addr.base = $Rn_wb", []> {
2334 let Inst{23} = offset{12};
2335 let Inst{19-16} = addr;
2336 let Inst{11-0} = offset{11-0};
2339 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2342 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2343 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2344 IndexModePost, LdFrm, iii,
2345 opc, "\t$Rt, $addr, $offset",
2346 "$addr.base = $Rn_wb", []> {
2352 let Inst{23} = offset{12};
2353 let Inst{19-16} = addr;
2354 let Inst{11-0} = offset{11-0};
2356 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2361 let mayLoad = 1, neverHasSideEffects = 1 in {
2362 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2363 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2364 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2365 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2368 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2369 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2370 (ins addrmode3_pre:$addr), IndexModePre,
2372 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2374 let Inst{23} = addr{8}; // U bit
2375 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2376 let Inst{19-16} = addr{12-9}; // Rn
2377 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2378 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2379 let DecoderMethod = "DecodeAddrMode3Instruction";
2381 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2382 (ins addr_offset_none:$addr, am3offset:$offset),
2383 IndexModePost, LdMiscFrm, itin,
2384 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2388 let Inst{23} = offset{8}; // U bit
2389 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2390 let Inst{19-16} = addr;
2391 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2392 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2393 let DecoderMethod = "DecodeAddrMode3Instruction";
2397 let mayLoad = 1, neverHasSideEffects = 1 in {
2398 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2399 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2400 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2401 let hasExtraDefRegAllocReq = 1 in {
2402 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2403 (ins addrmode3_pre:$addr), IndexModePre,
2404 LdMiscFrm, IIC_iLoad_d_ru,
2405 "ldrd", "\t$Rt, $Rt2, $addr!",
2406 "$addr.base = $Rn_wb", []> {
2408 let Inst{23} = addr{8}; // U bit
2409 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2410 let Inst{19-16} = addr{12-9}; // Rn
2411 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2412 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2413 let DecoderMethod = "DecodeAddrMode3Instruction";
2415 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2416 (ins addr_offset_none:$addr, am3offset:$offset),
2417 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2418 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2419 "$addr.base = $Rn_wb", []> {
2422 let Inst{23} = offset{8}; // U bit
2423 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2424 let Inst{19-16} = addr;
2425 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2426 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2427 let DecoderMethod = "DecodeAddrMode3Instruction";
2429 } // hasExtraDefRegAllocReq = 1
2430 } // mayLoad = 1, neverHasSideEffects = 1
2432 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2433 let mayLoad = 1, neverHasSideEffects = 1 in {
2434 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2435 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2436 IndexModePost, LdFrm, IIC_iLoad_ru,
2437 "ldrt", "\t$Rt, $addr, $offset",
2438 "$addr.base = $Rn_wb", []> {
2444 let Inst{23} = offset{12};
2445 let Inst{21} = 1; // overwrite
2446 let Inst{19-16} = addr;
2447 let Inst{11-5} = offset{11-5};
2449 let Inst{3-0} = offset{3-0};
2450 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2453 def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2454 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2455 IndexModePost, LdFrm, IIC_iLoad_ru,
2456 "ldrt", "\t$Rt, $addr, $offset",
2457 "$addr.base = $Rn_wb", []> {
2463 let Inst{23} = offset{12};
2464 let Inst{21} = 1; // overwrite
2465 let Inst{19-16} = addr;
2466 let Inst{11-0} = offset{11-0};
2467 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2470 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2471 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2472 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2473 "ldrbt", "\t$Rt, $addr, $offset",
2474 "$addr.base = $Rn_wb", []> {
2480 let Inst{23} = offset{12};
2481 let Inst{21} = 1; // overwrite
2482 let Inst{19-16} = addr;
2483 let Inst{11-5} = offset{11-5};
2485 let Inst{3-0} = offset{3-0};
2486 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2489 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2490 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2491 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2492 "ldrbt", "\t$Rt, $addr, $offset",
2493 "$addr.base = $Rn_wb", []> {
2499 let Inst{23} = offset{12};
2500 let Inst{21} = 1; // overwrite
2501 let Inst{19-16} = addr;
2502 let Inst{11-0} = offset{11-0};
2503 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2506 multiclass AI3ldrT<bits<4> op, string opc> {
2507 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2508 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2509 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2510 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2512 let Inst{23} = offset{8};
2514 let Inst{11-8} = offset{7-4};
2515 let Inst{3-0} = offset{3-0};
2517 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2518 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2519 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2520 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2522 let Inst{23} = Rm{4};
2525 let Unpredictable{11-8} = 0b1111;
2526 let Inst{3-0} = Rm{3-0};
2527 let DecoderMethod = "DecodeLDR";
2531 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2532 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2533 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2538 // Stores with truncate
2539 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2540 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2541 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2544 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2545 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2546 StMiscFrm, IIC_iStore_d_r,
2547 "strd", "\t$Rt, $src2, $addr", []>,
2548 Requires<[IsARM, HasV5TE]> {
2553 multiclass AI2_stridx<bit isByte, string opc,
2554 InstrItinClass iii, InstrItinClass iir> {
2555 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2556 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre,
2558 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2561 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2562 let Inst{19-16} = addr{16-13}; // Rn
2563 let Inst{11-0} = addr{11-0}; // imm12
2564 let DecoderMethod = "DecodeSTRPreImm";
2567 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2568 (ins GPR:$Rt, ldst_so_reg:$addr),
2569 IndexModePre, StFrm, iir,
2570 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2573 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2574 let Inst{19-16} = addr{16-13}; // Rn
2575 let Inst{11-0} = addr{11-0};
2576 let Inst{4} = 0; // Inst{4} = 0
2577 let DecoderMethod = "DecodeSTRPreReg";
2579 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2580 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2581 IndexModePost, StFrm, iir,
2582 opc, "\t$Rt, $addr, $offset",
2583 "$addr.base = $Rn_wb", []> {
2589 let Inst{23} = offset{12};
2590 let Inst{19-16} = addr;
2591 let Inst{11-0} = offset{11-0};
2594 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2597 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2598 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2599 IndexModePost, StFrm, iii,
2600 opc, "\t$Rt, $addr, $offset",
2601 "$addr.base = $Rn_wb", []> {
2607 let Inst{23} = offset{12};
2608 let Inst{19-16} = addr;
2609 let Inst{11-0} = offset{11-0};
2611 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2615 let mayStore = 1, neverHasSideEffects = 1 in {
2616 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2617 // IIC_iStore_siu depending on whether it the offset register is shifted.
2618 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2619 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2622 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2623 am2offset_reg:$offset),
2624 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2625 am2offset_reg:$offset)>;
2626 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2627 am2offset_imm:$offset),
2628 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2629 am2offset_imm:$offset)>;
2630 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2631 am2offset_reg:$offset),
2632 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2633 am2offset_reg:$offset)>;
2634 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2635 am2offset_imm:$offset),
2636 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2637 am2offset_imm:$offset)>;
2639 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2640 // put the patterns on the instruction definitions directly as ISel wants
2641 // the address base and offset to be separate operands, not a single
2642 // complex operand like we represent the instructions themselves. The
2643 // pseudos map between the two.
2644 let usesCustomInserter = 1,
2645 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2646 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2647 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2650 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2651 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2652 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2655 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2656 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2657 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2660 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2661 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2662 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2665 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2666 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2667 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2670 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2675 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2676 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
2677 StMiscFrm, IIC_iStore_bh_ru,
2678 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2680 let Inst{23} = addr{8}; // U bit
2681 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2682 let Inst{19-16} = addr{12-9}; // Rn
2683 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2684 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2685 let DecoderMethod = "DecodeAddrMode3Instruction";
2688 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2689 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2690 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2691 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2692 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2693 addr_offset_none:$addr,
2694 am3offset:$offset))]> {
2697 let Inst{23} = offset{8}; // U bit
2698 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2699 let Inst{19-16} = addr;
2700 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2701 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2702 let DecoderMethod = "DecodeAddrMode3Instruction";
2705 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2706 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2707 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
2708 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2709 "strd", "\t$Rt, $Rt2, $addr!",
2710 "$addr.base = $Rn_wb", []> {
2712 let Inst{23} = addr{8}; // U bit
2713 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2714 let Inst{19-16} = addr{12-9}; // Rn
2715 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2716 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2717 let DecoderMethod = "DecodeAddrMode3Instruction";
2720 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2721 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2723 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2724 "strd", "\t$Rt, $Rt2, $addr, $offset",
2725 "$addr.base = $Rn_wb", []> {
2728 let Inst{23} = offset{8}; // U bit
2729 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2730 let Inst{19-16} = addr;
2731 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2732 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2733 let DecoderMethod = "DecodeAddrMode3Instruction";
2735 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2737 // STRT, STRBT, and STRHT
2739 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2740 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2741 IndexModePost, StFrm, IIC_iStore_bh_ru,
2742 "strbt", "\t$Rt, $addr, $offset",
2743 "$addr.base = $Rn_wb", []> {
2749 let Inst{23} = offset{12};
2750 let Inst{21} = 1; // overwrite
2751 let Inst{19-16} = addr;
2752 let Inst{11-5} = offset{11-5};
2754 let Inst{3-0} = offset{3-0};
2755 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2758 def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2759 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2760 IndexModePost, StFrm, IIC_iStore_bh_ru,
2761 "strbt", "\t$Rt, $addr, $offset",
2762 "$addr.base = $Rn_wb", []> {
2768 let Inst{23} = offset{12};
2769 let Inst{21} = 1; // overwrite
2770 let Inst{19-16} = addr;
2771 let Inst{11-0} = offset{11-0};
2772 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2775 let mayStore = 1, neverHasSideEffects = 1 in {
2776 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2777 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2778 IndexModePost, StFrm, IIC_iStore_ru,
2779 "strt", "\t$Rt, $addr, $offset",
2780 "$addr.base = $Rn_wb", []> {
2786 let Inst{23} = offset{12};
2787 let Inst{21} = 1; // overwrite
2788 let Inst{19-16} = addr;
2789 let Inst{11-5} = offset{11-5};
2791 let Inst{3-0} = offset{3-0};
2792 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2795 def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2796 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2797 IndexModePost, StFrm, IIC_iStore_ru,
2798 "strt", "\t$Rt, $addr, $offset",
2799 "$addr.base = $Rn_wb", []> {
2805 let Inst{23} = offset{12};
2806 let Inst{21} = 1; // overwrite
2807 let Inst{19-16} = addr;
2808 let Inst{11-0} = offset{11-0};
2809 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2814 multiclass AI3strT<bits<4> op, string opc> {
2815 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2816 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2817 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2818 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2820 let Inst{23} = offset{8};
2822 let Inst{11-8} = offset{7-4};
2823 let Inst{3-0} = offset{3-0};
2825 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2826 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2827 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2828 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2830 let Inst{23} = Rm{4};
2833 let Inst{3-0} = Rm{3-0};
2838 defm STRHT : AI3strT<0b1011, "strht">;
2841 //===----------------------------------------------------------------------===//
2842 // Load / store multiple Instructions.
2845 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
2846 InstrItinClass itin, InstrItinClass itin_upd> {
2847 // IA is the default, so no need for an explicit suffix on the
2848 // mnemonic here. Without it is the canonical spelling.
2850 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2851 IndexModeNone, f, itin,
2852 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
2853 let Inst{24-23} = 0b01; // Increment After
2854 let Inst{22} = P_bit;
2855 let Inst{21} = 0; // No writeback
2856 let Inst{20} = L_bit;
2859 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2860 IndexModeUpd, f, itin_upd,
2861 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2862 let Inst{24-23} = 0b01; // Increment After
2863 let Inst{22} = P_bit;
2864 let Inst{21} = 1; // Writeback
2865 let Inst{20} = L_bit;
2867 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2870 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2871 IndexModeNone, f, itin,
2872 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
2873 let Inst{24-23} = 0b00; // Decrement After
2874 let Inst{22} = P_bit;
2875 let Inst{21} = 0; // No writeback
2876 let Inst{20} = L_bit;
2879 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2880 IndexModeUpd, f, itin_upd,
2881 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2882 let Inst{24-23} = 0b00; // Decrement After
2883 let Inst{22} = P_bit;
2884 let Inst{21} = 1; // Writeback
2885 let Inst{20} = L_bit;
2887 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2890 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2891 IndexModeNone, f, itin,
2892 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
2893 let Inst{24-23} = 0b10; // Decrement Before
2894 let Inst{22} = P_bit;
2895 let Inst{21} = 0; // No writeback
2896 let Inst{20} = L_bit;
2899 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2900 IndexModeUpd, f, itin_upd,
2901 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2902 let Inst{24-23} = 0b10; // Decrement Before
2903 let Inst{22} = P_bit;
2904 let Inst{21} = 1; // Writeback
2905 let Inst{20} = L_bit;
2907 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2910 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2911 IndexModeNone, f, itin,
2912 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
2913 let Inst{24-23} = 0b11; // Increment Before
2914 let Inst{22} = P_bit;
2915 let Inst{21} = 0; // No writeback
2916 let Inst{20} = L_bit;
2919 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2920 IndexModeUpd, f, itin_upd,
2921 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2922 let Inst{24-23} = 0b11; // Increment Before
2923 let Inst{22} = P_bit;
2924 let Inst{21} = 1; // Writeback
2925 let Inst{20} = L_bit;
2927 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2931 let neverHasSideEffects = 1 in {
2933 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2934 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
2937 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2938 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
2941 } // neverHasSideEffects
2943 // FIXME: remove when we have a way to marking a MI with these properties.
2944 // FIXME: Should pc be an implicit operand like PICADD, etc?
2945 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2946 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2947 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2948 reglist:$regs, variable_ops),
2949 4, IIC_iLoad_mBr, [],
2950 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2951 RegConstraint<"$Rn = $wb">;
2953 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2954 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
2957 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2958 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
2963 //===----------------------------------------------------------------------===//
2964 // Move Instructions.
2967 let neverHasSideEffects = 1 in
2968 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2969 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
2973 let Inst{19-16} = 0b0000;
2974 let Inst{11-4} = 0b00000000;
2977 let Inst{15-12} = Rd;
2980 // A version for the smaller set of tail call registers.
2981 let neverHasSideEffects = 1 in
2982 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2983 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
2987 let Inst{11-4} = 0b00000000;
2990 let Inst{15-12} = Rd;
2993 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
2994 DPSoRegRegFrm, IIC_iMOVsr,
2995 "mov", "\t$Rd, $src",
2996 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
3000 let Inst{15-12} = Rd;
3001 let Inst{19-16} = 0b0000;
3002 let Inst{11-8} = src{11-8};
3004 let Inst{6-5} = src{6-5};
3006 let Inst{3-0} = src{3-0};
3010 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
3011 DPSoRegImmFrm, IIC_iMOVsr,
3012 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
3013 UnaryDP, Sched<[WriteALU]> {
3016 let Inst{15-12} = Rd;
3017 let Inst{19-16} = 0b0000;
3018 let Inst{11-5} = src{11-5};
3020 let Inst{3-0} = src{3-0};
3024 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3025 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
3026 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP,
3031 let Inst{15-12} = Rd;
3032 let Inst{19-16} = 0b0000;
3033 let Inst{11-0} = imm;
3036 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3037 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3039 "movw", "\t$Rd, $imm",
3040 [(set GPR:$Rd, imm0_65535:$imm)]>,
3041 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> {
3044 let Inst{15-12} = Rd;
3045 let Inst{11-0} = imm{11-0};
3046 let Inst{19-16} = imm{15-12};
3049 let DecoderMethod = "DecodeArmMOVTWInstruction";
3052 def : InstAlias<"mov${p} $Rd, $imm",
3053 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3056 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3057 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3060 let Constraints = "$src = $Rd" in {
3061 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3062 (ins GPR:$src, imm0_65535_expr:$imm),
3064 "movt", "\t$Rd, $imm",
3066 (or (and GPR:$src, 0xffff),
3067 lo16AllZero:$imm))]>, UnaryDP,
3068 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> {
3071 let Inst{15-12} = Rd;
3072 let Inst{11-0} = imm{11-0};
3073 let Inst{19-16} = imm{15-12};
3076 let DecoderMethod = "DecodeArmMOVTWInstruction";
3079 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3080 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3085 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3086 Requires<[IsARM, HasV6T2]>;
3088 let Uses = [CPSR] in
3089 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3090 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3091 Requires<[IsARM]>, Sched<[WriteALU]>;
3093 // These aren't really mov instructions, but we have to define them this way
3094 // due to flag operands.
3096 let Defs = [CPSR] in {
3097 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3098 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3099 Sched<[WriteALU]>, Requires<[IsARM]>;
3100 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3101 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3102 Sched<[WriteALU]>, Requires<[IsARM]>;
3105 //===----------------------------------------------------------------------===//
3106 // Extend Instructions.
3111 def SXTB : AI_ext_rrot<0b01101010,
3112 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3113 def SXTH : AI_ext_rrot<0b01101011,
3114 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3116 def SXTAB : AI_exta_rrot<0b01101010,
3117 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3118 def SXTAH : AI_exta_rrot<0b01101011,
3119 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3121 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3123 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3127 let AddedComplexity = 16 in {
3128 def UXTB : AI_ext_rrot<0b01101110,
3129 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3130 def UXTH : AI_ext_rrot<0b01101111,
3131 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3132 def UXTB16 : AI_ext_rrot<0b01101100,
3133 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3135 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3136 // The transformation should probably be done as a combiner action
3137 // instead so we can include a check for masking back in the upper
3138 // eight bits of the source into the lower eight bits of the result.
3139 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3140 // (UXTB16r_rot GPR:$Src, 3)>;
3141 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3142 (UXTB16 GPR:$Src, 1)>;
3144 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3145 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3146 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3147 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3150 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3151 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3154 def SBFX : I<(outs GPRnopc:$Rd),
3155 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3156 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3157 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3158 Requires<[IsARM, HasV6T2]> {
3163 let Inst{27-21} = 0b0111101;
3164 let Inst{6-4} = 0b101;
3165 let Inst{20-16} = width;
3166 let Inst{15-12} = Rd;
3167 let Inst{11-7} = lsb;
3171 def UBFX : I<(outs GPR:$Rd),
3172 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3173 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3174 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3175 Requires<[IsARM, HasV6T2]> {
3180 let Inst{27-21} = 0b0111111;
3181 let Inst{6-4} = 0b101;
3182 let Inst{20-16} = width;
3183 let Inst{15-12} = Rd;
3184 let Inst{11-7} = lsb;
3188 //===----------------------------------------------------------------------===//
3189 // Arithmetic Instructions.
3192 defm ADD : AsI1_bin_irs<0b0100, "add",
3193 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3194 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
3195 defm SUB : AsI1_bin_irs<0b0010, "sub",
3196 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3197 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3199 // ADD and SUB with 's' bit set.
3201 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3202 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3203 // AdjustInstrPostInstrSelection where we determine whether or not to
3204 // set the "s" bit based on CPSR liveness.
3206 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3207 // support for an optional CPSR definition that corresponds to the DAG
3208 // node's second value. We can then eliminate the implicit def of CPSR.
3209 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3210 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3211 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3212 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3214 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3215 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
3216 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3217 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3219 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3220 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3221 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3223 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3224 // CPSR and the implicit def of CPSR is not needed.
3225 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3226 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3228 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3229 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3231 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3232 // The assume-no-carry-in form uses the negation of the input since add/sub
3233 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3234 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3236 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3237 (SUBri GPR:$src, so_imm_neg:$imm)>;
3238 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3239 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3241 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3242 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3243 Requires<[IsARM, HasV6T2]>;
3244 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3245 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3246 Requires<[IsARM, HasV6T2]>;
3248 // The with-carry-in form matches bitwise not instead of the negation.
3249 // Effectively, the inverse interpretation of the carry flag already accounts
3250 // for part of the negation.
3251 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3252 (SBCri GPR:$src, so_imm_not:$imm)>;
3253 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
3254 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>;
3256 // Note: These are implemented in C++ code, because they have to generate
3257 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3259 // (mul X, 2^n+1) -> (add (X << n), X)
3260 // (mul X, 2^n-1) -> (rsb X, (X << n))
3262 // ARM Arithmetic Instruction
3263 // GPR:$dst = GPR:$a op GPR:$b
3264 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3265 list<dag> pattern = [],
3266 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3267 string asm = "\t$Rd, $Rn, $Rm">
3268 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>,
3269 Sched<[WriteALU, ReadALU, ReadALU]> {
3273 let Inst{27-20} = op27_20;
3274 let Inst{11-4} = op11_4;
3275 let Inst{19-16} = Rn;
3276 let Inst{15-12} = Rd;
3279 let Unpredictable{11-8} = 0b1111;
3282 // Saturating add/subtract
3284 let DecoderMethod = "DecodeQADDInstruction" in
3285 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3286 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3287 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3289 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3290 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3291 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3292 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3293 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3295 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3296 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3299 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3300 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3301 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3302 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3303 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3304 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3305 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3306 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3307 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3308 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3309 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3310 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3312 // Signed/Unsigned add/subtract
3314 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3315 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3316 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3317 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3318 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3319 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3320 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3321 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3322 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3323 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3324 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3325 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3327 // Signed/Unsigned halving add/subtract
3329 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3330 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3331 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3332 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3333 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3334 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3335 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3336 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3337 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3338 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3339 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3340 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3342 // Unsigned Sum of Absolute Differences [and Accumulate].
3344 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3345 MulFrm /* for convenience */, NoItinerary, "usad8",
3346 "\t$Rd, $Rn, $Rm", []>,
3347 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> {
3351 let Inst{27-20} = 0b01111000;
3352 let Inst{15-12} = 0b1111;
3353 let Inst{7-4} = 0b0001;
3354 let Inst{19-16} = Rd;
3355 let Inst{11-8} = Rm;
3358 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3359 MulFrm /* for convenience */, NoItinerary, "usada8",
3360 "\t$Rd, $Rn, $Rm, $Ra", []>,
3361 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{
3366 let Inst{27-20} = 0b01111000;
3367 let Inst{7-4} = 0b0001;
3368 let Inst{19-16} = Rd;
3369 let Inst{15-12} = Ra;
3370 let Inst{11-8} = Rm;
3374 // Signed/Unsigned saturate
3376 def SSAT : AI<(outs GPRnopc:$Rd),
3377 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3378 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3383 let Inst{27-21} = 0b0110101;
3384 let Inst{5-4} = 0b01;
3385 let Inst{20-16} = sat_imm;
3386 let Inst{15-12} = Rd;
3387 let Inst{11-7} = sh{4-0};
3388 let Inst{6} = sh{5};
3392 def SSAT16 : AI<(outs GPRnopc:$Rd),
3393 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3394 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3398 let Inst{27-20} = 0b01101010;
3399 let Inst{11-4} = 0b11110011;
3400 let Inst{15-12} = Rd;
3401 let Inst{19-16} = sat_imm;
3405 def USAT : AI<(outs GPRnopc:$Rd),
3406 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3407 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3412 let Inst{27-21} = 0b0110111;
3413 let Inst{5-4} = 0b01;
3414 let Inst{15-12} = Rd;
3415 let Inst{11-7} = sh{4-0};
3416 let Inst{6} = sh{5};
3417 let Inst{20-16} = sat_imm;
3421 def USAT16 : AI<(outs GPRnopc:$Rd),
3422 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3423 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3427 let Inst{27-20} = 0b01101110;
3428 let Inst{11-4} = 0b11110011;
3429 let Inst{15-12} = Rd;
3430 let Inst{19-16} = sat_imm;
3434 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3435 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3436 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3437 (USAT imm:$pos, GPRnopc:$a, 0)>;
3439 //===----------------------------------------------------------------------===//
3440 // Bitwise Instructions.
3443 defm AND : AsI1_bin_irs<0b0000, "and",
3444 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3445 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
3446 defm ORR : AsI1_bin_irs<0b1100, "orr",
3447 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3448 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
3449 defm EOR : AsI1_bin_irs<0b0001, "eor",
3450 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3451 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
3452 defm BIC : AsI1_bin_irs<0b1110, "bic",
3453 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3454 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
3456 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3457 // like in the actual instruction encoding. The complexity of mapping the mask
3458 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3459 // instruction description.
3460 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3461 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3462 "bfc", "\t$Rd, $imm", "$src = $Rd",
3463 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3464 Requires<[IsARM, HasV6T2]> {
3467 let Inst{27-21} = 0b0111110;
3468 let Inst{6-0} = 0b0011111;
3469 let Inst{15-12} = Rd;
3470 let Inst{11-7} = imm{4-0}; // lsb
3471 let Inst{20-16} = imm{9-5}; // msb
3474 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3475 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3476 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3477 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3478 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3479 bf_inv_mask_imm:$imm))]>,
3480 Requires<[IsARM, HasV6T2]> {
3484 let Inst{27-21} = 0b0111110;
3485 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3486 let Inst{15-12} = Rd;
3487 let Inst{11-7} = imm{4-0}; // lsb
3488 let Inst{20-16} = imm{9-5}; // width
3492 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3493 "mvn", "\t$Rd, $Rm",
3494 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
3498 let Inst{19-16} = 0b0000;
3499 let Inst{11-4} = 0b00000000;
3500 let Inst{15-12} = Rd;
3503 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3504 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3505 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
3510 let Inst{19-16} = 0b0000;
3511 let Inst{15-12} = Rd;
3512 let Inst{11-5} = shift{11-5};
3514 let Inst{3-0} = shift{3-0};
3516 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3517 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3518 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
3523 let Inst{19-16} = 0b0000;
3524 let Inst{15-12} = Rd;
3525 let Inst{11-8} = shift{11-8};
3527 let Inst{6-5} = shift{6-5};
3529 let Inst{3-0} = shift{3-0};
3531 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3532 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3533 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3534 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
3538 let Inst{19-16} = 0b0000;
3539 let Inst{15-12} = Rd;
3540 let Inst{11-0} = imm;
3543 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3544 (BICri GPR:$src, so_imm_not:$imm)>;
3546 //===----------------------------------------------------------------------===//
3547 // Multiply Instructions.
3549 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3550 string opc, string asm, list<dag> pattern>
3551 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3555 let Inst{19-16} = Rd;
3556 let Inst{11-8} = Rm;
3559 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3560 string opc, string asm, list<dag> pattern>
3561 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3566 let Inst{19-16} = RdHi;
3567 let Inst{15-12} = RdLo;
3568 let Inst{11-8} = Rm;
3571 class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3572 string opc, string asm, list<dag> pattern>
3573 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3578 let Inst{19-16} = RdHi;
3579 let Inst{15-12} = RdLo;
3580 let Inst{11-8} = Rm;
3584 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3585 // property. Remove them when it's possible to add those properties
3586 // on an individual MachineInstr, not just an instruction description.
3587 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3588 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3589 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3590 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3591 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3592 Requires<[IsARM, HasV6]> {
3593 let Inst{15-12} = 0b0000;
3594 let Unpredictable{15-12} = 0b1111;
3597 let Constraints = "@earlyclobber $Rd" in
3598 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3599 pred:$p, cc_out:$s),
3601 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3602 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3603 Requires<[IsARM, NoV6, UseMulOps]>;
3606 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3607 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3608 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3609 Requires<[IsARM, HasV6, UseMulOps]> {
3611 let Inst{15-12} = Ra;
3614 let Constraints = "@earlyclobber $Rd" in
3615 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3616 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3618 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3619 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3620 Requires<[IsARM, NoV6]>;
3622 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3623 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3624 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3625 Requires<[IsARM, HasV6T2, UseMulOps]> {
3630 let Inst{19-16} = Rd;
3631 let Inst{15-12} = Ra;
3632 let Inst{11-8} = Rm;
3636 // Extra precision multiplies with low / high results
3637 let neverHasSideEffects = 1 in {
3638 let isCommutable = 1 in {
3639 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3640 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3641 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3642 Requires<[IsARM, HasV6]>;
3644 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3645 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3646 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3647 Requires<[IsARM, HasV6]>;
3649 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3650 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3651 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3653 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3654 Requires<[IsARM, NoV6]>;
3656 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3657 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3659 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3660 Requires<[IsARM, NoV6]>;
3664 // Multiply + accumulate
3665 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3666 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3667 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3668 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3669 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3670 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3671 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3672 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3674 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3675 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3676 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3677 Requires<[IsARM, HasV6]> {
3682 let Inst{19-16} = RdHi;
3683 let Inst{15-12} = RdLo;
3684 let Inst{11-8} = Rm;
3688 let Constraints = "$RLo = $RdLo,$RHi = $RdHi" in {
3689 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3690 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3692 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3693 pred:$p, cc_out:$s)>,
3694 Requires<[IsARM, NoV6]>;
3695 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3696 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3698 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3699 pred:$p, cc_out:$s)>,
3700 Requires<[IsARM, NoV6]>;
3703 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3704 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3705 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3707 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3708 Requires<[IsARM, NoV6]>;
3711 } // neverHasSideEffects
3713 // Most significant word multiply
3714 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3715 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3716 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3717 Requires<[IsARM, HasV6]> {
3718 let Inst{15-12} = 0b1111;
3721 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3722 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3723 Requires<[IsARM, HasV6]> {
3724 let Inst{15-12} = 0b1111;
3727 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3728 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3729 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3730 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3731 Requires<[IsARM, HasV6, UseMulOps]>;
3733 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3734 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3735 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3736 Requires<[IsARM, HasV6]>;
3738 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3739 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3740 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3741 Requires<[IsARM, HasV6, UseMulOps]>;
3743 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3744 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3745 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3746 Requires<[IsARM, HasV6]>;
3748 multiclass AI_smul<string opc, PatFrag opnode> {
3749 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3750 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3751 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3752 (sext_inreg GPR:$Rm, i16)))]>,
3753 Requires<[IsARM, HasV5TE]>;
3755 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3756 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3757 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3758 (sra GPR:$Rm, (i32 16))))]>,
3759 Requires<[IsARM, HasV5TE]>;
3761 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3762 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3763 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3764 (sext_inreg GPR:$Rm, i16)))]>,
3765 Requires<[IsARM, HasV5TE]>;
3767 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3768 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3769 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3770 (sra GPR:$Rm, (i32 16))))]>,
3771 Requires<[IsARM, HasV5TE]>;
3773 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3774 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3775 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3776 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3777 Requires<[IsARM, HasV5TE]>;
3779 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3780 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3781 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3782 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3783 Requires<[IsARM, HasV5TE]>;
3787 multiclass AI_smla<string opc, PatFrag opnode> {
3788 let DecoderMethod = "DecodeSMLAInstruction" in {
3789 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3790 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3791 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3792 [(set GPRnopc:$Rd, (add GPR:$Ra,
3793 (opnode (sext_inreg GPRnopc:$Rn, i16),
3794 (sext_inreg GPRnopc:$Rm, i16))))]>,
3795 Requires<[IsARM, HasV5TE, UseMulOps]>;
3797 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3798 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3799 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3801 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3802 (sra GPRnopc:$Rm, (i32 16)))))]>,
3803 Requires<[IsARM, HasV5TE, UseMulOps]>;
3805 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3806 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3807 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3809 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3810 (sext_inreg GPRnopc:$Rm, i16))))]>,
3811 Requires<[IsARM, HasV5TE, UseMulOps]>;
3813 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3814 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3815 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3817 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3818 (sra GPRnopc:$Rm, (i32 16)))))]>,
3819 Requires<[IsARM, HasV5TE, UseMulOps]>;
3821 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3822 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3823 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3825 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3826 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3827 Requires<[IsARM, HasV5TE, UseMulOps]>;
3829 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3830 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3831 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3833 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3834 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3835 Requires<[IsARM, HasV5TE, UseMulOps]>;
3839 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3840 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3842 // Halfword multiply accumulate long: SMLAL<x><y>.
3843 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3844 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3845 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3846 Requires<[IsARM, HasV5TE]>;
3848 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3849 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3850 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3851 Requires<[IsARM, HasV5TE]>;
3853 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3854 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3855 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3856 Requires<[IsARM, HasV5TE]>;
3858 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3859 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3860 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3861 Requires<[IsARM, HasV5TE]>;
3863 // Helper class for AI_smld.
3864 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3865 InstrItinClass itin, string opc, string asm>
3866 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3869 let Inst{27-23} = 0b01110;
3870 let Inst{22} = long;
3871 let Inst{21-20} = 0b00;
3872 let Inst{11-8} = Rm;
3879 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3880 InstrItinClass itin, string opc, string asm>
3881 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3883 let Inst{15-12} = 0b1111;
3884 let Inst{19-16} = Rd;
3886 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3887 InstrItinClass itin, string opc, string asm>
3888 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3891 let Inst{19-16} = Rd;
3892 let Inst{15-12} = Ra;
3894 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3895 InstrItinClass itin, string opc, string asm>
3896 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3899 let Inst{19-16} = RdHi;
3900 let Inst{15-12} = RdLo;
3903 multiclass AI_smld<bit sub, string opc> {
3905 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3906 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3907 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3909 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3910 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3911 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3913 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3914 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3915 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3917 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3918 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3919 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3923 defm SMLA : AI_smld<0, "smla">;
3924 defm SMLS : AI_smld<1, "smls">;
3926 multiclass AI_sdml<bit sub, string opc> {
3928 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3929 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3930 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3931 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3934 defm SMUA : AI_sdml<0, "smua">;
3935 defm SMUS : AI_sdml<1, "smus">;
3937 //===----------------------------------------------------------------------===//
3938 // Division Instructions (ARMv7-A with virtualization extension)
3940 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
3941 "sdiv", "\t$Rd, $Rn, $Rm",
3942 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
3943 Requires<[IsARM, HasDivideInARM]>;
3945 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
3946 "udiv", "\t$Rd, $Rn, $Rm",
3947 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
3948 Requires<[IsARM, HasDivideInARM]>;
3950 //===----------------------------------------------------------------------===//
3951 // Misc. Arithmetic Instructions.
3954 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3955 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3956 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
3959 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3960 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3961 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3962 Requires<[IsARM, HasV6T2]>,
3965 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3966 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3967 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
3970 let AddedComplexity = 5 in
3971 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3972 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3973 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3974 Requires<[IsARM, HasV6]>,
3977 let AddedComplexity = 5 in
3978 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3979 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3980 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3981 Requires<[IsARM, HasV6]>,
3984 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3985 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3988 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
3989 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
3990 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3991 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
3992 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
3994 Requires<[IsARM, HasV6]>,
3995 Sched<[WriteALUsi, ReadALU]>;
3997 // Alternate cases for PKHBT where identities eliminate some nodes.
3998 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
3999 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
4000 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
4001 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
4003 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
4004 // will match the pattern below.
4005 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
4006 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
4007 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
4008 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
4009 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
4011 Requires<[IsARM, HasV6]>,
4012 Sched<[WriteALUsi, ReadALU]>;
4014 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
4015 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
4016 // We also can not replace a srl (17..31) by an arithmetic shift we would use in
4017 // pkhtb src1, src2, asr (17..31).
4018 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4019 (srl GPRnopc:$src2, imm16:$sh)),
4020 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>;
4021 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4022 (sra GPRnopc:$src2, imm16_31:$sh)),
4023 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
4024 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4025 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
4026 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
4028 //===----------------------------------------------------------------------===//
4029 // Comparison Instructions...
4032 defm CMP : AI1_cmp_irs<0b1010, "cmp",
4033 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
4034 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
4036 // ARMcmpZ can re-use the above instruction definitions.
4037 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
4038 (CMPri GPR:$src, so_imm:$imm)>;
4039 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
4040 (CMPrr GPR:$src, GPR:$rhs)>;
4041 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
4042 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
4043 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
4044 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
4046 // CMN register-integer
4047 let isCompare = 1, Defs = [CPSR] in {
4048 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, IIC_iCMPi,
4049 "cmn", "\t$Rn, $imm",
4050 [(ARMcmn GPR:$Rn, so_imm:$imm)]>,
4051 Sched<[WriteCMP, ReadALU]> {
4056 let Inst{19-16} = Rn;
4057 let Inst{15-12} = 0b0000;
4058 let Inst{11-0} = imm;
4060 let Unpredictable{15-12} = 0b1111;
4063 // CMN register-register/shift
4064 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4065 "cmn", "\t$Rn, $Rm",
4066 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4067 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
4070 let isCommutable = 1;
4073 let Inst{19-16} = Rn;
4074 let Inst{15-12} = 0b0000;
4075 let Inst{11-4} = 0b00000000;
4078 let Unpredictable{15-12} = 0b1111;
4081 def CMNzrsi : AI1<0b1011, (outs),
4082 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
4083 "cmn", "\t$Rn, $shift",
4084 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4085 GPR:$Rn, so_reg_imm:$shift)]>,
4086 Sched<[WriteCMPsi, ReadALU]> {
4091 let Inst{19-16} = Rn;
4092 let Inst{15-12} = 0b0000;
4093 let Inst{11-5} = shift{11-5};
4095 let Inst{3-0} = shift{3-0};
4097 let Unpredictable{15-12} = 0b1111;
4100 def CMNzrsr : AI1<0b1011, (outs),
4101 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
4102 "cmn", "\t$Rn, $shift",
4103 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4104 GPRnopc:$Rn, so_reg_reg:$shift)]>,
4105 Sched<[WriteCMPsr, ReadALU]> {
4110 let Inst{19-16} = Rn;
4111 let Inst{15-12} = 0b0000;
4112 let Inst{11-8} = shift{11-8};
4114 let Inst{6-5} = shift{6-5};
4116 let Inst{3-0} = shift{3-0};
4118 let Unpredictable{15-12} = 0b1111;
4123 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
4124 (CMNri GPR:$src, so_imm_neg:$imm)>;
4126 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
4127 (CMNri GPR:$src, so_imm_neg:$imm)>;
4129 // Note that TST/TEQ don't set all the same flags that CMP does!
4130 defm TST : AI1_cmp_irs<0b1000, "tst",
4131 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4132 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
4133 defm TEQ : AI1_cmp_irs<0b1001, "teq",
4134 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4135 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
4137 // Pseudo i64 compares for some floating point compares.
4138 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4140 def BCCi64 : PseudoInst<(outs),
4141 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4143 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>,
4146 def BCCZi64 : PseudoInst<(outs),
4147 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4148 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>,
4150 } // usesCustomInserter
4153 // Conditional moves
4154 let neverHasSideEffects = 1 in {
4156 let isCommutable = 1, isSelect = 1 in
4157 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd),
4158 (ins GPR:$false, GPR:$Rm, cmovpred:$p),
4160 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm,
4162 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4164 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4165 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p),
4168 (ARMcmov GPR:$false, so_reg_imm:$shift,
4170 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4171 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4172 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p),
4174 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4176 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4179 let isMoveImm = 1 in
4181 : ARMPseudoInst<(outs GPR:$Rd),
4182 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
4184 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm,
4186 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
4189 let isMoveImm = 1 in
4190 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4191 (ins GPR:$false, so_imm:$imm, cmovpred:$p),
4193 [(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm,
4195 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4197 // Two instruction predicate mov immediate.
4198 let isMoveImm = 1 in
4200 : ARMPseudoInst<(outs GPR:$Rd),
4201 (ins GPR:$false, i32imm:$src, cmovpred:$p),
4203 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src,
4205 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4207 let isMoveImm = 1 in
4208 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4209 (ins GPR:$false, so_imm:$imm, cmovpred:$p),
4211 [(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm,
4213 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4215 } // neverHasSideEffects
4218 //===----------------------------------------------------------------------===//
4219 // Atomic operations intrinsics
4222 def MemBarrierOptOperand : AsmOperandClass {
4223 let Name = "MemBarrierOpt";
4224 let ParserMethod = "parseMemBarrierOptOperand";
4226 def memb_opt : Operand<i32> {
4227 let PrintMethod = "printMemBOption";
4228 let ParserMatchClass = MemBarrierOptOperand;
4229 let DecoderMethod = "DecodeMemBarrierOption";
4232 def InstSyncBarrierOptOperand : AsmOperandClass {
4233 let Name = "InstSyncBarrierOpt";
4234 let ParserMethod = "parseInstSyncBarrierOptOperand";
4236 def instsyncb_opt : Operand<i32> {
4237 let PrintMethod = "printInstSyncBOption";
4238 let ParserMatchClass = InstSyncBarrierOptOperand;
4239 let DecoderMethod = "DecodeInstSyncBarrierOption";
4242 // memory barriers protect the atomic sequences
4243 let hasSideEffects = 1 in {
4244 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4245 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
4246 Requires<[IsARM, HasDB]> {
4248 let Inst{31-4} = 0xf57ff05;
4249 let Inst{3-0} = opt;
4253 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4254 "dsb", "\t$opt", []>,
4255 Requires<[IsARM, HasDB]> {
4257 let Inst{31-4} = 0xf57ff04;
4258 let Inst{3-0} = opt;
4261 // ISB has only full system option
4262 def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary,
4263 "isb", "\t$opt", []>,
4264 Requires<[IsARM, HasDB]> {
4266 let Inst{31-4} = 0xf57ff06;
4267 let Inst{3-0} = opt;
4270 // Pseudo instruction that combines movs + predicated rsbmi
4271 // to implement integer ABS
4272 let usesCustomInserter = 1, Defs = [CPSR] in
4273 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
4275 let usesCustomInserter = 1 in {
4276 let Defs = [CPSR] in {
4277 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
4278 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4279 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
4280 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
4281 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4282 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
4283 def ATOMIC_LOAD_AND_I8 : PseudoInst<
4284 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4285 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
4286 def ATOMIC_LOAD_OR_I8 : PseudoInst<
4287 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4288 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
4289 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4290 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4291 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
4292 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4293 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4294 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
4295 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4296 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4297 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4298 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4299 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4300 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4301 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4302 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4303 [(set GPR:$dst, (atomic_load_umin_8 GPR:$ptr, GPR:$val))]>;
4304 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4305 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4306 [(set GPR:$dst, (atomic_load_umax_8 GPR:$ptr, GPR:$val))]>;
4307 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4308 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4309 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
4310 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4311 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4312 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
4313 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4314 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4315 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
4316 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4317 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4318 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
4319 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4320 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4321 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
4322 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4323 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4324 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
4325 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4326 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4327 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4328 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4329 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4330 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4331 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4332 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4333 [(set GPR:$dst, (atomic_load_umin_16 GPR:$ptr, GPR:$val))]>;
4334 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4335 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4336 [(set GPR:$dst, (atomic_load_umax_16 GPR:$ptr, GPR:$val))]>;
4337 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4338 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4339 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
4340 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4341 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4342 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
4343 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4344 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4345 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
4346 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4347 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4348 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
4349 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4350 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4351 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
4352 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4353 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4354 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
4355 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4356 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4357 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4358 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4359 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4360 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4361 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4362 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4363 [(set GPR:$dst, (atomic_load_umin_32 GPR:$ptr, GPR:$val))]>;
4364 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4365 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4366 [(set GPR:$dst, (atomic_load_umax_32 GPR:$ptr, GPR:$val))]>;
4368 def ATOMIC_SWAP_I8 : PseudoInst<
4369 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4370 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
4371 def ATOMIC_SWAP_I16 : PseudoInst<
4372 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4373 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
4374 def ATOMIC_SWAP_I32 : PseudoInst<
4375 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4376 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
4378 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4379 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4380 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
4381 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4382 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4383 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
4384 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4385 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4386 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
4390 let usesCustomInserter = 1 in {
4391 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4392 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4394 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4397 def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4398 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4401 def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4402 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4405 def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4406 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4409 def strex_1 : PatFrag<(ops node:$val, node:$ptr),
4410 (int_arm_strex node:$val, node:$ptr), [{
4411 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4414 def strex_2 : PatFrag<(ops node:$val, node:$ptr),
4415 (int_arm_strex node:$val, node:$ptr), [{
4416 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4419 def strex_4 : PatFrag<(ops node:$val, node:$ptr),
4420 (int_arm_strex node:$val, node:$ptr), [{
4421 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4424 let mayLoad = 1 in {
4425 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4427 "ldrexb", "\t$Rt, $addr",
4428 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>;
4429 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4430 NoItinerary, "ldrexh", "\t$Rt, $addr",
4431 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>;
4432 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4433 NoItinerary, "ldrex", "\t$Rt, $addr",
4434 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>;
4435 let hasExtraDefRegAllocReq = 1 in
4436 def LDREXD: AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4437 NoItinerary, "ldrexd", "\t$Rt, $addr", []> {
4438 let DecoderMethod = "DecodeDoubleRegLoad";
4442 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4443 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4444 NoItinerary, "strexb", "\t$Rd, $Rt, $addr",
4445 [(set GPR:$Rd, (strex_1 GPR:$Rt, addr_offset_none:$addr))]>;
4446 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4447 NoItinerary, "strexh", "\t$Rd, $Rt, $addr",
4448 [(set GPR:$Rd, (strex_2 GPR:$Rt, addr_offset_none:$addr))]>;
4449 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4450 NoItinerary, "strex", "\t$Rd, $Rt, $addr",
4451 [(set GPR:$Rd, (strex_4 GPR:$Rt, addr_offset_none:$addr))]>;
4452 let hasExtraSrcRegAllocReq = 1 in
4453 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4454 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4455 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
4456 let DecoderMethod = "DecodeDoubleRegStore";
4461 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
4463 Requires<[IsARM, HasV7]> {
4464 let Inst{31-0} = 0b11110101011111111111000000011111;
4467 def : ARMPat<(and (ldrex_1 addr_offset_none:$addr), 0xff),
4468 (LDREXB addr_offset_none:$addr)>;
4469 def : ARMPat<(and (ldrex_2 addr_offset_none:$addr), 0xffff),
4470 (LDREXH addr_offset_none:$addr)>;
4471 def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4472 (STREXB GPR:$Rt, addr_offset_none:$addr)>;
4473 def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4474 (STREXH GPR:$Rt, addr_offset_none:$addr)>;
4476 // SWP/SWPB are deprecated in V6/V7.
4477 let mayLoad = 1, mayStore = 1 in {
4478 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4479 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>,
4481 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4482 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>,
4486 //===----------------------------------------------------------------------===//
4487 // Coprocessor Instructions.
4490 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4491 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4492 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4493 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4494 imm:$CRm, imm:$opc2)]> {
4502 let Inst{3-0} = CRm;
4504 let Inst{7-5} = opc2;
4505 let Inst{11-8} = cop;
4506 let Inst{15-12} = CRd;
4507 let Inst{19-16} = CRn;
4508 let Inst{23-20} = opc1;
4511 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4512 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4513 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4514 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4515 imm:$CRm, imm:$opc2)]> {
4516 let Inst{31-28} = 0b1111;
4524 let Inst{3-0} = CRm;
4526 let Inst{7-5} = opc2;
4527 let Inst{11-8} = cop;
4528 let Inst{15-12} = CRd;
4529 let Inst{19-16} = CRn;
4530 let Inst{23-20} = opc1;
4533 class ACI<dag oops, dag iops, string opc, string asm,
4534 IndexMode im = IndexModeNone>
4535 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4537 let Inst{27-25} = 0b110;
4539 class ACInoP<dag oops, dag iops, string opc, string asm,
4540 IndexMode im = IndexModeNone>
4541 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4543 let Inst{31-28} = 0b1111;
4544 let Inst{27-25} = 0b110;
4546 multiclass LdStCop<bit load, bit Dbit, string asm> {
4547 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4548 asm, "\t$cop, $CRd, $addr"> {
4552 let Inst{24} = 1; // P = 1
4553 let Inst{23} = addr{8};
4554 let Inst{22} = Dbit;
4555 let Inst{21} = 0; // W = 0
4556 let Inst{20} = load;
4557 let Inst{19-16} = addr{12-9};
4558 let Inst{15-12} = CRd;
4559 let Inst{11-8} = cop;
4560 let Inst{7-0} = addr{7-0};
4561 let DecoderMethod = "DecodeCopMemInstruction";
4563 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4564 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4568 let Inst{24} = 1; // P = 1
4569 let Inst{23} = addr{8};
4570 let Inst{22} = Dbit;
4571 let Inst{21} = 1; // W = 1
4572 let Inst{20} = load;
4573 let Inst{19-16} = addr{12-9};
4574 let Inst{15-12} = CRd;
4575 let Inst{11-8} = cop;
4576 let Inst{7-0} = addr{7-0};
4577 let DecoderMethod = "DecodeCopMemInstruction";
4579 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4580 postidx_imm8s4:$offset),
4581 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4586 let Inst{24} = 0; // P = 0
4587 let Inst{23} = offset{8};
4588 let Inst{22} = Dbit;
4589 let Inst{21} = 1; // W = 1
4590 let Inst{20} = load;
4591 let Inst{19-16} = addr;
4592 let Inst{15-12} = CRd;
4593 let Inst{11-8} = cop;
4594 let Inst{7-0} = offset{7-0};
4595 let DecoderMethod = "DecodeCopMemInstruction";
4597 def _OPTION : ACI<(outs),
4598 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4599 coproc_option_imm:$option),
4600 asm, "\t$cop, $CRd, $addr, $option"> {
4605 let Inst{24} = 0; // P = 0
4606 let Inst{23} = 1; // U = 1
4607 let Inst{22} = Dbit;
4608 let Inst{21} = 0; // W = 0
4609 let Inst{20} = load;
4610 let Inst{19-16} = addr;
4611 let Inst{15-12} = CRd;
4612 let Inst{11-8} = cop;
4613 let Inst{7-0} = option;
4614 let DecoderMethod = "DecodeCopMemInstruction";
4617 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4618 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4619 asm, "\t$cop, $CRd, $addr"> {
4623 let Inst{24} = 1; // P = 1
4624 let Inst{23} = addr{8};
4625 let Inst{22} = Dbit;
4626 let Inst{21} = 0; // W = 0
4627 let Inst{20} = load;
4628 let Inst{19-16} = addr{12-9};
4629 let Inst{15-12} = CRd;
4630 let Inst{11-8} = cop;
4631 let Inst{7-0} = addr{7-0};
4632 let DecoderMethod = "DecodeCopMemInstruction";
4634 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4635 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4639 let Inst{24} = 1; // P = 1
4640 let Inst{23} = addr{8};
4641 let Inst{22} = Dbit;
4642 let Inst{21} = 1; // W = 1
4643 let Inst{20} = load;
4644 let Inst{19-16} = addr{12-9};
4645 let Inst{15-12} = CRd;
4646 let Inst{11-8} = cop;
4647 let Inst{7-0} = addr{7-0};
4648 let DecoderMethod = "DecodeCopMemInstruction";
4650 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4651 postidx_imm8s4:$offset),
4652 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4657 let Inst{24} = 0; // P = 0
4658 let Inst{23} = offset{8};
4659 let Inst{22} = Dbit;
4660 let Inst{21} = 1; // W = 1
4661 let Inst{20} = load;
4662 let Inst{19-16} = addr;
4663 let Inst{15-12} = CRd;
4664 let Inst{11-8} = cop;
4665 let Inst{7-0} = offset{7-0};
4666 let DecoderMethod = "DecodeCopMemInstruction";
4668 def _OPTION : ACInoP<(outs),
4669 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4670 coproc_option_imm:$option),
4671 asm, "\t$cop, $CRd, $addr, $option"> {
4676 let Inst{24} = 0; // P = 0
4677 let Inst{23} = 1; // U = 1
4678 let Inst{22} = Dbit;
4679 let Inst{21} = 0; // W = 0
4680 let Inst{20} = load;
4681 let Inst{19-16} = addr;
4682 let Inst{15-12} = CRd;
4683 let Inst{11-8} = cop;
4684 let Inst{7-0} = option;
4685 let DecoderMethod = "DecodeCopMemInstruction";
4689 defm LDC : LdStCop <1, 0, "ldc">;
4690 defm LDCL : LdStCop <1, 1, "ldcl">;
4691 defm STC : LdStCop <0, 0, "stc">;
4692 defm STCL : LdStCop <0, 1, "stcl">;
4693 defm LDC2 : LdSt2Cop<1, 0, "ldc2">;
4694 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">;
4695 defm STC2 : LdSt2Cop<0, 0, "stc2">;
4696 defm STC2L : LdSt2Cop<0, 1, "stc2l">;
4698 //===----------------------------------------------------------------------===//
4699 // Move between coprocessor and ARM core register.
4702 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4704 : ABI<0b1110, oops, iops, NoItinerary, opc,
4705 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4706 let Inst{20} = direction;
4716 let Inst{15-12} = Rt;
4717 let Inst{11-8} = cop;
4718 let Inst{23-21} = opc1;
4719 let Inst{7-5} = opc2;
4720 let Inst{3-0} = CRm;
4721 let Inst{19-16} = CRn;
4724 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4726 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4727 c_imm:$CRm, imm0_7:$opc2),
4728 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4729 imm:$CRm, imm:$opc2)]>;
4730 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4731 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4732 c_imm:$CRm, 0, pred:$p)>;
4733 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4734 (outs GPRwithAPSR:$Rt),
4735 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4737 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4738 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4739 c_imm:$CRm, 0, pred:$p)>;
4741 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4742 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4744 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4746 : ABXI<0b1110, oops, iops, NoItinerary,
4747 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4748 let Inst{31-24} = 0b11111110;
4749 let Inst{20} = direction;
4759 let Inst{15-12} = Rt;
4760 let Inst{11-8} = cop;
4761 let Inst{23-21} = opc1;
4762 let Inst{7-5} = opc2;
4763 let Inst{3-0} = CRm;
4764 let Inst{19-16} = CRn;
4767 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4769 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4770 c_imm:$CRm, imm0_7:$opc2),
4771 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4772 imm:$CRm, imm:$opc2)]>;
4773 def : ARMInstAlias<"mcr2$ $cop, $opc1, $Rt, $CRn, $CRm",
4774 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4776 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4777 (outs GPRwithAPSR:$Rt),
4778 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4780 def : ARMInstAlias<"mrc2$ $cop, $opc1, $Rt, $CRn, $CRm",
4781 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4784 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4785 imm:$CRm, imm:$opc2),
4786 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4788 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4789 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4790 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm),
4791 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4792 let Inst{23-21} = 0b010;
4793 let Inst{20} = direction;
4801 let Inst{15-12} = Rt;
4802 let Inst{19-16} = Rt2;
4803 let Inst{11-8} = cop;
4804 let Inst{7-4} = opc1;
4805 let Inst{3-0} = CRm;
4808 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4809 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
4810 GPRnopc:$Rt2, imm:$CRm)]>;
4811 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4813 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
4814 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4815 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
4816 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
4817 let Inst{31-28} = 0b1111;
4818 let Inst{23-21} = 0b010;
4819 let Inst{20} = direction;
4827 let Inst{15-12} = Rt;
4828 let Inst{19-16} = Rt2;
4829 let Inst{11-8} = cop;
4830 let Inst{7-4} = opc1;
4831 let Inst{3-0} = CRm;
4833 let DecoderMethod = "DecodeMRRC2";
4836 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
4837 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
4838 GPRnopc:$Rt2, imm:$CRm)]>;
4839 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
4841 //===----------------------------------------------------------------------===//
4842 // Move between special register and ARM core register
4845 // Move to ARM core register from Special Register
4846 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4847 "mrs", "\t$Rd, apsr", []> {
4849 let Inst{23-16} = 0b00001111;
4850 let Unpredictable{19-17} = 0b111;
4852 let Inst{15-12} = Rd;
4854 let Inst{11-0} = 0b000000000000;
4855 let Unpredictable{11-0} = 0b110100001111;
4858 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
4861 // The MRSsys instruction is the MRS instruction from the ARM ARM,
4862 // section B9.3.9, with the R bit set to 1.
4863 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4864 "mrs", "\t$Rd, spsr", []> {
4866 let Inst{23-16} = 0b01001111;
4867 let Unpredictable{19-16} = 0b1111;
4869 let Inst{15-12} = Rd;
4871 let Inst{11-0} = 0b000000000000;
4872 let Unpredictable{11-0} = 0b110100001111;
4875 // Move from ARM core register to Special Register
4877 // No need to have both system and application versions, the encodings are the
4878 // same and the assembly parser has no way to distinguish between them. The mask
4879 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4880 // the mask with the fields to be accessed in the special register.
4881 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
4882 "msr", "\t$mask, $Rn", []> {
4887 let Inst{22} = mask{4}; // R bit
4888 let Inst{21-20} = 0b10;
4889 let Inst{19-16} = mask{3-0};
4890 let Inst{15-12} = 0b1111;
4891 let Inst{11-4} = 0b00000000;
4895 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
4896 "msr", "\t$mask, $a", []> {
4901 let Inst{22} = mask{4}; // R bit
4902 let Inst{21-20} = 0b10;
4903 let Inst{19-16} = mask{3-0};
4904 let Inst{15-12} = 0b1111;
4908 //===----------------------------------------------------------------------===//
4912 // __aeabi_read_tp preserves the registers r1-r3.
4913 // This is a pseudo inst so that we can get the encoding right,
4914 // complete with fixup for the aeabi_read_tp function.
4916 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
4917 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
4918 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>;
4921 //===----------------------------------------------------------------------===//
4922 // SJLJ Exception handling intrinsics
4923 // eh_sjlj_setjmp() is an instruction sequence to store the return
4924 // address and save #0 in R0 for the non-longjmp case.
4925 // Since by its nature we may be coming from some other function to get
4926 // here, and we're using the stack frame for the containing function to
4927 // save/restore registers, we can't keep anything live in regs across
4928 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4929 // when we get here from a longjmp(). We force everything out of registers
4930 // except for our own input by listing the relevant registers in Defs. By
4931 // doing so, we also cause the prologue/epilogue code to actively preserve
4932 // all of the callee-saved resgisters, which is exactly what we want.
4933 // A constant value is passed in $val, and we use the location as a scratch.
4935 // These are pseudo-instructions and are lowered to individual MC-insts, so
4936 // no encoding information is necessary.
4938 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4939 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4940 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4941 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4943 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4944 Requires<[IsARM, HasVFP2]>;
4948 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4949 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4950 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4952 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4953 Requires<[IsARM, NoVFP]>;
4956 // FIXME: Non-IOS version(s)
4957 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
4958 Defs = [ R7, LR, SP ] in {
4959 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
4961 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
4962 Requires<[IsARM, IsIOS]>;
4965 // eh.sjlj.dispatchsetup pseudo-instruction.
4966 // This pseudo is used for both ARM and Thumb. Any differences are handled when
4967 // the pseudo is expanded (which happens before any passes that need the
4968 // instruction size).
4969 let isBarrier = 1 in
4970 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
4973 //===----------------------------------------------------------------------===//
4974 // Non-Instruction Patterns
4977 // ARMv4 indirect branch using (MOVr PC, dst)
4978 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
4979 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
4980 4, IIC_Br, [(brind GPR:$dst)],
4981 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
4982 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
4984 // Large immediate handling.
4986 // 32-bit immediate using two piece so_imms or movw + movt.
4987 // This is a single pseudo instruction, the benefit is that it can be remat'd
4988 // as a single unit instead of having to handle reg inputs.
4989 // FIXME: Remove this when we can do generalized remat.
4990 let isReMaterializable = 1, isMoveImm = 1 in
4991 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
4992 [(set GPR:$dst, (arm_i32imm:$src))]>,
4995 // Pseudo instruction that combines movw + movt + add pc (if PIC).
4996 // It also makes it possible to rematerialize the instructions.
4997 // FIXME: Remove this when we can do generalized remat and when machine licm
4998 // can properly the instructions.
4999 let isReMaterializable = 1 in {
5000 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5002 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
5003 Requires<[IsARM, UseMovt]>;
5005 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5007 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
5008 Requires<[IsARM, UseMovt]>;
5010 let AddedComplexity = 10 in
5011 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5013 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5014 Requires<[IsARM, UseMovt]>;
5015 } // isReMaterializable
5017 // ConstantPool, GlobalAddress, and JumpTable
5018 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
5019 Requires<[IsARM, DontUseMovt]>;
5020 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
5021 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
5022 Requires<[IsARM, UseMovt]>;
5023 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
5024 (LEApcrelJT tjumptable:$dst, imm:$id)>;
5026 // TODO: add,sub,and, 3-instr forms?
5028 // Tail calls. These patterns also apply to Thumb mode.
5029 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
5030 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
5031 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
5034 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
5035 def : ARMPat<(ARMcall_nolink texternalsym:$func),
5036 (BMOVPCB_CALL texternalsym:$func)>;
5038 // zextload i1 -> zextload i8
5039 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5040 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5042 // extload -> zextload
5043 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5044 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5045 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5046 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5048 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
5050 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
5051 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
5054 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5055 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5056 (SMULBB GPR:$a, GPR:$b)>;
5057 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
5058 (SMULBB GPR:$a, GPR:$b)>;
5059 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5060 (sra GPR:$b, (i32 16))),
5061 (SMULBT GPR:$a, GPR:$b)>;
5062 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
5063 (SMULBT GPR:$a, GPR:$b)>;
5064 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
5065 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5066 (SMULTB GPR:$a, GPR:$b)>;
5067 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
5068 (SMULTB GPR:$a, GPR:$b)>;
5069 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
5071 (SMULWB GPR:$a, GPR:$b)>;
5072 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
5073 (SMULWB GPR:$a, GPR:$b)>;
5075 def : ARMV5MOPat<(add GPR:$acc,
5076 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5077 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5078 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5079 def : ARMV5MOPat<(add GPR:$acc,
5080 (mul sext_16_node:$a, sext_16_node:$b)),
5081 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5082 def : ARMV5MOPat<(add GPR:$acc,
5083 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5084 (sra GPR:$b, (i32 16)))),
5085 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5086 def : ARMV5MOPat<(add GPR:$acc,
5087 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
5088 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5089 def : ARMV5MOPat<(add GPR:$acc,
5090 (mul (sra GPR:$a, (i32 16)),
5091 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5092 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5093 def : ARMV5MOPat<(add GPR:$acc,
5094 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
5095 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5096 def : ARMV5MOPat<(add GPR:$acc,
5097 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
5099 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
5100 def : ARMV5MOPat<(add GPR:$acc,
5101 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
5102 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
5105 // Pre-v7 uses MCR for synchronization barriers.
5106 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
5107 Requires<[IsARM, HasV6]>;
5109 // SXT/UXT with no rotate
5110 let AddedComplexity = 16 in {
5111 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
5112 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
5113 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
5114 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
5115 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
5116 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
5117 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
5120 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
5121 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
5123 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
5124 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
5125 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
5126 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
5128 // Atomic load/store patterns
5129 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
5130 (LDRBrs ldst_so_reg:$src)>;
5131 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
5132 (LDRBi12 addrmode_imm12:$src)>;
5133 def : ARMPat<(atomic_load_16 addrmode3:$src),
5134 (LDRH addrmode3:$src)>;
5135 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
5136 (LDRrs ldst_so_reg:$src)>;
5137 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
5138 (LDRi12 addrmode_imm12:$src)>;
5139 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
5140 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
5141 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
5142 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
5143 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
5144 (STRH GPR:$val, addrmode3:$ptr)>;
5145 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
5146 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
5147 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
5148 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
5151 //===----------------------------------------------------------------------===//
5155 include "ARMInstrThumb.td"
5157 //===----------------------------------------------------------------------===//
5161 include "ARMInstrThumb2.td"
5163 //===----------------------------------------------------------------------===//
5164 // Floating Point Support
5167 include "ARMInstrVFP.td"
5169 //===----------------------------------------------------------------------===//
5170 // Advanced SIMD (NEON) Support
5173 include "ARMInstrNEON.td"
5175 //===----------------------------------------------------------------------===//
5176 // Assembler aliases
5180 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
5181 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
5182 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
5184 // System instructions
5185 def : MnemonicAlias<"swi", "svc">;
5187 // Load / Store Multiple
5188 def : MnemonicAlias<"ldmfd", "ldm">;
5189 def : MnemonicAlias<"ldmia", "ldm">;
5190 def : MnemonicAlias<"ldmea", "ldmdb">;
5191 def : MnemonicAlias<"stmfd", "stmdb">;
5192 def : MnemonicAlias<"stmia", "stm">;
5193 def : MnemonicAlias<"stmea", "stm">;
5195 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
5196 // shift amount is zero (i.e., unspecified).
5197 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5198 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5199 Requires<[IsARM, HasV6]>;
5200 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5201 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5202 Requires<[IsARM, HasV6]>;
5204 // PUSH/POP aliases for STM/LDM
5205 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
5206 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5208 // SSAT/USAT optional shift operand.
5209 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5210 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5211 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5212 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5215 // Extend instruction optional rotate operand.
5216 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5217 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5218 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5219 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5220 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5221 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5222 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5223 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5224 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5225 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5226 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5227 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5229 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5230 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5231 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5232 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5233 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5234 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5235 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5236 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5237 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5238 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5239 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5240 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5244 def : MnemonicAlias<"rfefa", "rfeda">;
5245 def : MnemonicAlias<"rfeea", "rfedb">;
5246 def : MnemonicAlias<"rfefd", "rfeia">;
5247 def : MnemonicAlias<"rfeed", "rfeib">;
5248 def : MnemonicAlias<"rfe", "rfeia">;
5251 def : MnemonicAlias<"srsfa", "srsib">;
5252 def : MnemonicAlias<"srsea", "srsia">;
5253 def : MnemonicAlias<"srsfd", "srsdb">;
5254 def : MnemonicAlias<"srsed", "srsda">;
5255 def : MnemonicAlias<"srs", "srsia">;
5258 def : MnemonicAlias<"qsubaddx", "qsax">;
5260 def : MnemonicAlias<"saddsubx", "sasx">;
5261 // SHASX == SHADDSUBX
5262 def : MnemonicAlias<"shaddsubx", "shasx">;
5263 // SHSAX == SHSUBADDX
5264 def : MnemonicAlias<"shsubaddx", "shsax">;
5266 def : MnemonicAlias<"ssubaddx", "ssax">;
5268 def : MnemonicAlias<"uaddsubx", "uasx">;
5269 // UHASX == UHADDSUBX
5270 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5271 // UHSAX == UHSUBADDX
5272 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5273 // UQASX == UQADDSUBX
5274 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5275 // UQSAX == UQSUBADDX
5276 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5278 def : MnemonicAlias<"usubaddx", "usax">;
5280 // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
5282 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5283 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5284 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5285 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5286 // Same for AND <--> BIC
5287 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5288 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5289 pred:$p, cc_out:$s)>;
5290 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5291 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5292 pred:$p, cc_out:$s)>;
5293 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5294 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5295 pred:$p, cc_out:$s)>;
5296 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5297 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5298 pred:$p, cc_out:$s)>;
5300 // Likewise, "add Rd, so_imm_neg" -> sub
5301 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5302 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5303 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5304 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5305 // Same for CMP <--> CMN via so_imm_neg
5306 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5307 (CMNri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5308 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5309 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5311 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5312 // LSR, ROR, and RRX instructions.
5313 // FIXME: We need C++ parser hooks to map the alias to the MOV
5314 // encoding. It seems we should be able to do that sort of thing
5315 // in tblgen, but it could get ugly.
5316 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5317 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5318 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5320 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5321 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5323 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5324 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5326 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5327 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5330 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5331 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
5332 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5333 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5334 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5336 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5337 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5339 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5340 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5342 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5343 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5347 // "neg" is and alias for "rsb rd, rn, #0"
5348 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5349 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5351 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5352 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5353 Requires<[IsARM, NoV6]>;
5355 // UMULL/SMULL are available on all arches, but the instruction definitions
5356 // need difference constraints pre-v6. Use these aliases for the assembly
5357 // parsing on pre-v6.
5358 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5359 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5360 Requires<[IsARM, NoV6]>;
5361 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5362 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5363 Requires<[IsARM, NoV6]>;
5365 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5367 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>;