1 //===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstrInfo.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMGenInstrInfo.inc"
18 #include "ARMMachineFunctionInfo.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/LiveVariables.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineJumpTableInfo.h"
24 #include "llvm/Target/TargetAsmInfo.h"
25 #include "llvm/Support/CommandLine.h"
29 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
30 cl::desc("Enable ARM 2-addr to 3-addr conv"));
33 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
34 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
38 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
42 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget &STI)
43 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)) {
46 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
47 : ARMBaseInstrInfo(STI), RI(*this, STI) {
50 /// Return true if the instruction is a register to register move and
51 /// leave the source and dest operands in the passed parameters.
53 bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
54 unsigned &SrcReg, unsigned &DstReg,
55 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
56 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
58 unsigned oc = MI.getOpcode();
66 SrcReg = MI.getOperand(1).getReg();
67 DstReg = MI.getOperand(0).getReg();
70 assert(MI.getDesc().getNumOperands() >= 2 &&
71 MI.getOperand(0).isReg() &&
72 MI.getOperand(1).isReg() &&
73 "Invalid ARM MOV instruction");
74 SrcReg = MI.getOperand(1).getReg();
75 DstReg = MI.getOperand(0).getReg();
80 unsigned ARMInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
81 int &FrameIndex) const {
82 switch (MI->getOpcode()) {
85 if (MI->getOperand(1).isFI() &&
86 MI->getOperand(2).isReg() &&
87 MI->getOperand(3).isImm() &&
88 MI->getOperand(2).getReg() == 0 &&
89 MI->getOperand(3).getImm() == 0) {
90 FrameIndex = MI->getOperand(1).getIndex();
91 return MI->getOperand(0).getReg();
96 if (MI->getOperand(1).isFI() &&
97 MI->getOperand(2).isImm() &&
98 MI->getOperand(2).getImm() == 0) {
99 FrameIndex = MI->getOperand(1).getIndex();
100 return MI->getOperand(0).getReg();
107 unsigned ARMInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
108 int &FrameIndex) const {
109 switch (MI->getOpcode()) {
112 if (MI->getOperand(1).isFI() &&
113 MI->getOperand(2).isReg() &&
114 MI->getOperand(3).isImm() &&
115 MI->getOperand(2).getReg() == 0 &&
116 MI->getOperand(3).getImm() == 0) {
117 FrameIndex = MI->getOperand(1).getIndex();
118 return MI->getOperand(0).getReg();
123 if (MI->getOperand(1).isFI() &&
124 MI->getOperand(2).isImm() &&
125 MI->getOperand(2).getImm() == 0) {
126 FrameIndex = MI->getOperand(1).getIndex();
127 return MI->getOperand(0).getReg();
135 void ARMInstrInfo::reMaterialize(MachineBasicBlock &MBB,
136 MachineBasicBlock::iterator I,
138 const MachineInstr *Orig) const {
139 DebugLoc dl = Orig->getDebugLoc();
140 if (Orig->getOpcode() == ARM::MOVi2pieces) {
141 RI.emitLoadConstPool(MBB, I, this, dl,
143 Orig->getOperand(1).getImm(),
144 (ARMCC::CondCodes)Orig->getOperand(2).getImm(),
145 Orig->getOperand(3).getReg());
149 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
150 MI->getOperand(0).setReg(DestReg);
154 static unsigned getUnindexedOpcode(unsigned Opc) {
167 case ARM::LDRSH_POST:
170 case ARM::LDRSB_POST:
186 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
187 MachineBasicBlock::iterator &MBBI,
188 LiveVariables *LV) const {
192 MachineInstr *MI = MBBI;
193 MachineFunction &MF = *MI->getParent()->getParent();
194 unsigned TSFlags = MI->getDesc().TSFlags;
196 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
197 default: return NULL;
198 case ARMII::IndexModePre:
201 case ARMII::IndexModePost:
205 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
207 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
211 MachineInstr *UpdateMI = NULL;
212 MachineInstr *MemMI = NULL;
213 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
214 const TargetInstrDesc &TID = MI->getDesc();
215 unsigned NumOps = TID.getNumOperands();
216 bool isLoad = !TID.mayStore();
217 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
218 const MachineOperand &Base = MI->getOperand(2);
219 const MachineOperand &Offset = MI->getOperand(NumOps-3);
220 unsigned WBReg = WB.getReg();
221 unsigned BaseReg = Base.getReg();
222 unsigned OffReg = Offset.getReg();
223 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
224 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
227 assert(false && "Unknown indexed op!");
229 case ARMII::AddrMode2: {
230 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
231 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
233 int SOImmVal = ARM_AM::getSOImmVal(Amt);
235 // Can't encode it in a so_imm operand. This transformation will
236 // add more than 1 instruction. Abandon!
238 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
239 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
240 .addReg(BaseReg).addImm(SOImmVal)
241 .addImm(Pred).addReg(0).addReg(0);
242 } else if (Amt != 0) {
243 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
244 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
245 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
246 get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
247 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
248 .addImm(Pred).addReg(0).addReg(0);
250 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
251 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
252 .addReg(BaseReg).addReg(OffReg)
253 .addImm(Pred).addReg(0).addReg(0);
256 case ARMII::AddrMode3 : {
257 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
258 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
260 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
261 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
262 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
263 .addReg(BaseReg).addImm(Amt)
264 .addImm(Pred).addReg(0).addReg(0);
266 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
267 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
268 .addReg(BaseReg).addReg(OffReg)
269 .addImm(Pred).addReg(0).addReg(0);
274 std::vector<MachineInstr*> NewMIs;
277 MemMI = BuildMI(MF, MI->getDebugLoc(),
278 get(MemOpc), MI->getOperand(0).getReg())
279 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
281 MemMI = BuildMI(MF, MI->getDebugLoc(),
282 get(MemOpc)).addReg(MI->getOperand(1).getReg())
283 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
284 NewMIs.push_back(MemMI);
285 NewMIs.push_back(UpdateMI);
288 MemMI = BuildMI(MF, MI->getDebugLoc(),
289 get(MemOpc), MI->getOperand(0).getReg())
290 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
292 MemMI = BuildMI(MF, MI->getDebugLoc(),
293 get(MemOpc)).addReg(MI->getOperand(1).getReg())
294 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
296 UpdateMI->getOperand(0).setIsDead();
297 NewMIs.push_back(UpdateMI);
298 NewMIs.push_back(MemMI);
301 // Transfer LiveVariables states, kill / dead info.
303 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
304 MachineOperand &MO = MI->getOperand(i);
305 if (MO.isReg() && MO.getReg() &&
306 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
307 unsigned Reg = MO.getReg();
309 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
311 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
313 LV->addVirtualRegisterDead(Reg, NewMI);
315 if (MO.isUse() && MO.isKill()) {
316 for (unsigned j = 0; j < 2; ++j) {
317 // Look at the two new MI's in reverse order.
318 MachineInstr *NewMI = NewMIs[j];
319 if (!NewMI->readsRegister(Reg))
321 LV->addVirtualRegisterKilled(Reg, NewMI);
322 if (VI.removeKill(MI))
323 VI.Kills.push_back(NewMI);
331 MFI->insert(MBBI, NewMIs[1]);
332 MFI->insert(MBBI, NewMIs[0]);
338 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
339 MachineBasicBlock *&FBB,
340 SmallVectorImpl<MachineOperand> &Cond,
341 bool AllowModify) const {
342 // If the block has no terminators, it just falls into the block after it.
343 MachineBasicBlock::iterator I = MBB.end();
344 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
347 // Get the last instruction in the block.
348 MachineInstr *LastInst = I;
350 // If there is only one terminator instruction, process it.
351 unsigned LastOpc = LastInst->getOpcode();
352 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
353 if (LastOpc == ARM::B || LastOpc == ARM::tB || LastOpc == ARM::t2B) {
354 TBB = LastInst->getOperand(0).getMBB();
357 if (LastOpc == ARM::Bcc || LastOpc == ARM::tBcc || LastOpc == ARM::t2Bcc) {
358 // Block ends with fall-through condbranch.
359 TBB = LastInst->getOperand(0).getMBB();
360 Cond.push_back(LastInst->getOperand(1));
361 Cond.push_back(LastInst->getOperand(2));
364 return true; // Can't handle indirect branch.
367 // Get the instruction before it if it is a terminator.
368 MachineInstr *SecondLastInst = I;
370 // If there are three terminators, we don't know what sort of block this is.
371 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
374 // If the block ends with ARM::B/ARM::tB/ARM::t2B and a
375 // ARM::Bcc/ARM::tBcc/ARM::t2Bcc, handle it.
376 unsigned SecondLastOpc = SecondLastInst->getOpcode();
377 if ((SecondLastOpc == ARM::Bcc && LastOpc == ARM::B) ||
378 (SecondLastOpc == ARM::tBcc && LastOpc == ARM::tB) ||
379 (SecondLastOpc == ARM::t2Bcc && LastOpc == ARM::t2B)) {
380 TBB = SecondLastInst->getOperand(0).getMBB();
381 Cond.push_back(SecondLastInst->getOperand(1));
382 Cond.push_back(SecondLastInst->getOperand(2));
383 FBB = LastInst->getOperand(0).getMBB();
387 // If the block ends with two unconditional branches, handle it. The second
388 // one is not executed, so remove it.
389 if ((SecondLastOpc == ARM::B || SecondLastOpc==ARM::tB ||
390 SecondLastOpc==ARM::t2B) &&
391 (LastOpc == ARM::B || LastOpc == ARM::tB || LastOpc == ARM::t2B)) {
392 TBB = SecondLastInst->getOperand(0).getMBB();
395 I->eraseFromParent();
399 // ...likewise if it ends with a branch table followed by an unconditional
400 // branch. The branch folder can create these, and we must get rid of them for
401 // correctness of Thumb constant islands.
402 if ((SecondLastOpc == ARM::BR_JTr || SecondLastOpc==ARM::BR_JTm ||
403 SecondLastOpc == ARM::BR_JTadd || SecondLastOpc==ARM::tBR_JTr ||
404 SecondLastOpc==ARM::t2BR_JTr) &&
405 (LastOpc == ARM::B || LastOpc == ARM::tB || LastOpc == ARM::t2B)) {
408 I->eraseFromParent();
412 // Otherwise, can't handle this.
417 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
418 MachineFunction &MF = *MBB.getParent();
419 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
420 int BOpc = AFI->isThumbFunction() ?
421 (AFI->isThumb2Function() ? ARM::t2B : ARM::tB) : ARM::B;
422 int BccOpc = AFI->isThumbFunction() ?
423 (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
425 MachineBasicBlock::iterator I = MBB.end();
426 if (I == MBB.begin()) return 0;
428 if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc)
431 // Remove the branch.
432 I->eraseFromParent();
436 if (I == MBB.begin()) return 1;
438 if (I->getOpcode() != BccOpc)
441 // Remove the branch.
442 I->eraseFromParent();
447 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
448 MachineBasicBlock *FBB,
449 const SmallVectorImpl<MachineOperand> &Cond) const {
450 // FIXME this should probably have a DebugLoc argument
451 DebugLoc dl = DebugLoc::getUnknownLoc();
452 MachineFunction &MF = *MBB.getParent();
453 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
454 int BOpc = AFI->isThumbFunction() ?
455 (AFI->isThumb2Function() ? ARM::t2B : ARM::tB) : ARM::B;
456 int BccOpc = AFI->isThumbFunction() ?
457 (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
459 // Shouldn't be a fall through.
460 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
461 assert((Cond.size() == 2 || Cond.size() == 0) &&
462 "ARM branch conditions have two components!");
465 if (Cond.empty()) // Unconditional branch?
466 BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB);
468 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
469 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
473 // Two-way conditional branch.
474 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
475 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
476 BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB);
480 bool ARMInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
481 MachineBasicBlock::iterator I,
482 unsigned DestReg, unsigned SrcReg,
483 const TargetRegisterClass *DestRC,
484 const TargetRegisterClass *SrcRC) const {
485 DebugLoc DL = DebugLoc::getUnknownLoc();
486 if (I != MBB.end()) DL = I->getDebugLoc();
488 if (DestRC != SrcRC) {
489 // Not yet supported!
493 if (DestRC == ARM::GPRRegisterClass)
494 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
496 else if (DestRC == ARM::SPRRegisterClass)
497 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg)
499 else if (DestRC == ARM::DPRRegisterClass)
500 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg)
502 else if (DestRC == ARM::QPRRegisterClass)
503 BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg);
511 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
512 unsigned SrcReg, bool isKill, int FI,
513 const TargetRegisterClass *RC) const {
514 DebugLoc DL = DebugLoc::getUnknownLoc();
515 if (I != MBB.end()) DL = I->getDebugLoc();
517 if (RC == ARM::GPRRegisterClass) {
518 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
519 .addReg(SrcReg, getKillRegState(isKill))
520 .addFrameIndex(FI).addReg(0).addImm(0));
521 } else if (RC == ARM::DPRRegisterClass) {
522 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD))
523 .addReg(SrcReg, getKillRegState(isKill))
524 .addFrameIndex(FI).addImm(0));
526 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
527 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS))
528 .addReg(SrcReg, getKillRegState(isKill))
529 .addFrameIndex(FI).addImm(0));
533 void ARMInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
535 SmallVectorImpl<MachineOperand> &Addr,
536 const TargetRegisterClass *RC,
537 SmallVectorImpl<MachineInstr*> &NewMIs) const{
538 DebugLoc DL = DebugLoc::getUnknownLoc();
540 if (RC == ARM::GPRRegisterClass) {
542 } else if (RC == ARM::DPRRegisterClass) {
545 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
549 MachineInstrBuilder MIB =
550 BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill));
551 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
552 MIB.addOperand(Addr[i]);
554 NewMIs.push_back(MIB);
559 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
560 unsigned DestReg, int FI,
561 const TargetRegisterClass *RC) const {
562 DebugLoc DL = DebugLoc::getUnknownLoc();
563 if (I != MBB.end()) DL = I->getDebugLoc();
565 if (RC == ARM::GPRRegisterClass) {
566 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
567 .addFrameIndex(FI).addReg(0).addImm(0));
568 } else if (RC == ARM::DPRRegisterClass) {
569 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg)
570 .addFrameIndex(FI).addImm(0));
572 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
573 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg)
574 .addFrameIndex(FI).addImm(0));
579 loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
580 SmallVectorImpl<MachineOperand> &Addr,
581 const TargetRegisterClass *RC,
582 SmallVectorImpl<MachineInstr*> &NewMIs) const {
583 DebugLoc DL = DebugLoc::getUnknownLoc();
585 if (RC == ARM::GPRRegisterClass) {
587 } else if (RC == ARM::DPRRegisterClass) {
590 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
594 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
595 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
596 MIB.addOperand(Addr[i]);
598 NewMIs.push_back(MIB);
602 MachineInstr *ARMInstrInfo::
603 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
604 const SmallVectorImpl<unsigned> &Ops, int FI) const {
605 if (Ops.size() != 1) return NULL;
607 unsigned OpNum = Ops[0];
608 unsigned Opc = MI->getOpcode();
609 MachineInstr *NewMI = NULL;
613 if (MI->getOperand(4).getReg() == ARM::CPSR)
614 // If it is updating CPSR, then it cannot be folded.
616 unsigned Pred = MI->getOperand(2).getImm();
617 unsigned PredReg = MI->getOperand(3).getReg();
618 if (OpNum == 0) { // move -> store
619 unsigned SrcReg = MI->getOperand(1).getReg();
620 bool isKill = MI->getOperand(1).isKill();
621 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
622 .addReg(SrcReg, getKillRegState(isKill))
623 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
624 } else { // move -> load
625 unsigned DstReg = MI->getOperand(0).getReg();
626 bool isDead = MI->getOperand(0).isDead();
627 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
628 .addReg(DstReg, RegState::Define | getDeadRegState(isDead))
629 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
634 unsigned Pred = MI->getOperand(2).getImm();
635 unsigned PredReg = MI->getOperand(3).getReg();
636 if (OpNum == 0) { // move -> store
637 unsigned SrcReg = MI->getOperand(1).getReg();
638 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS))
639 .addReg(SrcReg).addFrameIndex(FI)
640 .addImm(0).addImm(Pred).addReg(PredReg);
641 } else { // move -> load
642 unsigned DstReg = MI->getOperand(0).getReg();
643 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS), DstReg)
645 .addImm(0).addImm(Pred).addReg(PredReg);
650 unsigned Pred = MI->getOperand(2).getImm();
651 unsigned PredReg = MI->getOperand(3).getReg();
652 if (OpNum == 0) { // move -> store
653 unsigned SrcReg = MI->getOperand(1).getReg();
654 bool isKill = MI->getOperand(1).isKill();
655 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD))
656 .addReg(SrcReg, getKillRegState(isKill))
657 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
658 } else { // move -> load
659 unsigned DstReg = MI->getOperand(0).getReg();
660 bool isDead = MI->getOperand(0).isDead();
661 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD))
662 .addReg(DstReg, RegState::Define | getDeadRegState(isDead))
663 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
673 ARMInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
674 const SmallVectorImpl<unsigned> &Ops) const {
675 if (Ops.size() != 1) return false;
677 unsigned Opc = MI->getOpcode();
681 // If it is updating CPSR, then it cannot be folded.
682 return MI->getOperand(4).getReg() != ARM::CPSR;
689 return false; // FIXME
696 ARMBaseInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
697 if (MBB.empty()) return false;
699 switch (MBB.back().getOpcode()) {
700 case ARM::BX_RET: // Return.
703 case ARM::tBX_RET_vararg:
707 case ARM::t2B: // Uncond branch.
710 case ARM::BR_JTr: // Jumptable branch.
711 case ARM::BR_JTm: // Jumptable branch through mem.
712 case ARM::BR_JTadd: // Jumptable branch add to pc.
714 default: return false;
718 bool ARMBaseInstrInfo::
719 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
720 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
721 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
725 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
726 int PIdx = MI->findFirstPredOperandIdx();
727 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
730 bool ARMBaseInstrInfo::
731 PredicateInstruction(MachineInstr *MI,
732 const SmallVectorImpl<MachineOperand> &Pred) const {
733 unsigned Opc = MI->getOpcode();
734 if (Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B) {
735 MI->setDesc(get((Opc == ARM::B) ? ARM::Bcc :
736 ((Opc == ARM::tB) ? ARM::tBcc : ARM::t2Bcc)));
737 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
738 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
742 int PIdx = MI->findFirstPredOperandIdx();
744 MachineOperand &PMO = MI->getOperand(PIdx);
745 PMO.setImm(Pred[0].getImm());
746 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
752 bool ARMBaseInstrInfo::
753 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
754 const SmallVectorImpl<MachineOperand> &Pred2) const {
755 if (Pred1.size() > 2 || Pred2.size() > 2)
758 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
759 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
769 return CC2 == ARMCC::HI;
771 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
773 return CC2 == ARMCC::GT;
775 return CC2 == ARMCC::LT;
779 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
780 std::vector<MachineOperand> &Pred) const {
781 const TargetInstrDesc &TID = MI->getDesc();
782 if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
786 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
787 const MachineOperand &MO = MI->getOperand(i);
788 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
798 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
799 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
800 unsigned JTI) DISABLE_INLINE;
801 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
803 return JT[JTI].MBBs.size();
806 /// GetInstSize - Return the size of the specified MachineInstr.
808 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
809 const MachineBasicBlock &MBB = *MI->getParent();
810 const MachineFunction *MF = MBB.getParent();
811 const TargetAsmInfo *TAI = MF->getTarget().getTargetAsmInfo();
813 // Basic size info comes from the TSFlags field.
814 const TargetInstrDesc &TID = MI->getDesc();
815 unsigned TSFlags = TID.TSFlags;
817 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
819 // If this machine instr is an inline asm, measure it.
820 if (MI->getOpcode() == ARM::INLINEASM)
821 return TAI->getInlineAsmLength(MI->getOperand(0).getSymbolName());
824 switch (MI->getOpcode()) {
826 assert(0 && "Unknown or unset size field for instr!");
828 case TargetInstrInfo::IMPLICIT_DEF:
829 case TargetInstrInfo::DECLARE:
830 case TargetInstrInfo::DBG_LABEL:
831 case TargetInstrInfo::EH_LABEL:
836 case ARMII::Size8Bytes: return 8; // Arm instruction x 2.
837 case ARMII::Size4Bytes: return 4; // Arm instruction.
838 case ARMII::Size2Bytes: return 2; // Thumb instruction.
839 case ARMII::SizeSpecial: {
840 switch (MI->getOpcode()) {
841 case ARM::CONSTPOOL_ENTRY:
842 // If this machine instr is a constant pool entry, its size is recorded as
844 return MI->getOperand(2).getImm();
845 case ARM::Int_eh_sjlj_setjmp: return 12;
850 case ARM::t2BR_JTr: {
851 // These are jumptable branches, i.e. a branch followed by an inlined
852 // jumptable. The size is 4 + 4 * number of entries.
853 unsigned NumOps = TID.getNumOperands();
854 MachineOperand JTOP =
855 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
856 unsigned JTI = JTOP.getIndex();
857 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
858 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
859 assert(JTI < JT.size());
860 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
861 // 4 aligned. The assembler / linker may add 2 byte padding just before
862 // the JT entries. The size does not include this padding; the
863 // constant islands pass does separate bookkeeping for it.
864 // FIXME: If we know the size of the function is less than (1 << 16) *2
865 // bytes, we can use 16-bit entries instead. Then there won't be an
867 return getNumJTEntries(JT, JTI) * 4 +
868 ((MI->getOpcode()==ARM::tBR_JTr ||
869 MI->getOpcode()==ARM::t2BR_JTr) ? 2 : 4);
872 // Otherwise, pseudo-instruction sizes are zero.
877 return 0; // Not reached