1 //===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstrInfo.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMGenInstrInfo.inc"
18 #include "ARMMachineFunctionInfo.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/LiveVariables.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineJumpTableInfo.h"
24 #include "llvm/Target/TargetAsmInfo.h"
25 #include "llvm/Support/CommandLine.h"
28 static cl::opt<bool> EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
29 cl::desc("Enable ARM 2-addr to 3-addr conv"));
32 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
33 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
37 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
41 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
42 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
47 /// Return true if the instruction is a register to register move and
48 /// leave the source and dest operands in the passed parameters.
50 bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
51 unsigned &SrcReg, unsigned &DstReg,
52 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
53 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
55 unsigned oc = MI.getOpcode();
61 SrcReg = MI.getOperand(1).getReg();
62 DstReg = MI.getOperand(0).getReg();
66 assert(MI.getDesc().getNumOperands() >= 2 &&
67 MI.getOperand(0).isReg() &&
68 MI.getOperand(1).isReg() &&
69 "Invalid ARM MOV instruction");
70 SrcReg = MI.getOperand(1).getReg();
71 DstReg = MI.getOperand(0).getReg();
76 unsigned ARMInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
77 int &FrameIndex) const {
78 switch (MI->getOpcode()) {
81 if (MI->getOperand(1).isFI() &&
82 MI->getOperand(2).isReg() &&
83 MI->getOperand(3).isImm() &&
84 MI->getOperand(2).getReg() == 0 &&
85 MI->getOperand(3).getImm() == 0) {
86 FrameIndex = MI->getOperand(1).getIndex();
87 return MI->getOperand(0).getReg();
92 if (MI->getOperand(1).isFI() &&
93 MI->getOperand(2).isImm() &&
94 MI->getOperand(2).getImm() == 0) {
95 FrameIndex = MI->getOperand(1).getIndex();
96 return MI->getOperand(0).getReg();
100 if (MI->getOperand(1).isFI() &&
101 MI->getOperand(2).isImm() &&
102 MI->getOperand(2).getImm() == 0) {
103 FrameIndex = MI->getOperand(1).getIndex();
104 return MI->getOperand(0).getReg();
111 unsigned ARMInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
112 int &FrameIndex) const {
113 switch (MI->getOpcode()) {
116 if (MI->getOperand(1).isFI() &&
117 MI->getOperand(2).isReg() &&
118 MI->getOperand(3).isImm() &&
119 MI->getOperand(2).getReg() == 0 &&
120 MI->getOperand(3).getImm() == 0) {
121 FrameIndex = MI->getOperand(1).getIndex();
122 return MI->getOperand(0).getReg();
127 if (MI->getOperand(1).isFI() &&
128 MI->getOperand(2).isImm() &&
129 MI->getOperand(2).getImm() == 0) {
130 FrameIndex = MI->getOperand(1).getIndex();
131 return MI->getOperand(0).getReg();
135 if (MI->getOperand(1).isFI() &&
136 MI->getOperand(2).isImm() &&
137 MI->getOperand(2).getImm() == 0) {
138 FrameIndex = MI->getOperand(1).getIndex();
139 return MI->getOperand(0).getReg();
146 void ARMInstrInfo::reMaterialize(MachineBasicBlock &MBB,
147 MachineBasicBlock::iterator I,
149 const MachineInstr *Orig) const {
150 if (Orig->getOpcode() == ARM::MOVi2pieces) {
151 RI.emitLoadConstPool(MBB, I, DestReg, Orig->getOperand(1).getImm(),
152 Orig->getOperand(2).getImm(),
153 Orig->getOperand(3).getReg(), this, false);
157 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
158 MI->getOperand(0).setReg(DestReg);
162 static unsigned getUnindexedOpcode(unsigned Opc) {
175 case ARM::LDRSH_POST:
178 case ARM::LDRSB_POST:
194 ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
195 MachineBasicBlock::iterator &MBBI,
196 LiveVariables *LV) const {
200 MachineInstr *MI = MBBI;
201 MachineFunction &MF = *MI->getParent()->getParent();
202 unsigned TSFlags = MI->getDesc().TSFlags;
204 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
205 default: return NULL;
206 case ARMII::IndexModePre:
209 case ARMII::IndexModePost:
213 // Try spliting an indexed load / store to a un-indexed one plus an add/sub
215 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
219 MachineInstr *UpdateMI = NULL;
220 MachineInstr *MemMI = NULL;
221 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
222 const TargetInstrDesc &TID = MI->getDesc();
223 unsigned NumOps = TID.getNumOperands();
224 bool isLoad = !TID.mayStore();
225 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
226 const MachineOperand &Base = MI->getOperand(2);
227 const MachineOperand &Offset = MI->getOperand(NumOps-3);
228 unsigned WBReg = WB.getReg();
229 unsigned BaseReg = Base.getReg();
230 unsigned OffReg = Offset.getReg();
231 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
232 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
235 assert(false && "Unknown indexed op!");
237 case ARMII::AddrMode2: {
238 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
239 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
241 int SOImmVal = ARM_AM::getSOImmVal(Amt);
243 // Can't encode it in a so_imm operand. This transformation will
244 // add more than 1 instruction. Abandon!
246 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
247 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
248 .addReg(BaseReg).addImm(SOImmVal)
249 .addImm(Pred).addReg(0).addReg(0);
250 } else if (Amt != 0) {
251 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
252 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
253 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
254 get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
255 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
256 .addImm(Pred).addReg(0).addReg(0);
258 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
259 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
260 .addReg(BaseReg).addReg(OffReg)
261 .addImm(Pred).addReg(0).addReg(0);
264 case ARMII::AddrMode3 : {
265 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
266 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
268 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
269 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
270 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
271 .addReg(BaseReg).addImm(Amt)
272 .addImm(Pred).addReg(0).addReg(0);
274 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
275 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
276 .addReg(BaseReg).addReg(OffReg)
277 .addImm(Pred).addReg(0).addReg(0);
282 std::vector<MachineInstr*> NewMIs;
285 MemMI = BuildMI(MF, MI->getDebugLoc(),
286 get(MemOpc), MI->getOperand(0).getReg())
287 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
289 MemMI = BuildMI(MF, MI->getDebugLoc(),
290 get(MemOpc)).addReg(MI->getOperand(1).getReg())
291 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
292 NewMIs.push_back(MemMI);
293 NewMIs.push_back(UpdateMI);
296 MemMI = BuildMI(MF, MI->getDebugLoc(),
297 get(MemOpc), MI->getOperand(0).getReg())
298 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
300 MemMI = BuildMI(MF, MI->getDebugLoc(),
301 get(MemOpc)).addReg(MI->getOperand(1).getReg())
302 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
304 UpdateMI->getOperand(0).setIsDead();
305 NewMIs.push_back(UpdateMI);
306 NewMIs.push_back(MemMI);
309 // Transfer LiveVariables states, kill / dead info.
311 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
312 MachineOperand &MO = MI->getOperand(i);
313 if (MO.isReg() && MO.getReg() &&
314 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
315 unsigned Reg = MO.getReg();
317 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
319 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
321 LV->addVirtualRegisterDead(Reg, NewMI);
323 if (MO.isUse() && MO.isKill()) {
324 for (unsigned j = 0; j < 2; ++j) {
325 // Look at the two new MI's in reverse order.
326 MachineInstr *NewMI = NewMIs[j];
327 if (!NewMI->readsRegister(Reg))
329 LV->addVirtualRegisterKilled(Reg, NewMI);
330 if (VI.removeKill(MI))
331 VI.Kills.push_back(NewMI);
339 MFI->insert(MBBI, NewMIs[1]);
340 MFI->insert(MBBI, NewMIs[0]);
345 bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
346 MachineBasicBlock *&FBB,
347 SmallVectorImpl<MachineOperand> &Cond,
348 bool AllowModify) const {
349 // If the block has no terminators, it just falls into the block after it.
350 MachineBasicBlock::iterator I = MBB.end();
351 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
354 // Get the last instruction in the block.
355 MachineInstr *LastInst = I;
357 // If there is only one terminator instruction, process it.
358 unsigned LastOpc = LastInst->getOpcode();
359 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
360 if (LastOpc == ARM::B || LastOpc == ARM::tB) {
361 TBB = LastInst->getOperand(0).getMBB();
364 if (LastOpc == ARM::Bcc || LastOpc == ARM::tBcc) {
365 // Block ends with fall-through condbranch.
366 TBB = LastInst->getOperand(0).getMBB();
367 Cond.push_back(LastInst->getOperand(1));
368 Cond.push_back(LastInst->getOperand(2));
371 return true; // Can't handle indirect branch.
374 // Get the instruction before it if it is a terminator.
375 MachineInstr *SecondLastInst = I;
377 // If there are three terminators, we don't know what sort of block this is.
378 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
381 // If the block ends with ARM::B/ARM::tB and a ARM::Bcc/ARM::tBcc, handle it.
382 unsigned SecondLastOpc = SecondLastInst->getOpcode();
383 if ((SecondLastOpc == ARM::Bcc && LastOpc == ARM::B) ||
384 (SecondLastOpc == ARM::tBcc && LastOpc == ARM::tB)) {
385 TBB = SecondLastInst->getOperand(0).getMBB();
386 Cond.push_back(SecondLastInst->getOperand(1));
387 Cond.push_back(SecondLastInst->getOperand(2));
388 FBB = LastInst->getOperand(0).getMBB();
392 // If the block ends with two unconditional branches, handle it. The second
393 // one is not executed, so remove it.
394 if ((SecondLastOpc == ARM::B || SecondLastOpc==ARM::tB) &&
395 (LastOpc == ARM::B || LastOpc == ARM::tB)) {
396 TBB = SecondLastInst->getOperand(0).getMBB();
399 I->eraseFromParent();
403 // Likewise if it ends with a branch table followed by an unconditional branch.
404 // The branch folder can create these, and we must get rid of them for
405 // correctness of Thumb constant islands.
406 if ((SecondLastOpc == ARM::BR_JTr || SecondLastOpc==ARM::BR_JTm ||
407 SecondLastOpc == ARM::BR_JTadd || SecondLastOpc==ARM::tBR_JTr) &&
408 (LastOpc == ARM::B || LastOpc == ARM::tB)) {
411 I->eraseFromParent();
415 // Otherwise, can't handle this.
420 unsigned ARMInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
421 MachineFunction &MF = *MBB.getParent();
422 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
423 int BOpc = AFI->isThumbFunction() ? ARM::tB : ARM::B;
424 int BccOpc = AFI->isThumbFunction() ? ARM::tBcc : ARM::Bcc;
426 MachineBasicBlock::iterator I = MBB.end();
427 if (I == MBB.begin()) return 0;
429 if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc)
432 // Remove the branch.
433 I->eraseFromParent();
437 if (I == MBB.begin()) return 1;
439 if (I->getOpcode() != BccOpc)
442 // Remove the branch.
443 I->eraseFromParent();
447 unsigned ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
448 MachineBasicBlock *FBB,
449 const SmallVectorImpl<MachineOperand> &Cond) const {
450 MachineFunction &MF = *MBB.getParent();
451 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
452 int BOpc = AFI->isThumbFunction() ? ARM::tB : ARM::B;
453 int BccOpc = AFI->isThumbFunction() ? ARM::tBcc : ARM::Bcc;
455 // Shouldn't be a fall through.
456 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
457 assert((Cond.size() == 2 || Cond.size() == 0) &&
458 "ARM branch conditions have two components!");
461 if (Cond.empty()) // Unconditional branch?
462 BuildMI(&MBB, get(BOpc)).addMBB(TBB);
464 BuildMI(&MBB, get(BccOpc)).addMBB(TBB)
465 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
469 // Two-way conditional branch.
470 BuildMI(&MBB, get(BccOpc)).addMBB(TBB)
471 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
472 BuildMI(&MBB, get(BOpc)).addMBB(FBB);
476 bool ARMInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
477 MachineBasicBlock::iterator I,
478 unsigned DestReg, unsigned SrcReg,
479 const TargetRegisterClass *DestRC,
480 const TargetRegisterClass *SrcRC) const {
481 if (DestRC != SrcRC) {
482 // Not yet supported!
486 DebugLoc DL = DebugLoc::getUnknownLoc();
487 if (I != MBB.end()) DL = I->getDebugLoc();
489 if (DestRC == ARM::GPRRegisterClass) {
490 MachineFunction &MF = *MBB.getParent();
491 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
492 if (AFI->isThumbFunction())
493 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
495 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
497 } else if (DestRC == ARM::SPRRegisterClass)
498 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg)
500 else if (DestRC == ARM::DPRRegisterClass)
501 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg)
509 static const MachineInstrBuilder &ARMInstrAddOperand(MachineInstrBuilder &MIB,
510 MachineOperand &MO) {
512 MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
514 MIB = MIB.addImm(MO.getImm());
516 MIB = MIB.addFrameIndex(MO.getIndex());
518 assert(0 && "Unknown operand for ARMInstrAddOperand!");
524 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
525 unsigned SrcReg, bool isKill, int FI,
526 const TargetRegisterClass *RC) const {
527 DebugLoc DL = DebugLoc::getUnknownLoc();
528 if (I != MBB.end()) DL = I->getDebugLoc();
530 if (RC == ARM::GPRRegisterClass) {
531 MachineFunction &MF = *MBB.getParent();
532 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
533 if (AFI->isThumbFunction())
534 BuildMI(MBB, I, DL, get(ARM::tSpill))
535 .addReg(SrcReg, false, false, isKill)
536 .addFrameIndex(FI).addImm(0);
538 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
539 .addReg(SrcReg, false, false, isKill)
540 .addFrameIndex(FI).addReg(0).addImm(0));
541 } else if (RC == ARM::DPRRegisterClass) {
542 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD))
543 .addReg(SrcReg, false, false, isKill)
544 .addFrameIndex(FI).addImm(0));
546 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
547 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS))
548 .addReg(SrcReg, false, false, isKill)
549 .addFrameIndex(FI).addImm(0));
553 void ARMInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
555 SmallVectorImpl<MachineOperand> &Addr,
556 const TargetRegisterClass *RC,
557 SmallVectorImpl<MachineInstr*> &NewMIs) const{
558 DebugLoc DL = DebugLoc::getUnknownLoc();
560 if (RC == ARM::GPRRegisterClass) {
561 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
562 if (AFI->isThumbFunction()) {
563 Opc = Addr[0].isFI() ? ARM::tSpill : ARM::tSTR;
564 MachineInstrBuilder MIB =
565 BuildMI(MF, DL, get(Opc)).addReg(SrcReg, false, false, isKill);
566 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
567 MIB = ARMInstrAddOperand(MIB, Addr[i]);
568 NewMIs.push_back(MIB);
572 } else if (RC == ARM::DPRRegisterClass) {
575 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
579 MachineInstrBuilder MIB =
580 BuildMI(MF, DL, get(Opc)).addReg(SrcReg, false, false, isKill);
581 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
582 MIB = ARMInstrAddOperand(MIB, Addr[i]);
584 NewMIs.push_back(MIB);
589 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
590 unsigned DestReg, int FI,
591 const TargetRegisterClass *RC) const {
592 DebugLoc DL = DebugLoc::getUnknownLoc();
593 if (I != MBB.end()) DL = I->getDebugLoc();
595 if (RC == ARM::GPRRegisterClass) {
596 MachineFunction &MF = *MBB.getParent();
597 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
598 if (AFI->isThumbFunction())
599 BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
600 .addFrameIndex(FI).addImm(0);
602 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
603 .addFrameIndex(FI).addReg(0).addImm(0));
604 } else if (RC == ARM::DPRRegisterClass) {
605 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg)
606 .addFrameIndex(FI).addImm(0));
608 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
609 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg)
610 .addFrameIndex(FI).addImm(0));
614 void ARMInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
615 SmallVectorImpl<MachineOperand> &Addr,
616 const TargetRegisterClass *RC,
617 SmallVectorImpl<MachineInstr*> &NewMIs) const {
618 DebugLoc DL = DebugLoc::getUnknownLoc();
620 if (RC == ARM::GPRRegisterClass) {
621 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
622 if (AFI->isThumbFunction()) {
623 Opc = Addr[0].isFI() ? ARM::tRestore : ARM::tLDR;
624 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
625 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
626 MIB = ARMInstrAddOperand(MIB, Addr[i]);
627 NewMIs.push_back(MIB);
631 } else if (RC == ARM::DPRRegisterClass) {
634 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
638 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
639 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
640 MIB = ARMInstrAddOperand(MIB, Addr[i]);
642 NewMIs.push_back(MIB);
646 bool ARMInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
647 MachineBasicBlock::iterator MI,
648 const std::vector<CalleeSavedInfo> &CSI) const {
649 MachineFunction &MF = *MBB.getParent();
650 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
651 if (!AFI->isThumbFunction() || CSI.empty())
654 DebugLoc DL = DebugLoc::getUnknownLoc();
655 if (MI != MBB.end()) DL = MI->getDebugLoc();
657 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
658 for (unsigned i = CSI.size(); i != 0; --i) {
659 unsigned Reg = CSI[i-1].getReg();
660 // Add the callee-saved register as live-in. It's killed at the spill.
662 MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/);
667 bool ARMInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
668 MachineBasicBlock::iterator MI,
669 const std::vector<CalleeSavedInfo> &CSI) const {
670 MachineFunction &MF = *MBB.getParent();
671 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
672 if (!AFI->isThumbFunction() || CSI.empty())
675 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
676 MachineInstr *PopMI = MF.CreateMachineInstr(get(ARM::tPOP),MI->getDebugLoc());
677 MBB.insert(MI, PopMI);
678 for (unsigned i = CSI.size(); i != 0; --i) {
679 unsigned Reg = CSI[i-1].getReg();
680 if (Reg == ARM::LR) {
681 // Special epilogue for vararg functions. See emitEpilogue
685 PopMI->setDesc(get(ARM::tPOP_RET));
688 PopMI->addOperand(MachineOperand::CreateReg(Reg, true));
693 MachineInstr *ARMInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
695 const SmallVectorImpl<unsigned> &Ops,
697 if (Ops.size() != 1) return NULL;
699 unsigned OpNum = Ops[0];
700 unsigned Opc = MI->getOpcode();
701 MachineInstr *NewMI = NULL;
705 if (MI->getOperand(4).getReg() == ARM::CPSR)
706 // If it is updating CPSR, then it cannot be foled.
708 unsigned Pred = MI->getOperand(2).getImm();
709 unsigned PredReg = MI->getOperand(3).getReg();
710 if (OpNum == 0) { // move -> store
711 unsigned SrcReg = MI->getOperand(1).getReg();
712 bool isKill = MI->getOperand(1).isKill();
713 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
714 .addReg(SrcReg, false, false, isKill)
715 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
716 } else { // move -> load
717 unsigned DstReg = MI->getOperand(0).getReg();
718 bool isDead = MI->getOperand(0).isDead();
719 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
720 .addReg(DstReg, true, false, false, isDead)
721 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
726 if (OpNum == 0) { // move -> store
727 unsigned SrcReg = MI->getOperand(1).getReg();
728 bool isKill = MI->getOperand(1).isKill();
729 if (RI.isPhysicalRegister(SrcReg) && !RI.isLowRegister(SrcReg))
730 // tSpill cannot take a high register operand.
732 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
733 .addReg(SrcReg, false, false, isKill)
734 .addFrameIndex(FI).addImm(0);
735 } else { // move -> load
736 unsigned DstReg = MI->getOperand(0).getReg();
737 if (RI.isPhysicalRegister(DstReg) && !RI.isLowRegister(DstReg))
738 // tRestore cannot target a high register operand.
740 bool isDead = MI->getOperand(0).isDead();
741 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
742 .addReg(DstReg, true, false, false, isDead)
743 .addFrameIndex(FI).addImm(0);
748 unsigned Pred = MI->getOperand(2).getImm();
749 unsigned PredReg = MI->getOperand(3).getReg();
750 if (OpNum == 0) { // move -> store
751 unsigned SrcReg = MI->getOperand(1).getReg();
752 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS))
753 .addReg(SrcReg).addFrameIndex(FI)
754 .addImm(0).addImm(Pred).addReg(PredReg);
755 } else { // move -> load
756 unsigned DstReg = MI->getOperand(0).getReg();
757 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS), DstReg)
759 .addImm(0).addImm(Pred).addReg(PredReg);
764 unsigned Pred = MI->getOperand(2).getImm();
765 unsigned PredReg = MI->getOperand(3).getReg();
766 if (OpNum == 0) { // move -> store
767 unsigned SrcReg = MI->getOperand(1).getReg();
768 bool isKill = MI->getOperand(1).isKill();
769 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD))
770 .addReg(SrcReg, false, false, isKill)
771 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
772 } else { // move -> load
773 unsigned DstReg = MI->getOperand(0).getReg();
774 bool isDead = MI->getOperand(0).isDead();
775 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD))
776 .addReg(DstReg, true, false, false, isDead)
777 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
786 bool ARMInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
787 const SmallVectorImpl<unsigned> &Ops) const {
788 if (Ops.size() != 1) return false;
790 unsigned OpNum = Ops[0];
791 unsigned Opc = MI->getOpcode();
795 // If it is updating CPSR, then it cannot be foled.
796 return MI->getOperand(4).getReg() != ARM::CPSR;
798 if (OpNum == 0) { // move -> store
799 unsigned SrcReg = MI->getOperand(1).getReg();
800 if (RI.isPhysicalRegister(SrcReg) && !RI.isLowRegister(SrcReg))
801 // tSpill cannot take a high register operand.
803 } else { // move -> load
804 unsigned DstReg = MI->getOperand(0).getReg();
805 if (RI.isPhysicalRegister(DstReg) && !RI.isLowRegister(DstReg))
806 // tRestore cannot target a high register operand.
819 bool ARMInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
820 if (MBB.empty()) return false;
822 switch (MBB.back().getOpcode()) {
823 case ARM::BX_RET: // Return.
826 case ARM::tBX_RET_vararg:
829 case ARM::tB: // Uncond branch.
831 case ARM::BR_JTr: // Jumptable branch.
832 case ARM::BR_JTm: // Jumptable branch through mem.
833 case ARM::BR_JTadd: // Jumptable branch add to pc.
835 default: return false;
840 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
841 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
842 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
846 bool ARMInstrInfo::isPredicated(const MachineInstr *MI) const {
847 int PIdx = MI->findFirstPredOperandIdx();
848 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
851 bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
852 const SmallVectorImpl<MachineOperand> &Pred) const {
853 unsigned Opc = MI->getOpcode();
854 if (Opc == ARM::B || Opc == ARM::tB) {
855 MI->setDesc(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc));
856 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
857 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
861 int PIdx = MI->findFirstPredOperandIdx();
863 MachineOperand &PMO = MI->getOperand(PIdx);
864 PMO.setImm(Pred[0].getImm());
865 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
872 ARMInstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
873 const SmallVectorImpl<MachineOperand> &Pred2) const{
874 if (Pred1.size() > 2 || Pred2.size() > 2)
877 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
878 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
888 return CC2 == ARMCC::HI;
890 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
892 return CC2 == ARMCC::GT;
894 return CC2 == ARMCC::LT;
898 bool ARMInstrInfo::DefinesPredicate(MachineInstr *MI,
899 std::vector<MachineOperand> &Pred) const {
900 const TargetInstrDesc &TID = MI->getDesc();
901 if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
905 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
906 const MachineOperand &MO = MI->getOperand(i);
907 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
917 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
918 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
919 unsigned JTI) DISABLE_INLINE;
920 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
922 return JT[JTI].MBBs.size();
925 /// GetInstSize - Return the size of the specified MachineInstr.
927 unsigned ARMInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
928 const MachineBasicBlock &MBB = *MI->getParent();
929 const MachineFunction *MF = MBB.getParent();
930 const TargetAsmInfo *TAI = MF->getTarget().getTargetAsmInfo();
932 // Basic size info comes from the TSFlags field.
933 const TargetInstrDesc &TID = MI->getDesc();
934 unsigned TSFlags = TID.TSFlags;
936 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
938 // If this machine instr is an inline asm, measure it.
939 if (MI->getOpcode() == ARM::INLINEASM)
940 return TAI->getInlineAsmLength(MI->getOperand(0).getSymbolName());
943 switch (MI->getOpcode()) {
945 assert(0 && "Unknown or unset size field for instr!");
947 case TargetInstrInfo::IMPLICIT_DEF:
948 case TargetInstrInfo::DECLARE:
949 case TargetInstrInfo::DBG_LABEL:
950 case TargetInstrInfo::EH_LABEL:
955 case ARMII::Size8Bytes: return 8; // Arm instruction x 2.
956 case ARMII::Size4Bytes: return 4; // Arm instruction.
957 case ARMII::Size2Bytes: return 2; // Thumb instruction.
958 case ARMII::SizeSpecial: {
959 switch (MI->getOpcode()) {
960 case ARM::CONSTPOOL_ENTRY:
961 // If this machine instr is a constant pool entry, its size is recorded as
963 return MI->getOperand(2).getImm();
968 // These are jumptable branches, i.e. a branch followed by an inlined
969 // jumptable. The size is 4 + 4 * number of entries.
970 unsigned NumOps = TID.getNumOperands();
971 MachineOperand JTOP =
972 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
973 unsigned JTI = JTOP.getIndex();
974 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
975 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
976 assert(JTI < JT.size());
977 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
978 // 4 aligned. The assembler / linker may add 2 byte padding just before
979 // the JT entries. The size does not include this padding; the
980 // constant islands pass does separate bookkeeping for it.
981 // FIXME: If we know the size of the function is less than (1 << 16) *2
982 // bytes, we can use 16-bit entries instead. Then there won't be an
984 return getNumJTEntries(JT, JTI) * 4 +
985 (MI->getOpcode()==ARM::tBR_JTr ? 2 : 4);
988 // Otherwise, pseudo-instruction sizes are zero.
993 return 0; // Not reached