1 //===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<5> val> {
22 def Pseudo : Format<1>;
23 def MulFrm : Format<2>;
24 def MulSMLAW : Format<3>;
25 def MulSMULW : Format<4>;
26 def MulSMLA : Format<5>;
27 def MulSMUL : Format<6>;
28 def Branch : Format<7>;
29 def BranchMisc : Format<8>;
31 def DPRdIm : Format<9>;
32 def DPRdReg : Format<10>;
33 def DPRdSoReg : Format<11>;
34 def DPRdMisc : Format<12>;
35 def DPRnIm : Format<13>;
36 def DPRnReg : Format<14>;
37 def DPRnSoReg : Format<15>;
38 def DPRIm : Format<16>;
39 def DPRReg : Format<17>;
40 def DPRSoReg : Format<18>;
41 def DPRImS : Format<19>;
42 def DPRRegS : Format<20>;
43 def DPRSoRegS : Format<21>;
45 def LdFrm : Format<22>;
46 def StFrm : Format<23>;
48 def ArithMisc : Format<24>;
49 def ThumbFrm : Format<25>;
50 def VFPFrm : Format<26>;
53 //===----------------------------------------------------------------------===//
55 // ARM Instruction templates.
58 class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im,
59 Format f, string cstr>
63 let Namespace = "ARM";
65 bits<4> Opcode = opcod;
67 bits<4> AddrModeBits = AM.Value;
70 bits<3> SizeFlag = SZ.Value;
73 bits<2> IndexModeBits = IM.Value;
76 bits<5> Form = F.Value;
78 let Constraints = cstr;
81 class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern>
82 : InstARM<0, AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> {
83 let OutOperandList = oops;
84 let InOperandList = iops;
86 let Pattern = pattern;
89 // Almost all ARM instructions are predicable.
90 class I<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
91 IndexMode im, Format f, string opc, string asm, string cstr,
93 : InstARM<opcod, am, sz, im, f, cstr> {
94 let OutOperandList = oops;
95 let InOperandList = !con(iops, (ops pred:$p));
96 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
97 let Pattern = pattern;
98 list<Predicate> Predicates = [IsARM];
101 // Same as I except it can optionally modify CPSR. Note it's modeled as
102 // an input operand since by default it's a zero register. It will
103 // become an implicit def once it's "flipped".
104 class sI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
105 IndexMode im, Format f, string opc, string asm, string cstr,
107 : InstARM<opcod, am, sz, im, f, cstr> {
108 let OutOperandList = oops;
109 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
110 let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm));
111 let Pattern = pattern;
112 list<Predicate> Predicates = [IsARM];
116 class XI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
117 IndexMode im, Format f, string asm, string cstr, list<dag> pattern>
118 : InstARM<opcod, am, sz, im, f, cstr> {
119 let OutOperandList = oops;
120 let InOperandList = iops;
122 let Pattern = pattern;
123 list<Predicate> Predicates = [IsARM];
126 class AI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
127 string asm, list<dag> pattern>
128 : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
130 class AsI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
131 string asm, list<dag> pattern>
132 : sI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
134 class AXI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
136 : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
139 // Ctrl flow instructions
140 class ABLpredI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
141 string asm, list<dag> pattern>
142 : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
144 let Inst{24} = 1; // L bit
147 class ABLI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
149 : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
151 let Inst{24} = 1; // L bit
154 class ABLXI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
156 : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
159 let Inst{20-27} = 0x12;
162 class AXIx2<bits<4> opcod, dag oops, dag iops, Format f, string asm,
164 : XI<opcod, oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, f, asm,
166 class ABI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
168 : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
170 let Inst{24} = 0; // L bit
173 class ABccI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
174 string asm, list<dag> pattern>
175 : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
177 let Inst{24} = 0; // L bit
181 // BR_JT instructions
183 class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
184 : XI<opcod, oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BranchMisc,
186 let Inst{20} = 0; // S Bit
187 let Inst{21-24} = 0xd;
191 class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
192 : XI<opcod, oops, iops, AddrMode1, SizeSpecial, IndexModeNone, BranchMisc,
194 let Inst{20} = 1; // L bit
195 let Inst{21} = 0; // W bit
196 let Inst{22} = 0; // B bit
197 let Inst{24} = 1; // P bit
200 class JTI2<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
201 : XI<opcod, oops, iops, AddrMode2, SizeSpecial, IndexModeNone, BranchMisc,
203 let Inst{20} = 0; // S bit
209 // addrmode1 instructions
210 class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
211 string asm, list<dag> pattern>
212 : I<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
214 let Inst{21-24} = opcod;
217 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
218 string asm, list<dag> pattern>
219 : sI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
221 let Inst{21-24} = opcod;
224 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, string asm,
226 : XI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm,
228 let Inst{21-24} = opcod;
231 class AI1x2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
232 string asm, list<dag> pattern>
233 : I<opcod, oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, opc,
237 // addrmode2 loads and stores
238 class AI2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
239 string asm, list<dag> pattern>
240 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
244 class AXI2<bits<4> opcod, dag oops, dag iops, Format f, string asm,
246 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
250 class AI2ldw<bits<4> opcod, dag oops, dag iops, Format f, string opc,
251 string asm, list<dag> pattern>
252 : AI2<opcod, oops, iops, f, opc, asm, pattern> {
253 let Inst{20} = 1; // L bit
254 let Inst{21} = 0; // W bit
255 let Inst{22} = 0; // B bit
256 let Inst{24} = 1; // P bit
258 class AXI2ldw<bits<4> opcod, dag oops, dag iops, Format f, string asm,
260 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
262 let Inst{20} = 1; // L bit
263 let Inst{21} = 0; // W bit
264 let Inst{22} = 0; // B bit
265 let Inst{24} = 1; // P bit
267 class AI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
268 string asm, list<dag> pattern>
269 : AI2<opcod, oops, iops, f, opc, asm, pattern> {
270 let Inst{20} = 1; // L bit
271 let Inst{21} = 0; // W bit
272 let Inst{22} = 1; // B bit
273 let Inst{24} = 1; // P bit
275 class AXI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
277 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
279 let Inst{20} = 1; // L bit
280 let Inst{21} = 0; // W bit
281 let Inst{22} = 1; // B bit
282 let Inst{24} = 1; // P bit
286 class AI2stw<bits<4> opcod, dag oops, dag iops, Format f, string opc,
287 string asm, list<dag> pattern>
288 : AI2<opcod, oops, iops, f, opc, asm, pattern> {
289 let Inst{20} = 0; // L bit
290 let Inst{21} = 0; // W bit
291 let Inst{22} = 0; // B bit
292 let Inst{24} = 1; // P bit
294 class AXI2stw<bits<4> opcod, dag oops, dag iops, Format f, string asm,
296 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
298 let Inst{20} = 0; // L bit
299 let Inst{21} = 0; // W bit
300 let Inst{22} = 0; // B bit
301 let Inst{24} = 1; // P bit
303 class AI2stb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
304 string asm, list<dag> pattern>
305 : AI2<opcod, oops, iops, f, opc, asm, pattern> {
306 let Inst{20} = 0; // L bit
307 let Inst{21} = 0; // W bit
308 let Inst{22} = 1; // B bit
309 let Inst{24} = 1; // P bit
311 class AXI2stb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
313 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
315 let Inst{20} = 0; // L bit
316 let Inst{21} = 0; // W bit
317 let Inst{22} = 1; // B bit
318 let Inst{24} = 1; // P bit
322 class AI2ldwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
323 string asm, string cstr, list<dag> pattern>
324 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
325 asm, cstr, pattern> {
326 let Inst{20} = 1; // L bit
327 let Inst{21} = 1; // W bit
328 let Inst{22} = 0; // B bit
329 let Inst{24} = 1; // P bit
331 class AI2ldbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
332 string asm, string cstr, list<dag> pattern>
333 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
334 asm, cstr, pattern> {
335 let Inst{20} = 1; // L bit
336 let Inst{21} = 1; // W bit
337 let Inst{22} = 1; // B bit
338 let Inst{24} = 1; // P bit
341 // Pre-indexed stores
342 class AI2stwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
343 string asm, string cstr, list<dag> pattern>
344 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
345 asm, cstr, pattern> {
346 let Inst{20} = 0; // L bit
347 let Inst{21} = 1; // W bit
348 let Inst{22} = 0; // B bit
349 let Inst{24} = 1; // P bit
351 class AI2stbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
352 string asm, string cstr, list<dag> pattern>
353 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
354 asm, cstr, pattern> {
355 let Inst{20} = 0; // L bit
356 let Inst{21} = 1; // W bit
357 let Inst{22} = 1; // B bit
358 let Inst{24} = 1; // P bit
361 // Post-indexed loads
362 class AI2ldwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
363 string asm, string cstr, list<dag> pattern>
364 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
366 let Inst{20} = 1; // L bit
367 let Inst{21} = 0; // W bit
368 let Inst{22} = 0; // B bit
369 let Inst{24} = 0; // P bit
371 class AI2ldbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
372 string asm, string cstr, list<dag> pattern>
373 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
375 let Inst{20} = 1; // L bit
376 let Inst{21} = 0; // W bit
377 let Inst{22} = 1; // B bit
378 let Inst{24} = 0; // P bit
381 // Post-indexed stores
382 class AI2stwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
383 string asm, string cstr, list<dag> pattern>
384 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
386 let Inst{20} = 0; // L bit
387 let Inst{21} = 0; // W bit
388 let Inst{22} = 0; // B bit
389 let Inst{24} = 0; // P bit
391 class AI2stbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
392 string asm, string cstr, list<dag> pattern>
393 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
395 let Inst{20} = 0; // L bit
396 let Inst{21} = 0; // W bit
397 let Inst{22} = 1; // B bit
398 let Inst{24} = 0; // P bit
401 // addrmode3 instructions
402 class AI3<bits<4> opcod, dag oops, dag iops, Format f, string opc,
403 string asm, list<dag> pattern>
404 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
406 class AXI3<bits<4> opcod, dag oops, dag iops, Format f, string asm,
408 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
412 class AI3ldh<bits<4> opcod, dag oops, dag iops, Format f, string opc,
413 string asm, list<dag> pattern>
414 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
417 let Inst{5} = 1; // H bit
418 let Inst{6} = 0; // S bit
420 let Inst{20} = 1; // L bit
421 let Inst{21} = 0; // W bit
422 let Inst{24} = 1; // P bit
424 class AXI3ldh<bits<4> opcod, dag oops, dag iops, Format f, string asm,
426 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
429 let Inst{5} = 1; // H bit
430 let Inst{6} = 0; // S bit
432 let Inst{20} = 1; // L bit
433 let Inst{21} = 0; // W bit
434 let Inst{24} = 1; // P bit
436 class AI3ldsh<bits<4> opcod, dag oops, dag iops, Format f, string opc,
437 string asm, list<dag> pattern>
438 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
441 let Inst{5} = 1; // H bit
442 let Inst{6} = 1; // S bit
444 let Inst{20} = 1; // L bit
445 let Inst{21} = 0; // W bit
446 let Inst{24} = 1; // P bit
448 class AXI3ldsh<bits<4> opcod, dag oops, dag iops, Format f, string asm,
450 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
453 let Inst{5} = 1; // H bit
454 let Inst{6} = 1; // S bit
456 let Inst{20} = 1; // L bit
457 let Inst{21} = 0; // W bit
458 let Inst{24} = 1; // P bit
460 class AI3ldsb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
461 string asm, list<dag> pattern>
462 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
465 let Inst{5} = 0; // H bit
466 let Inst{6} = 1; // S bit
468 let Inst{20} = 1; // L bit
469 let Inst{21} = 0; // W bit
470 let Inst{24} = 1; // P bit
472 class AXI3ldsb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
474 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
477 let Inst{5} = 0; // H bit
478 let Inst{6} = 1; // S bit
480 let Inst{20} = 1; // L bit
481 let Inst{21} = 0; // W bit
482 let Inst{24} = 1; // P bit
484 class AI3ldd<bits<4> opcod, dag oops, dag iops, Format f, string opc,
485 string asm, list<dag> pattern>
486 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
489 let Inst{5} = 0; // H bit
490 let Inst{6} = 1; // S bit
492 let Inst{20} = 0; // L bit
493 let Inst{21} = 0; // W bit
494 let Inst{24} = 1; // P bit
498 class AI3sth<bits<4> opcod, dag oops, dag iops, Format f, string opc,
499 string asm, list<dag> pattern>
500 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
503 let Inst{5} = 1; // H bit
504 let Inst{6} = 0; // S bit
506 let Inst{20} = 0; // L bit
507 let Inst{21} = 0; // W bit
508 let Inst{24} = 1; // P bit
510 class AXI3sth<bits<4> opcod, dag oops, dag iops, Format f, string asm,
512 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
515 let Inst{5} = 1; // H bit
516 let Inst{6} = 0; // S bit
518 let Inst{20} = 0; // L bit
519 let Inst{21} = 0; // W bit
520 let Inst{24} = 1; // P bit
522 class AI3std<bits<4> opcod, dag oops, dag iops, Format f, string opc,
523 string asm, list<dag> pattern>
524 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
527 let Inst{5} = 1; // H bit
528 let Inst{6} = 1; // S bit
530 let Inst{20} = 0; // L bit
531 let Inst{21} = 0; // W bit
532 let Inst{24} = 1; // P bit
536 class AI3ldhpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
537 string asm, string cstr, list<dag> pattern>
538 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
539 asm, cstr, pattern> {
541 let Inst{5} = 1; // H bit
542 let Inst{6} = 0; // S bit
544 let Inst{20} = 1; // L bit
545 let Inst{21} = 1; // W bit
546 let Inst{24} = 1; // P bit
548 class AI3ldshpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
549 string asm, string cstr, list<dag> pattern>
550 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
551 asm, cstr, pattern> {
553 let Inst{5} = 1; // H bit
554 let Inst{6} = 1; // S bit
556 let Inst{20} = 1; // L bit
557 let Inst{21} = 1; // W bit
558 let Inst{24} = 1; // P bit
560 class AI3ldsbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
561 string asm, string cstr, list<dag> pattern>
562 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
563 asm, cstr, pattern> {
565 let Inst{5} = 0; // H bit
566 let Inst{6} = 1; // S bit
568 let Inst{20} = 1; // L bit
569 let Inst{21} = 1; // W bit
570 let Inst{24} = 1; // P bit
573 // Pre-indexed stores
574 class AI3sthpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
575 string asm, string cstr, list<dag> pattern>
576 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
577 asm, cstr, pattern> {
579 let Inst{5} = 1; // H bit
580 let Inst{6} = 0; // S bit
582 let Inst{20} = 0; // L bit
583 let Inst{21} = 1; // W bit
584 let Inst{24} = 1; // P bit
587 // Post-indexed loads
588 class AI3ldhpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
589 string asm, string cstr, list<dag> pattern>
590 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
593 let Inst{5} = 1; // H bit
594 let Inst{6} = 0; // S bit
596 let Inst{20} = 1; // L bit
597 let Inst{21} = 1; // W bit
598 let Inst{24} = 0; // P bit
600 class AI3ldshpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
601 string asm, string cstr, list<dag> pattern>
602 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
605 let Inst{5} = 1; // H bit
606 let Inst{6} = 1; // S bit
608 let Inst{20} = 1; // L bit
609 let Inst{21} = 1; // W bit
610 let Inst{24} = 0; // P bit
612 class AI3ldsbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
613 string asm, string cstr, list<dag> pattern>
614 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
617 let Inst{5} = 0; // H bit
618 let Inst{6} = 1; // S bit
620 let Inst{20} = 1; // L bit
621 let Inst{21} = 1; // W bit
622 let Inst{24} = 0; // P bit
625 // Post-indexed stores
626 class AI3sthpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
627 string asm, string cstr, list<dag> pattern>
628 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
631 let Inst{5} = 1; // H bit
632 let Inst{6} = 0; // S bit
634 let Inst{20} = 0; // L bit
635 let Inst{21} = 1; // W bit
636 let Inst{24} = 0; // P bit
640 // addrmode4 instructions
641 class AI4<bits<4> opcod, dag oops, dag iops, Format f, string opc,
642 string asm, list<dag> pattern>
643 : I<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, opc,
645 let Inst{25-27} = 0x4;
647 class AXI4ld<bits<4> opcod, dag oops, dag iops, Format f, string asm,
649 : XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
651 let Inst{20} = 1; // L bit
652 let Inst{22} = 0; // S bit
653 let Inst{25-27} = 0x4;
655 class AXI4ldpc<bits<4> opcod, dag oops, dag iops, Format f, string asm,
657 : XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
659 let Inst{20} = 1; // L bit
660 let Inst{22} = 1; // S bit
661 let Inst{25-27} = 0x4;
663 class AXI4st<bits<4> opcod, dag oops, dag iops, Format f, string asm,
665 : XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
667 let Inst{20} = 0; // L bit
668 let Inst{22} = 0; // S bit
669 let Inst{25-27} = 0x4;
673 //===----------------------------------------------------------------------===//
675 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
676 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
677 list<Predicate> Predicates = [IsARM];
679 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
680 list<Predicate> Predicates = [IsARM, HasV5TE];
682 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
683 list<Predicate> Predicates = [IsARM, HasV6];
686 //===----------------------------------------------------------------------===//
688 // Thumb Instruction Format Definitions.
692 // TI - Thumb instruction.
694 class ThumbI<dag outs, dag ins, AddrMode am, SizeFlagVal sz,
695 string asm, string cstr, list<dag> pattern>
696 // FIXME: Set all opcodes to 0 for now.
697 : InstARM<0, am, sz, IndexModeNone, ThumbFrm, cstr> {
698 let OutOperandList = outs;
699 let InOperandList = ins;
701 let Pattern = pattern;
702 list<Predicate> Predicates = [IsThumb];
705 class TI<dag outs, dag ins, string asm, list<dag> pattern>
706 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "", pattern>;
707 class TI1<dag outs, dag ins, string asm, list<dag> pattern>
708 : ThumbI<outs, ins, AddrModeT1, Size2Bytes, asm, "", pattern>;
709 class TI2<dag outs, dag ins, string asm, list<dag> pattern>
710 : ThumbI<outs, ins, AddrModeT2, Size2Bytes, asm, "", pattern>;
711 class TI4<dag outs, dag ins, string asm, list<dag> pattern>
712 : ThumbI<outs, ins, AddrModeT4, Size2Bytes, asm, "", pattern>;
713 class TIs<dag outs, dag ins, string asm, list<dag> pattern>
714 : ThumbI<outs, ins, AddrModeTs, Size2Bytes, asm, "", pattern>;
716 // Two-address instructions
717 class TIt<dag outs, dag ins, string asm, list<dag> pattern>
718 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>;
720 // BL, BLX(1) are translated by assembler into two instructions
721 class TIx2<dag outs, dag ins, string asm, list<dag> pattern>
722 : ThumbI<outs, ins, AddrModeNone, Size4Bytes, asm, "", pattern>;
724 // BR_JT instructions
725 class TJTI<dag outs, dag ins, string asm, list<dag> pattern>
726 : ThumbI<outs, ins, AddrModeNone, SizeSpecial, asm, "", pattern>;
729 //===----------------------------------------------------------------------===//
732 // ThumbPat - Same as Pat<>, but requires that the compiler be in Thumb mode.
733 class ThumbPat<dag pattern, dag result> : Pat<pattern, result> {
734 list<Predicate> Predicates = [IsThumb];
737 class ThumbV5Pat<dag pattern, dag result> : Pat<pattern, result> {
738 list<Predicate> Predicates = [IsThumb, HasV5T];