1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef ARMISELLOWERING_H
16 #define ARMISELLOWERING_H
18 #include "ARMSubtarget.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
25 class ARMConstantPoolValue;
28 // ARM Specific DAG Nodes
30 // Start the numbering where the builtin ops and target ops leave off.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
34 // TargetExternalSymbol, and TargetGlobalAddress.
35 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
37 CALL, // Function call.
38 CALL_PRED, // Function call that's predicable.
39 CALL_NOLINK, // Function call with branch not branch-and-link.
40 tCALL, // Thumb function call.
41 BRCOND, // Conditional branch.
42 BR_JT, // Jumptable branch.
43 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
44 RET_FLAG, // Return with a flag operand.
46 PIC_ADD, // Add with a PC operand and a PIC label.
48 CMP, // ARM compare instructions.
49 CMPZ, // ARM compare that sets only Z flag.
50 CMPFP, // ARM VFP compare instruction, sets FPSCR.
51 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
52 FMSTAT, // ARM fmstat instruction.
53 CMOV, // ARM conditional move instructions.
54 CNEG, // ARM conditional negate instructions.
58 RBIT, // ARM bitreverse instruction
60 FTOSI, // FP to sint within a FP register.
61 FTOUI, // FP to uint within a FP register.
62 SITOF, // sint to FP within a FP register.
63 UITOF, // uint to FP within a FP register.
65 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
66 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
67 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
69 VMOVRRD, // double to two gprs.
70 VMOVDRR, // Two gprs to double.
72 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
73 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
75 TC_RETURN, // Tail call return pseudo.
79 DYN_ALLOC, // Dynamic allocation on the stack.
81 MEMBARRIER, // Memory barrier
82 SYNCBARRIER, // Memory sync barrier
84 VCEQ, // Vector compare equal.
85 VCGE, // Vector compare greater than or equal.
86 VCGEU, // Vector compare unsigned greater than or equal.
87 VCGT, // Vector compare greater than.
88 VCGTU, // Vector compare unsigned greater than.
89 VTST, // Vector test bits.
91 // Vector shift by immediate:
93 VSHRs, // ...right (signed)
94 VSHRu, // ...right (unsigned)
95 VSHLLs, // ...left long (signed)
96 VSHLLu, // ...left long (unsigned)
97 VSHLLi, // ...left long (with maximum shift count)
98 VSHRN, // ...right narrow
100 // Vector rounding shift by immediate:
101 VRSHRs, // ...right (signed)
102 VRSHRu, // ...right (unsigned)
103 VRSHRN, // ...right narrow
105 // Vector saturating shift by immediate:
106 VQSHLs, // ...left (signed)
107 VQSHLu, // ...left (unsigned)
108 VQSHLsu, // ...left (signed to unsigned)
109 VQSHRNs, // ...right narrow (signed)
110 VQSHRNu, // ...right narrow (unsigned)
111 VQSHRNsu, // ...right narrow (signed to unsigned)
113 // Vector saturating rounding shift by immediate:
114 VQRSHRNs, // ...right narrow (signed)
115 VQRSHRNu, // ...right narrow (unsigned)
116 VQRSHRNsu, // ...right narrow (signed to unsigned)
118 // Vector shift and insert:
122 // Vector get lane (VMOV scalar to ARM core register)
123 // (These are used for 8- and 16-bit element types only.)
124 VGETLANEu, // zero-extend vector extract element
125 VGETLANEs, // sign-extend vector extract element
127 // Vector move immediate and move negated immediate:
137 VREV64, // reverse elements within 64-bit doublewords
138 VREV32, // reverse elements within 32-bit words
139 VREV16, // reverse elements within 16-bit halfwords
140 VZIP, // zip (interleave)
141 VUZP, // unzip (deinterleave)
144 // Operands of the standard BUILD_VECTOR node are not legalized, which
145 // is fine if BUILD_VECTORs are always lowered to shuffles or other
146 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
147 // operands need to be legalized. Define an ARM-specific version of
148 // BUILD_VECTOR for this purpose.
151 // Floating-point max and min:
160 /// Define some predicates that are used for node matching.
162 /// getVFPf32Imm / getVFPf64Imm - If the given fp immediate can be
163 /// materialized with a VMOV.f32 / VMOV.f64 (i.e. fconsts / fconstd)
164 /// instruction, returns its 8-bit integer representation. Otherwise,
166 int getVFPf32Imm(const APFloat &FPImm);
167 int getVFPf64Imm(const APFloat &FPImm);
168 bool isBitFieldInvertedMask(unsigned v);
171 //===--------------------------------------------------------------------===//
172 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
174 class ARMTargetLowering : public TargetLowering {
176 explicit ARMTargetLowering(TargetMachine &TM);
178 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
180 /// ReplaceNodeResults - Replace the results of node with an illegal result
181 /// type with new values built out of custom code.
183 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
184 SelectionDAG &DAG) const;
186 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
188 virtual const char *getTargetNodeName(unsigned Opcode) const;
190 virtual MachineBasicBlock *
191 EmitInstrWithCustomInserter(MachineInstr *MI,
192 MachineBasicBlock *MBB) const;
194 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
195 /// unaligned memory accesses. of the specified type.
196 /// FIXME: Add getOptimalMemOpType to implement memcpy with NEON?
197 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const;
199 /// isLegalAddressingMode - Return true if the addressing mode represented
200 /// by AM is legal for this target, for a load/store of the specified type.
201 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
202 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
204 /// isLegalICmpImmediate - Return true if the specified immediate is legal
205 /// icmp immediate, that is the target has icmp instructions which can
206 /// compare a register against the immediate without having to materialize
207 /// the immediate into a register.
208 virtual bool isLegalICmpImmediate(int64_t Imm) const;
210 /// getPreIndexedAddressParts - returns true by value, base pointer and
211 /// offset pointer and addressing mode by reference if the node's address
212 /// can be legally represented as pre-indexed load / store address.
213 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
215 ISD::MemIndexedMode &AM,
216 SelectionDAG &DAG) const;
218 /// getPostIndexedAddressParts - returns true by value, base pointer and
219 /// offset pointer and addressing mode by reference if this node can be
220 /// combined with a load / store to form a post-indexed load / store.
221 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
222 SDValue &Base, SDValue &Offset,
223 ISD::MemIndexedMode &AM,
224 SelectionDAG &DAG) const;
226 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
230 const SelectionDAG &DAG,
231 unsigned Depth) const;
234 ConstraintType getConstraintType(const std::string &Constraint) const;
235 std::pair<unsigned, const TargetRegisterClass*>
236 getRegForInlineAsmConstraint(const std::string &Constraint,
238 std::vector<unsigned>
239 getRegClassForInlineAsmConstraint(const std::string &Constraint,
242 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
243 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
244 /// true it means one of the asm constraint of the inline asm instruction
245 /// being processed is 'm'.
246 virtual void LowerAsmOperandForConstraint(SDValue Op,
247 char ConstraintLetter,
248 std::vector<SDValue> &Ops,
249 SelectionDAG &DAG) const;
251 const ARMSubtarget* getSubtarget() const {
255 /// getRegClassFor - Return the register class that should be used for the
256 /// specified value type.
257 virtual TargetRegisterClass *getRegClassFor(EVT VT) const;
259 /// getFunctionAlignment - Return the Log2 alignment of this function.
260 virtual unsigned getFunctionAlignment(const Function *F) const;
262 Sched::Preference getSchedulingPreference(SDNode *N) const;
264 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
265 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
267 /// isFPImmLegal - Returns true if the target can instruction select the
268 /// specified FP immediate natively. If false, the legalizer will
269 /// materialize the FP immediate as a load from a constant pool.
270 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
273 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
274 /// make the right decision when generating code for different targets.
275 const ARMSubtarget *Subtarget;
277 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
279 unsigned ARMPCLabelIndex;
281 void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT);
282 void addDRTypeForNEON(EVT VT);
283 void addQRTypeForNEON(EVT VT);
285 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
286 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
287 SDValue Chain, SDValue &Arg,
288 RegsToPassVector &RegsToPass,
289 CCValAssign &VA, CCValAssign &NextVA,
291 SmallVector<SDValue, 8> &MemOpChains,
292 ISD::ArgFlagsTy Flags) const;
293 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
294 SDValue &Root, SelectionDAG &DAG,
297 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
298 bool isVarArg) const;
299 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
300 DebugLoc dl, SelectionDAG &DAG,
301 const CCValAssign &VA,
302 ISD::ArgFlagsTy Flags) const;
303 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
304 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
305 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
306 const ARMSubtarget *Subtarget) const;
307 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
308 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
309 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
310 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
311 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
312 SelectionDAG &DAG) const;
313 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
314 SelectionDAG &DAG) const;
315 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
316 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
317 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
318 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
319 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
320 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
321 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
322 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
323 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
324 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
326 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
327 CallingConv::ID CallConv, bool isVarArg,
328 const SmallVectorImpl<ISD::InputArg> &Ins,
329 DebugLoc dl, SelectionDAG &DAG,
330 SmallVectorImpl<SDValue> &InVals) const;
333 LowerFormalArguments(SDValue Chain,
334 CallingConv::ID CallConv, bool isVarArg,
335 const SmallVectorImpl<ISD::InputArg> &Ins,
336 DebugLoc dl, SelectionDAG &DAG,
337 SmallVectorImpl<SDValue> &InVals) const;
340 LowerCall(SDValue Chain, SDValue Callee,
341 CallingConv::ID CallConv, bool isVarArg,
343 const SmallVectorImpl<ISD::OutputArg> &Outs,
344 const SmallVectorImpl<SDValue> &OutVals,
345 const SmallVectorImpl<ISD::InputArg> &Ins,
346 DebugLoc dl, SelectionDAG &DAG,
347 SmallVectorImpl<SDValue> &InVals) const;
349 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
350 /// for tail call optimization. Targets which want to do tail call
351 /// optimization should implement this function.
352 bool IsEligibleForTailCallOptimization(SDValue Callee,
353 CallingConv::ID CalleeCC,
355 bool isCalleeStructRet,
356 bool isCallerStructRet,
357 const SmallVectorImpl<ISD::OutputArg> &Outs,
358 const SmallVectorImpl<SDValue> &OutVals,
359 const SmallVectorImpl<ISD::InputArg> &Ins,
360 SelectionDAG& DAG) const;
362 LowerReturn(SDValue Chain,
363 CallingConv::ID CallConv, bool isVarArg,
364 const SmallVectorImpl<ISD::OutputArg> &Outs,
365 const SmallVectorImpl<SDValue> &OutVals,
366 DebugLoc dl, SelectionDAG &DAG) const;
368 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
369 SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const;
370 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
371 SelectionDAG &DAG, DebugLoc dl) const;
373 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
375 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
376 MachineBasicBlock *BB,
377 unsigned Size) const;
378 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
379 MachineBasicBlock *BB,
381 unsigned BinOpcode) const;
386 #endif // ARMISELLOWERING_H