1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef ARMISELLOWERING_H
16 #define ARMISELLOWERING_H
18 #include "ARMSubtarget.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
25 class ARMConstantPoolValue;
28 // ARM Specific DAG Nodes
30 // Start the numbering where the builtin ops and target ops leave off.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
34 // TargetExternalSymbol, and TargetGlobalAddress.
35 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
37 CALL, // Function call.
38 CALL_PRED, // Function call that's predicable.
39 CALL_NOLINK, // Function call with branch not branch-and-link.
40 tCALL, // Thumb function call.
41 BRCOND, // Conditional branch.
42 BR_JT, // Jumptable branch.
43 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
44 RET_FLAG, // Return with a flag operand.
46 PIC_ADD, // Add with a PC operand and a PIC label.
48 CMP, // ARM compare instructions.
49 CMPZ, // ARM compare that sets only Z flag.
50 CMPFP, // ARM VFP compare instruction, sets FPSCR.
51 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
52 FMSTAT, // ARM fmstat instruction.
53 CMOV, // ARM conditional move instructions.
54 CNEG, // ARM conditional negate instructions.
56 RBIT, // ARM bitreverse instruction
58 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
59 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
60 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
62 VMOVRRD, // double to two gprs.
63 VMOVDRR, // Two gprs to double.
65 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
66 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
70 DYN_ALLOC, // Dynamic allocation on the stack.
72 MEMBARRIER, // Memory barrier
73 SYNCBARRIER, // Memory sync barrier
75 VCEQ, // Vector compare equal.
76 VCGE, // Vector compare greater than or equal.
77 VCGEU, // Vector compare unsigned greater than or equal.
78 VCGT, // Vector compare greater than.
79 VCGTU, // Vector compare unsigned greater than.
80 VTST, // Vector test bits.
82 // Vector shift by immediate:
84 VSHRs, // ...right (signed)
85 VSHRu, // ...right (unsigned)
86 VSHLLs, // ...left long (signed)
87 VSHLLu, // ...left long (unsigned)
88 VSHLLi, // ...left long (with maximum shift count)
89 VSHRN, // ...right narrow
91 // Vector rounding shift by immediate:
92 VRSHRs, // ...right (signed)
93 VRSHRu, // ...right (unsigned)
94 VRSHRN, // ...right narrow
96 // Vector saturating shift by immediate:
97 VQSHLs, // ...left (signed)
98 VQSHLu, // ...left (unsigned)
99 VQSHLsu, // ...left (signed to unsigned)
100 VQSHRNs, // ...right narrow (signed)
101 VQSHRNu, // ...right narrow (unsigned)
102 VQSHRNsu, // ...right narrow (signed to unsigned)
104 // Vector saturating rounding shift by immediate:
105 VQRSHRNs, // ...right narrow (signed)
106 VQRSHRNu, // ...right narrow (unsigned)
107 VQRSHRNsu, // ...right narrow (signed to unsigned)
109 // Vector shift and insert:
113 // Vector get lane (VMOV scalar to ARM core register)
114 // (These are used for 8- and 16-bit element types only.)
115 VGETLANEu, // zero-extend vector extract element
116 VGETLANEs, // sign-extend vector extract element
124 VREV64, // reverse elements within 64-bit doublewords
125 VREV32, // reverse elements within 32-bit words
126 VREV16, // reverse elements within 16-bit halfwords
127 VZIP, // zip (interleave)
128 VUZP, // unzip (deinterleave)
131 // Floating-point max and min:
137 /// Define some predicates that are used for node matching.
139 /// getVMOVImm - If this is a build_vector of constants which can be
140 /// formed by using a VMOV instruction of the specified element size,
141 /// return the constant being splatted. The ByteSize field indicates the
142 /// number of bytes of each element [1248].
143 SDValue getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
145 /// getVFPf32Imm / getVFPf64Imm - If the given fp immediate can be
146 /// materialized with a VMOV.f32 / VMOV.f64 (i.e. fconsts / fconstd)
147 /// instruction, returns its 8-bit integer representation. Otherwise,
149 int getVFPf32Imm(const APFloat &FPImm);
150 int getVFPf64Imm(const APFloat &FPImm);
153 //===--------------------------------------------------------------------===//
154 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
156 class ARMTargetLowering : public TargetLowering {
157 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
159 explicit ARMTargetLowering(TargetMachine &TM);
161 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
163 /// ReplaceNodeResults - Replace the results of node with an illegal result
164 /// type with new values built out of custom code.
166 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
169 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
171 virtual const char *getTargetNodeName(unsigned Opcode) const;
173 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
174 MachineBasicBlock *MBB,
175 DenseMap<MachineBasicBlock*, MachineBasicBlock*>*) const;
177 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
178 /// unaligned memory accesses. of the specified type.
179 /// FIXME: Add getOptimalMemOpType to implement memcpy with NEON?
180 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const;
182 /// isLegalAddressingMode - Return true if the addressing mode represented
183 /// by AM is legal for this target, for a load/store of the specified type.
184 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
185 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
187 /// isLegalICmpImmediate - Return true if the specified immediate is legal
188 /// icmp immediate, that is the target has icmp instructions which can compare
189 /// a register against the immediate without having to materialize the
190 /// immediate into a register.
191 virtual bool isLegalICmpImmediate(int64_t Imm) const;
193 /// getPreIndexedAddressParts - returns true by value, base pointer and
194 /// offset pointer and addressing mode by reference if the node's address
195 /// can be legally represented as pre-indexed load / store address.
196 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
198 ISD::MemIndexedMode &AM,
199 SelectionDAG &DAG) const;
201 /// getPostIndexedAddressParts - returns true by value, base pointer and
202 /// offset pointer and addressing mode by reference if this node can be
203 /// combined with a load / store to form a post-indexed load / store.
204 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
205 SDValue &Base, SDValue &Offset,
206 ISD::MemIndexedMode &AM,
207 SelectionDAG &DAG) const;
209 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
213 const SelectionDAG &DAG,
214 unsigned Depth) const;
217 ConstraintType getConstraintType(const std::string &Constraint) const;
218 std::pair<unsigned, const TargetRegisterClass*>
219 getRegForInlineAsmConstraint(const std::string &Constraint,
221 std::vector<unsigned>
222 getRegClassForInlineAsmConstraint(const std::string &Constraint,
225 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
226 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
227 /// true it means one of the asm constraint of the inline asm instruction
228 /// being processed is 'm'.
229 virtual void LowerAsmOperandForConstraint(SDValue Op,
230 char ConstraintLetter,
232 std::vector<SDValue> &Ops,
233 SelectionDAG &DAG) const;
235 virtual const ARMSubtarget* getSubtarget() {
239 /// getFunctionAlignment - Return the Log2 alignment of this function.
240 virtual unsigned getFunctionAlignment(const Function *F) const;
242 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
243 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
245 /// isFPImmLegal - Returns true if the target can instruction select the
246 /// specified FP immediate natively. If false, the legalizer will
247 /// materialize the FP immediate as a load from a constant pool.
248 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
251 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
252 /// make the right decision when generating code for different targets.
253 const ARMSubtarget *Subtarget;
255 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
257 unsigned ARMPCLabelIndex;
259 void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT);
260 void addDRTypeForNEON(EVT VT);
261 void addQRTypeForNEON(EVT VT);
263 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
264 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
265 SDValue Chain, SDValue &Arg,
266 RegsToPassVector &RegsToPass,
267 CCValAssign &VA, CCValAssign &NextVA,
269 SmallVector<SDValue, 8> &MemOpChains,
270 ISD::ArgFlagsTy Flags);
271 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
272 SDValue &Root, SelectionDAG &DAG, DebugLoc dl);
274 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return, bool isVarArg) const;
275 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
276 DebugLoc dl, SelectionDAG &DAG,
277 const CCValAssign &VA,
278 ISD::ArgFlagsTy Flags);
279 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG);
280 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
281 const ARMSubtarget *Subtarget);
282 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG);
283 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG);
284 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG);
285 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
286 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
288 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
290 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG);
291 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG);
292 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
293 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG);
294 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
295 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG);
296 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG);
297 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG);
299 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
301 SDValue Dst, SDValue Src,
302 SDValue Size, unsigned Align,
304 const Value *DstSV, uint64_t DstSVOff,
305 const Value *SrcSV, uint64_t SrcSVOff);
306 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
307 CallingConv::ID CallConv, bool isVarArg,
308 const SmallVectorImpl<ISD::InputArg> &Ins,
309 DebugLoc dl, SelectionDAG &DAG,
310 SmallVectorImpl<SDValue> &InVals);
313 LowerFormalArguments(SDValue Chain,
314 CallingConv::ID CallConv, bool isVarArg,
315 const SmallVectorImpl<ISD::InputArg> &Ins,
316 DebugLoc dl, SelectionDAG &DAG,
317 SmallVectorImpl<SDValue> &InVals);
320 LowerCall(SDValue Chain, SDValue Callee,
321 CallingConv::ID CallConv, bool isVarArg,
323 const SmallVectorImpl<ISD::OutputArg> &Outs,
324 const SmallVectorImpl<ISD::InputArg> &Ins,
325 DebugLoc dl, SelectionDAG &DAG,
326 SmallVectorImpl<SDValue> &InVals);
329 LowerReturn(SDValue Chain,
330 CallingConv::ID CallConv, bool isVarArg,
331 const SmallVectorImpl<ISD::OutputArg> &Outs,
332 DebugLoc dl, SelectionDAG &DAG);
334 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
335 SDValue &ARMCC, SelectionDAG &DAG, DebugLoc dl);
337 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
338 MachineBasicBlock *BB,
339 unsigned Size) const;
340 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
341 MachineBasicBlock *BB,
343 unsigned BinOpcode) const;
348 #endif // ARMISELLOWERING_H