1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
16 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
18 #include "MCTargetDesc/ARMBaseInfo.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
25 class ARMConstantPoolValue;
29 // ARM Specific DAG Nodes
31 // Start the numbering where the builtin ops and target ops leave off.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
35 // TargetExternalSymbol, and TargetGlobalAddress.
36 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
38 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
40 // Add pseudo op to model memcpy for struct byval.
43 CALL, // Function call.
44 CALL_PRED, // Function call that's predicable.
45 CALL_NOLINK, // Function call with branch not branch-and-link.
46 tCALL, // Thumb function call.
47 BRCOND, // Conditional branch.
48 BR_JT, // Jumptable branch.
49 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
50 RET_FLAG, // Return with a flag operand.
51 INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand.
53 PIC_ADD, // Add with a PC operand and a PIC label.
55 CMP, // ARM compare instructions.
56 CMN, // ARM CMN instructions.
57 CMPZ, // ARM compare that sets only Z flag.
58 CMPFP, // ARM VFP compare instruction, sets FPSCR.
59 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
60 FMSTAT, // ARM fmstat instruction.
62 CMOV, // ARM conditional move instructions.
66 RBIT, // ARM bitreverse instruction
68 FTOSI, // FP to sint within a FP register.
69 FTOUI, // FP to uint within a FP register.
70 SITOF, // sint to FP within a FP register.
71 UITOF, // uint to FP within a FP register.
73 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
74 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
75 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
77 ADDC, // Add with carry
78 ADDE, // Add using carry
79 SUBC, // Sub with carry
80 SUBE, // Sub using carry
82 VMOVRRD, // double to two gprs.
83 VMOVDRR, // Two gprs to double.
85 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
86 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
88 TC_RETURN, // Tail call return pseudo.
92 DYN_ALLOC, // Dynamic allocation on the stack.
94 MEMBARRIER_MCR, // Memory barrier (MCR)
98 WIN__CHKSTK, // Windows' __chkstk call to do stack probing.
100 VCEQ, // Vector compare equal.
101 VCEQZ, // Vector compare equal to zero.
102 VCGE, // Vector compare greater than or equal.
103 VCGEZ, // Vector compare greater than or equal to zero.
104 VCLEZ, // Vector compare less than or equal to zero.
105 VCGEU, // Vector compare unsigned greater than or equal.
106 VCGT, // Vector compare greater than.
107 VCGTZ, // Vector compare greater than zero.
108 VCLTZ, // Vector compare less than zero.
109 VCGTU, // Vector compare unsigned greater than.
110 VTST, // Vector test bits.
112 // Vector shift by immediate:
114 VSHRs, // ...right (signed)
115 VSHRu, // ...right (unsigned)
117 // Vector rounding shift by immediate:
118 VRSHRs, // ...right (signed)
119 VRSHRu, // ...right (unsigned)
120 VRSHRN, // ...right narrow
122 // Vector saturating shift by immediate:
123 VQSHLs, // ...left (signed)
124 VQSHLu, // ...left (unsigned)
125 VQSHLsu, // ...left (signed to unsigned)
126 VQSHRNs, // ...right narrow (signed)
127 VQSHRNu, // ...right narrow (unsigned)
128 VQSHRNsu, // ...right narrow (signed to unsigned)
130 // Vector saturating rounding shift by immediate:
131 VQRSHRNs, // ...right narrow (signed)
132 VQRSHRNu, // ...right narrow (unsigned)
133 VQRSHRNsu, // ...right narrow (signed to unsigned)
135 // Vector shift and insert:
139 // Vector get lane (VMOV scalar to ARM core register)
140 // (These are used for 8- and 16-bit element types only.)
141 VGETLANEu, // zero-extend vector extract element
142 VGETLANEs, // sign-extend vector extract element
144 // Vector move immediate and move negated immediate:
148 // Vector move f32 immediate:
157 VREV64, // reverse elements within 64-bit doublewords
158 VREV32, // reverse elements within 32-bit words
159 VREV16, // reverse elements within 16-bit halfwords
160 VZIP, // zip (interleave)
161 VUZP, // unzip (deinterleave)
163 VTBL1, // 1-register shuffle with mask
164 VTBL2, // 2-register shuffle with mask
166 // Vector multiply long:
168 VMULLu, // ...unsigned
170 UMLAL, // 64bit Unsigned Accumulate Multiply
171 SMLAL, // 64bit Signed Accumulate Multiply
173 // Operands of the standard BUILD_VECTOR node are not legalized, which
174 // is fine if BUILD_VECTORs are always lowered to shuffles or other
175 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
176 // operands need to be legalized. Define an ARM-specific version of
177 // BUILD_VECTOR for this purpose.
180 // Floating-point max and min:
189 // Vector OR with immediate
191 // Vector AND with NOT of immediate
194 // Vector bitwise select
197 // Vector load N-element structure to all lanes:
198 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
202 // NEON loads with post-increment base updates:
214 // NEON stores with post-increment base updates:
225 /// Define some predicates that are used for node matching.
227 bool isBitFieldInvertedMask(unsigned v);
230 //===--------------------------------------------------------------------===//
231 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
233 class ARMTargetLowering : public TargetLowering {
235 explicit ARMTargetLowering(const TargetMachine &TM);
237 unsigned getJumpTableEncoding() const override;
239 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
241 /// ReplaceNodeResults - Replace the results of node with an illegal result
242 /// type with new values built out of custom code.
244 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
245 SelectionDAG &DAG) const override;
247 const char *getTargetNodeName(unsigned Opcode) const override;
249 bool isSelectSupported(SelectSupportKind Kind) const override {
250 // ARM does not support scalar condition selects on vectors.
251 return (Kind != ScalarCondVectorVal);
254 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
255 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
258 EmitInstrWithCustomInserter(MachineInstr *MI,
259 MachineBasicBlock *MBB) const override;
261 void AdjustInstrPostInstrSelection(MachineInstr *MI,
262 SDNode *Node) const override;
264 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
265 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
267 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
269 /// allowsMisalignedMemoryAccesses - Returns true if the target allows
270 /// unaligned memory accesses of the specified type. Returns whether it
271 /// is "fast" by reference in the second argument.
272 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
274 bool *Fast) const override;
276 EVT getOptimalMemOpType(uint64_t Size,
277 unsigned DstAlign, unsigned SrcAlign,
278 bool IsMemset, bool ZeroMemset,
280 MachineFunction &MF) const override;
282 using TargetLowering::isZExtFree;
283 bool isZExtFree(SDValue Val, EVT VT2) const override;
285 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
288 /// isLegalAddressingMode - Return true if the addressing mode represented
289 /// by AM is legal for this target, for a load/store of the specified type.
290 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
291 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
293 /// isLegalICmpImmediate - Return true if the specified immediate is legal
294 /// icmp immediate, that is the target has icmp instructions which can
295 /// compare a register against the immediate without having to materialize
296 /// the immediate into a register.
297 bool isLegalICmpImmediate(int64_t Imm) const override;
299 /// isLegalAddImmediate - Return true if the specified immediate is legal
300 /// add immediate, that is the target has add instructions which can
301 /// add a register and the immediate without having to materialize
302 /// the immediate into a register.
303 bool isLegalAddImmediate(int64_t Imm) const override;
305 /// getPreIndexedAddressParts - returns true by value, base pointer and
306 /// offset pointer and addressing mode by reference if the node's address
307 /// can be legally represented as pre-indexed load / store address.
308 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
309 ISD::MemIndexedMode &AM,
310 SelectionDAG &DAG) const override;
312 /// getPostIndexedAddressParts - returns true by value, base pointer and
313 /// offset pointer and addressing mode by reference if this node can be
314 /// combined with a load / store to form a post-indexed load / store.
315 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
316 SDValue &Offset, ISD::MemIndexedMode &AM,
317 SelectionDAG &DAG) const override;
319 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
321 const SelectionDAG &DAG,
322 unsigned Depth) const override;
325 bool ExpandInlineAsm(CallInst *CI) const override;
328 getConstraintType(const std::string &Constraint) const override;
330 /// Examine constraint string and operand type and determine a weight value.
331 /// The operand object must already have been set up with the operand type.
332 ConstraintWeight getSingleConstraintMatchWeight(
333 AsmOperandInfo &info, const char *constraint) const override;
335 std::pair<unsigned, const TargetRegisterClass*>
336 getRegForInlineAsmConstraint(const std::string &Constraint,
337 MVT VT) const override;
339 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
340 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
341 /// true it means one of the asm constraint of the inline asm instruction
342 /// being processed is 'm'.
343 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
344 std::vector<SDValue> &Ops,
345 SelectionDAG &DAG) const override;
347 const ARMSubtarget* getSubtarget() const {
351 /// getRegClassFor - Return the register class that should be used for the
352 /// specified value type.
353 const TargetRegisterClass *getRegClassFor(MVT VT) const override;
355 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
356 /// be used for loads / stores from the global.
357 unsigned getMaximalGlobalOffset() const override;
359 /// Returns true if a cast between SrcAS and DestAS is a noop.
360 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
361 // Addrspacecasts are always noops.
365 /// createFastISel - This method returns a target specific FastISel object,
366 /// or null if the target does not support "fast" ISel.
367 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
368 const TargetLibraryInfo *libInfo) const override;
370 Sched::Preference getSchedulingPreference(SDNode *N) const override;
373 isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const override;
374 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
376 /// isFPImmLegal - Returns true if the target can instruction select the
377 /// specified FP immediate natively. If false, the legalizer will
378 /// materialize the FP immediate as a load from a constant pool.
379 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
381 bool getTgtMemIntrinsic(IntrinsicInfo &Info,
383 unsigned Intrinsic) const override;
385 /// \brief Returns true if it is beneficial to convert a load of a constant
386 /// to just the constant itself.
387 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
388 Type *Ty) const override;
390 /// \brief Returns true if an argument of type Ty needs to be passed in a
391 /// contiguous block of registers in calling convention CallConv.
392 bool functionArgumentNeedsConsecutiveRegisters(
393 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override;
395 bool hasLoadLinkedStoreConditional() const override;
396 Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const;
397 Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
398 AtomicOrdering Ord) const override;
399 Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
400 Value *Addr, AtomicOrdering Ord) const override;
402 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
403 bool IsStore, bool IsLoad) const override;
404 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
405 bool IsStore, bool IsLoad) const override;
407 bool shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
408 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
409 bool shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
411 bool useLoadStackGuardNode() const override;
413 bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
414 unsigned &Cost) const override;
417 std::pair<const TargetRegisterClass*, uint8_t>
418 findRepresentativeClass(MVT VT) const override;
421 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
422 /// make the right decision when generating code for different targets.
423 const ARMSubtarget *Subtarget;
425 const TargetRegisterInfo *RegInfo;
427 const InstrItineraryData *Itins;
429 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
431 unsigned ARMPCLabelIndex;
433 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
434 void addDRTypeForNEON(MVT VT);
435 void addQRTypeForNEON(MVT VT);
436 std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
438 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
439 void PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG,
440 SDValue Chain, SDValue &Arg,
441 RegsToPassVector &RegsToPass,
442 CCValAssign &VA, CCValAssign &NextVA,
444 SmallVectorImpl<SDValue> &MemOpChains,
445 ISD::ArgFlagsTy Flags) const;
446 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
447 SDValue &Root, SelectionDAG &DAG,
450 CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
451 bool isVarArg) const;
452 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
453 bool isVarArg) const;
454 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
455 SDLoc dl, SelectionDAG &DAG,
456 const CCValAssign &VA,
457 ISD::ArgFlagsTy Flags) const;
458 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
459 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
460 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
461 const ARMSubtarget *Subtarget) const;
462 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
463 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
464 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
465 SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
466 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
467 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
468 SelectionDAG &DAG) const;
469 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
471 TLSModel::Model model) const;
472 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
473 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
474 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
475 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
476 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
477 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
478 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
479 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
480 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
481 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
482 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
483 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
484 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
485 const ARMSubtarget *ST) const;
486 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
487 const ARMSubtarget *ST) const;
488 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
489 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
490 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
491 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
492 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
493 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
494 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
496 unsigned getRegisterByName(const char* RegName, EVT VT) const override;
498 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
499 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
500 /// expanded to FMAs when this method returns true, otherwise fmuladd is
501 /// expanded to fmul + fadd.
503 /// ARM supports both fused and unfused multiply-add operations; we already
504 /// lower a pair of fmul and fadd to the latter so it's not clear that there
505 /// would be a gain or that the gain would be worthwhile enough to risk
506 /// correctness bugs.
507 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; }
509 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
511 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
512 CallingConv::ID CallConv, bool isVarArg,
513 const SmallVectorImpl<ISD::InputArg> &Ins,
514 SDLoc dl, SelectionDAG &DAG,
515 SmallVectorImpl<SDValue> &InVals,
516 bool isThisReturn, SDValue ThisVal) const;
519 LowerFormalArguments(SDValue Chain,
520 CallingConv::ID CallConv, bool isVarArg,
521 const SmallVectorImpl<ISD::InputArg> &Ins,
522 SDLoc dl, SelectionDAG &DAG,
523 SmallVectorImpl<SDValue> &InVals) const override;
525 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
526 SDLoc dl, SDValue &Chain,
527 const Value *OrigArg,
528 unsigned InRegsParamRecordIdx,
529 unsigned OffsetFromOrigArg,
533 unsigned ByValStoreOffset,
534 unsigned TotalArgRegsSaveSize) const;
536 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
537 SDLoc dl, SDValue &Chain,
539 unsigned TotalArgRegsSaveSize,
540 bool ForceMutable = false) const;
542 void computeRegArea(CCState &CCInfo, MachineFunction &MF,
543 unsigned InRegsParamRecordIdx,
545 unsigned &ArgRegsSize,
546 unsigned &ArgRegsSaveSize) const;
549 LowerCall(TargetLowering::CallLoweringInfo &CLI,
550 SmallVectorImpl<SDValue> &InVals) const override;
552 /// HandleByVal - Target-specific cleanup for ByVal support.
553 void HandleByVal(CCState *, unsigned &, unsigned) const override;
555 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
556 /// for tail call optimization. Targets which want to do tail call
557 /// optimization should implement this function.
558 bool IsEligibleForTailCallOptimization(SDValue Callee,
559 CallingConv::ID CalleeCC,
561 bool isCalleeStructRet,
562 bool isCallerStructRet,
563 const SmallVectorImpl<ISD::OutputArg> &Outs,
564 const SmallVectorImpl<SDValue> &OutVals,
565 const SmallVectorImpl<ISD::InputArg> &Ins,
566 SelectionDAG& DAG) const;
568 bool CanLowerReturn(CallingConv::ID CallConv,
569 MachineFunction &MF, bool isVarArg,
570 const SmallVectorImpl<ISD::OutputArg> &Outs,
571 LLVMContext &Context) const override;
574 LowerReturn(SDValue Chain,
575 CallingConv::ID CallConv, bool isVarArg,
576 const SmallVectorImpl<ISD::OutputArg> &Outs,
577 const SmallVectorImpl<SDValue> &OutVals,
578 SDLoc dl, SelectionDAG &DAG) const override;
580 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
582 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
584 SDValue getCMOV(SDLoc dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
585 SDValue ARMcc, SDValue CCR, SDValue Cmp,
586 SelectionDAG &DAG) const;
587 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
588 SDValue &ARMcc, SelectionDAG &DAG, SDLoc dl) const;
589 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
590 SelectionDAG &DAG, SDLoc dl) const;
591 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
593 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
595 void SetupEntryBlockForSjLj(MachineInstr *MI,
596 MachineBasicBlock *MBB,
597 MachineBasicBlock *DispatchBB, int FI) const;
599 MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr *MI,
600 MachineBasicBlock *MBB) const;
602 bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const;
604 MachineBasicBlock *EmitStructByval(MachineInstr *MI,
605 MachineBasicBlock *MBB) const;
607 MachineBasicBlock *EmitLowered__chkstk(MachineInstr *MI,
608 MachineBasicBlock *MBB) const;
611 enum NEONModImmType {
618 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
619 const TargetLibraryInfo *libInfo);
623 #endif // ARMISELLOWERING_H