1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
16 #include "ARMISelLowering.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMPerfectShuffle.h"
22 #include "ARMSubtarget.h"
23 #include "ARMTargetMachine.h"
24 #include "ARMTargetObjectFile.h"
25 #include "MCTargetDesc/ARMAddressingModes.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/ADT/StringExtras.h"
28 #include "llvm/CodeGen/CallingConvLower.h"
29 #include "llvm/CodeGen/IntrinsicLowering.h"
30 #include "llvm/CodeGen/MachineBasicBlock.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalValue.h"
41 #include "llvm/IR/Instruction.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/IR/LLVMContext.h"
45 #include "llvm/IR/Type.h"
46 #include "llvm/MC/MCSectionMachO.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Support/raw_ostream.h"
51 #include "llvm/Target/TargetOptions.h"
55 STATISTIC(NumTailCalls, "Number of tail calls");
56 STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt");
57 STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments");
59 // This option should go away when tail calls fully work.
61 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
62 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
66 EnableARMLongCalls("arm-long-calls", cl::Hidden,
67 cl::desc("Generate calls via indirect call instructions"),
71 ARMInterworking("arm-interworking", cl::Hidden,
72 cl::desc("Enable / disable ARM interworking (for debugging only)"),
76 class ARMCCState : public CCState {
78 ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
79 const TargetMachine &TM, SmallVectorImpl<CCValAssign> &locs,
80 LLVMContext &C, ParmContext PC)
81 : CCState(CC, isVarArg, MF, TM, locs, C) {
82 assert(((PC == Call) || (PC == Prologue)) &&
83 "ARMCCState users must specify whether their context is call"
84 "or prologue generation.");
90 // The APCS parameter registers.
91 static const uint16_t GPRArgRegs[] = {
92 ARM::R0, ARM::R1, ARM::R2, ARM::R3
95 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
96 MVT PromotedBitwiseVT) {
97 if (VT != PromotedLdStVT) {
98 setOperationAction(ISD::LOAD, VT, Promote);
99 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
101 setOperationAction(ISD::STORE, VT, Promote);
102 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
105 MVT ElemTy = VT.getVectorElementType();
106 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
107 setOperationAction(ISD::SETCC, VT, Custom);
108 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
109 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
110 if (ElemTy == MVT::i32) {
111 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
112 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
113 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
114 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
116 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
117 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
118 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
119 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
121 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
122 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
123 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
124 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
125 setOperationAction(ISD::SELECT, VT, Expand);
126 setOperationAction(ISD::SELECT_CC, VT, Expand);
127 setOperationAction(ISD::VSELECT, VT, Expand);
128 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
129 if (VT.isInteger()) {
130 setOperationAction(ISD::SHL, VT, Custom);
131 setOperationAction(ISD::SRA, VT, Custom);
132 setOperationAction(ISD::SRL, VT, Custom);
135 // Promote all bit-wise operations.
136 if (VT.isInteger() && VT != PromotedBitwiseVT) {
137 setOperationAction(ISD::AND, VT, Promote);
138 AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
139 setOperationAction(ISD::OR, VT, Promote);
140 AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
141 setOperationAction(ISD::XOR, VT, Promote);
142 AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
145 // Neon does not support vector divide/remainder operations.
146 setOperationAction(ISD::SDIV, VT, Expand);
147 setOperationAction(ISD::UDIV, VT, Expand);
148 setOperationAction(ISD::FDIV, VT, Expand);
149 setOperationAction(ISD::SREM, VT, Expand);
150 setOperationAction(ISD::UREM, VT, Expand);
151 setOperationAction(ISD::FREM, VT, Expand);
154 void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
155 addRegisterClass(VT, &ARM::DPRRegClass);
156 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
159 void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
160 addRegisterClass(VT, &ARM::QPRRegClass);
161 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
164 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
165 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
166 return new TargetLoweringObjectFileMachO();
168 return new ARMElfTargetObjectFile();
171 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
172 : TargetLowering(TM, createTLOF(TM)) {
173 Subtarget = &TM.getSubtarget<ARMSubtarget>();
174 RegInfo = TM.getRegisterInfo();
175 Itins = TM.getInstrItineraryData();
177 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
179 if (Subtarget->isTargetIOS()) {
180 // Uses VFP for Thumb libfuncs if available.
181 if (Subtarget->isThumb() && Subtarget->hasVFP2() &&
182 Subtarget->hasARMOps()) {
183 // Single-precision floating-point arithmetic.
184 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
185 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
186 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
187 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
189 // Double-precision floating-point arithmetic.
190 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
191 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
192 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
193 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
195 // Single-precision comparisons.
196 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
197 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
198 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
199 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
200 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
201 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
202 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
203 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
205 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
206 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
207 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
208 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
209 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
210 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
211 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
212 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
214 // Double-precision comparisons.
215 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
216 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
217 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
218 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
219 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
220 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
221 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
222 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
224 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
225 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
226 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
227 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
228 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
229 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
230 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
231 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
233 // Floating-point to integer conversions.
234 // i64 conversions are done via library routines even when generating VFP
235 // instructions, so use the same ones.
236 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
237 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
238 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
239 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
241 // Conversions between floating types.
242 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
243 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
245 // Integer to floating-point conversions.
246 // i64 conversions are done via library routines even when generating VFP
247 // instructions, so use the same ones.
248 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
249 // e.g., __floatunsidf vs. __floatunssidfvfp.
250 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
251 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
252 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
253 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
257 // These libcalls are not available in 32-bit.
258 setLibcallName(RTLIB::SHL_I128, 0);
259 setLibcallName(RTLIB::SRL_I128, 0);
260 setLibcallName(RTLIB::SRA_I128, 0);
262 if (Subtarget->isAAPCS_ABI() && !Subtarget->isTargetDarwin()) {
263 // Double-precision floating-point arithmetic helper functions
264 // RTABI chapter 4.1.2, Table 2
265 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd");
266 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv");
267 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul");
268 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub");
269 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS);
270 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS);
271 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS);
272 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS);
274 // Double-precision floating-point comparison helper functions
275 // RTABI chapter 4.1.2, Table 3
276 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq");
277 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
278 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq");
279 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ);
280 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt");
281 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
282 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple");
283 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
284 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge");
285 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
286 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt");
287 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
288 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun");
289 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
290 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun");
291 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
292 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS);
293 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS);
294 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS);
295 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS);
296 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS);
297 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS);
298 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS);
299 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS);
301 // Single-precision floating-point arithmetic helper functions
302 // RTABI chapter 4.1.2, Table 4
303 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd");
304 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv");
305 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul");
306 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub");
307 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS);
308 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS);
309 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS);
310 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS);
312 // Single-precision floating-point comparison helper functions
313 // RTABI chapter 4.1.2, Table 5
314 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq");
315 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
316 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq");
317 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ);
318 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt");
319 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
320 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple");
321 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
322 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge");
323 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
324 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt");
325 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
326 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun");
327 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
328 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun");
329 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
330 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS);
331 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS);
332 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS);
333 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS);
334 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS);
335 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS);
336 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS);
337 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS);
339 // Floating-point to integer conversions.
340 // RTABI chapter 4.1.2, Table 6
341 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz");
342 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz");
343 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz");
344 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz");
345 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz");
346 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz");
347 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz");
348 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz");
349 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS);
350 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS);
351 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS);
352 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS);
353 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS);
354 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS);
355 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS);
356 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS);
358 // Conversions between floating types.
359 // RTABI chapter 4.1.2, Table 7
360 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f");
361 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d");
362 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS);
363 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS);
365 // Integer to floating-point conversions.
366 // RTABI chapter 4.1.2, Table 8
367 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d");
368 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d");
369 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d");
370 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d");
371 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f");
372 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f");
373 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f");
374 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f");
375 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
376 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
377 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
378 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
379 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
380 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
381 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
382 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
384 // Long long helper functions
385 // RTABI chapter 4.2, Table 9
386 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul");
387 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl");
388 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr");
389 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr");
390 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS);
391 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS);
392 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS);
393 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS);
394 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS);
395 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS);
397 // Integer division functions
398 // RTABI chapter 4.3.1
399 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv");
400 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv");
401 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv");
402 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod");
403 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv");
404 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv");
405 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv");
406 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod");
407 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS);
408 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS);
409 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS);
410 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS);
411 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS);
412 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS);
413 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS);
414 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS);
417 // RTABI chapter 4.3.4
418 setLibcallName(RTLIB::MEMCPY, "__aeabi_memcpy");
419 setLibcallName(RTLIB::MEMMOVE, "__aeabi_memmove");
420 setLibcallName(RTLIB::MEMSET, "__aeabi_memset");
421 setLibcallCallingConv(RTLIB::MEMCPY, CallingConv::ARM_AAPCS);
422 setLibcallCallingConv(RTLIB::MEMMOVE, CallingConv::ARM_AAPCS);
423 setLibcallCallingConv(RTLIB::MEMSET, CallingConv::ARM_AAPCS);
426 // Use divmod compiler-rt calls for iOS 5.0 and later.
427 if (Subtarget->getTargetTriple().isiOS() &&
428 !Subtarget->getTargetTriple().isOSVersionLT(5, 0)) {
429 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
430 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
433 if (Subtarget->isThumb1Only())
434 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
436 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
437 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
438 !Subtarget->isThumb1Only()) {
439 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
440 if (!Subtarget->isFPOnlySP())
441 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
443 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
446 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
447 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
448 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
449 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
450 setTruncStoreAction((MVT::SimpleValueType)VT,
451 (MVT::SimpleValueType)InnerVT, Expand);
452 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
453 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
454 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
457 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
458 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
460 if (Subtarget->hasNEON()) {
461 addDRTypeForNEON(MVT::v2f32);
462 addDRTypeForNEON(MVT::v8i8);
463 addDRTypeForNEON(MVT::v4i16);
464 addDRTypeForNEON(MVT::v2i32);
465 addDRTypeForNEON(MVT::v1i64);
467 addQRTypeForNEON(MVT::v4f32);
468 addQRTypeForNEON(MVT::v2f64);
469 addQRTypeForNEON(MVT::v16i8);
470 addQRTypeForNEON(MVT::v8i16);
471 addQRTypeForNEON(MVT::v4i32);
472 addQRTypeForNEON(MVT::v2i64);
474 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
475 // neither Neon nor VFP support any arithmetic operations on it.
476 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
477 // supported for v4f32.
478 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
479 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
480 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
481 // FIXME: Code duplication: FDIV and FREM are expanded always, see
482 // ARMTargetLowering::addTypeForNEON method for details.
483 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
484 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
485 // FIXME: Create unittest.
486 // In another words, find a way when "copysign" appears in DAG with vector
488 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
489 // FIXME: Code duplication: SETCC has custom operation action, see
490 // ARMTargetLowering::addTypeForNEON method for details.
491 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
492 // FIXME: Create unittest for FNEG and for FABS.
493 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
494 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
495 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
496 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
497 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
498 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
499 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
500 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
501 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
502 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
503 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
504 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
505 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
506 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
507 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
508 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
509 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
510 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
511 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
513 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
514 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
515 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
516 setOperationAction(ISD::FPOWI, MVT::v4f32, Expand);
517 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
518 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
519 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
520 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
521 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
522 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
523 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
524 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
525 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
526 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
527 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
529 // Mark v2f32 intrinsics.
530 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
531 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
532 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
533 setOperationAction(ISD::FPOWI, MVT::v2f32, Expand);
534 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
535 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
536 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
537 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
538 setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
539 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
540 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
541 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
542 setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
543 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
544 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
546 // Neon does not support some operations on v1i64 and v2i64 types.
547 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
548 // Custom handling for some quad-vector types to detect VMULL.
549 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
550 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
551 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
552 // Custom handling for some vector types to avoid expensive expansions
553 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
554 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
555 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
556 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
557 setOperationAction(ISD::SETCC, MVT::v1i64, Expand);
558 setOperationAction(ISD::SETCC, MVT::v2i64, Expand);
559 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
560 // a destination type that is wider than the source, and nor does
561 // it have a FP_TO_[SU]INT instruction with a narrower destination than
563 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
564 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
565 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
566 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
568 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
569 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
571 // NEON does not have single instruction CTPOP for vectors with element
572 // types wider than 8-bits. However, custom lowering can leverage the
573 // v8i8/v16i8 vcnt instruction.
574 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
575 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
576 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
577 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
579 // NEON only has FMA instructions as of VFP4.
580 if (!Subtarget->hasVFP4()) {
581 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
582 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
585 setTargetDAGCombine(ISD::INTRINSIC_VOID);
586 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
587 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
588 setTargetDAGCombine(ISD::SHL);
589 setTargetDAGCombine(ISD::SRL);
590 setTargetDAGCombine(ISD::SRA);
591 setTargetDAGCombine(ISD::SIGN_EXTEND);
592 setTargetDAGCombine(ISD::ZERO_EXTEND);
593 setTargetDAGCombine(ISD::ANY_EXTEND);
594 setTargetDAGCombine(ISD::SELECT_CC);
595 setTargetDAGCombine(ISD::BUILD_VECTOR);
596 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
597 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
598 setTargetDAGCombine(ISD::STORE);
599 setTargetDAGCombine(ISD::FP_TO_SINT);
600 setTargetDAGCombine(ISD::FP_TO_UINT);
601 setTargetDAGCombine(ISD::FDIV);
603 // It is legal to extload from v4i8 to v4i16 or v4i32.
604 MVT Tys[6] = {MVT::v8i8, MVT::v4i8, MVT::v2i8,
605 MVT::v4i16, MVT::v2i16,
607 for (unsigned i = 0; i < 6; ++i) {
608 setLoadExtAction(ISD::EXTLOAD, Tys[i], Legal);
609 setLoadExtAction(ISD::ZEXTLOAD, Tys[i], Legal);
610 setLoadExtAction(ISD::SEXTLOAD, Tys[i], Legal);
614 // ARM and Thumb2 support UMLAL/SMLAL.
615 if (!Subtarget->isThumb1Only())
616 setTargetDAGCombine(ISD::ADDC);
619 computeRegisterProperties();
621 // ARM does not have f32 extending load.
622 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
624 // ARM does not have i1 sign extending load.
625 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
627 // ARM supports all 4 flavors of integer indexed load / store.
628 if (!Subtarget->isThumb1Only()) {
629 for (unsigned im = (unsigned)ISD::PRE_INC;
630 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
631 setIndexedLoadAction(im, MVT::i1, Legal);
632 setIndexedLoadAction(im, MVT::i8, Legal);
633 setIndexedLoadAction(im, MVT::i16, Legal);
634 setIndexedLoadAction(im, MVT::i32, Legal);
635 setIndexedStoreAction(im, MVT::i1, Legal);
636 setIndexedStoreAction(im, MVT::i8, Legal);
637 setIndexedStoreAction(im, MVT::i16, Legal);
638 setIndexedStoreAction(im, MVT::i32, Legal);
642 // i64 operation support.
643 setOperationAction(ISD::MUL, MVT::i64, Expand);
644 setOperationAction(ISD::MULHU, MVT::i32, Expand);
645 if (Subtarget->isThumb1Only()) {
646 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
647 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
649 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
650 || (Subtarget->isThumb2() && !Subtarget->hasThumb2DSP()))
651 setOperationAction(ISD::MULHS, MVT::i32, Expand);
653 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
654 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
655 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
656 setOperationAction(ISD::SRL, MVT::i64, Custom);
657 setOperationAction(ISD::SRA, MVT::i64, Custom);
659 if (!Subtarget->isThumb1Only()) {
660 // FIXME: We should do this for Thumb1 as well.
661 setOperationAction(ISD::ADDC, MVT::i32, Custom);
662 setOperationAction(ISD::ADDE, MVT::i32, Custom);
663 setOperationAction(ISD::SUBC, MVT::i32, Custom);
664 setOperationAction(ISD::SUBE, MVT::i32, Custom);
667 // ARM does not have ROTL.
668 setOperationAction(ISD::ROTL, MVT::i32, Expand);
669 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
670 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
671 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
672 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
674 // These just redirect to CTTZ and CTLZ on ARM.
675 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i32 , Expand);
676 setOperationAction(ISD::CTLZ_ZERO_UNDEF , MVT::i32 , Expand);
678 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
680 // Only ARMv6 has BSWAP.
681 if (!Subtarget->hasV6Ops())
682 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
684 if (!(Subtarget->hasDivide() && Subtarget->isThumb2()) &&
685 !(Subtarget->hasDivideInARMMode() && !Subtarget->isThumb())) {
686 // These are expanded into libcalls if the cpu doesn't have HW divider.
687 setOperationAction(ISD::SDIV, MVT::i32, Expand);
688 setOperationAction(ISD::UDIV, MVT::i32, Expand);
691 // FIXME: Also set divmod for SREM on EABI
692 setOperationAction(ISD::SREM, MVT::i32, Expand);
693 setOperationAction(ISD::UREM, MVT::i32, Expand);
694 // Register based DivRem for AEABI (RTABI 4.2)
695 if (Subtarget->isTargetAEABI()) {
696 setLibcallName(RTLIB::SDIVREM_I8, "__aeabi_idivmod");
697 setLibcallName(RTLIB::SDIVREM_I16, "__aeabi_idivmod");
698 setLibcallName(RTLIB::SDIVREM_I32, "__aeabi_idivmod");
699 setLibcallName(RTLIB::SDIVREM_I64, "__aeabi_ldivmod");
700 setLibcallName(RTLIB::UDIVREM_I8, "__aeabi_uidivmod");
701 setLibcallName(RTLIB::UDIVREM_I16, "__aeabi_uidivmod");
702 setLibcallName(RTLIB::UDIVREM_I32, "__aeabi_uidivmod");
703 setLibcallName(RTLIB::UDIVREM_I64, "__aeabi_uldivmod");
705 setLibcallCallingConv(RTLIB::SDIVREM_I8, CallingConv::ARM_AAPCS);
706 setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::ARM_AAPCS);
707 setLibcallCallingConv(RTLIB::SDIVREM_I32, CallingConv::ARM_AAPCS);
708 setLibcallCallingConv(RTLIB::SDIVREM_I64, CallingConv::ARM_AAPCS);
709 setLibcallCallingConv(RTLIB::UDIVREM_I8, CallingConv::ARM_AAPCS);
710 setLibcallCallingConv(RTLIB::UDIVREM_I16, CallingConv::ARM_AAPCS);
711 setLibcallCallingConv(RTLIB::UDIVREM_I32, CallingConv::ARM_AAPCS);
712 setLibcallCallingConv(RTLIB::UDIVREM_I64, CallingConv::ARM_AAPCS);
714 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
715 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
717 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
718 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
721 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
722 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
723 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
724 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
725 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
727 setOperationAction(ISD::TRAP, MVT::Other, Legal);
729 // Use the default implementation.
730 setOperationAction(ISD::VASTART, MVT::Other, Custom);
731 setOperationAction(ISD::VAARG, MVT::Other, Expand);
732 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
733 setOperationAction(ISD::VAEND, MVT::Other, Expand);
734 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
735 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
737 if (!Subtarget->isTargetDarwin()) {
738 // Non-Darwin platforms may return values in these registers via the
739 // personality function.
740 setExceptionPointerRegister(ARM::R0);
741 setExceptionSelectorRegister(ARM::R1);
744 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
745 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
746 // the default expansion.
747 if (Subtarget->hasAnyDataBarrier() && !Subtarget->isThumb1Only()) {
748 // ATOMIC_FENCE needs custom lowering; the other 32-bit ones are legal and
750 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
751 // Custom lowering for 64-bit ops
752 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
753 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
754 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
755 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
756 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
757 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
758 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
759 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
760 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
761 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
762 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
763 // On v8, we have particularly efficient implementations of atomic fences
764 // if they can be combined with nearby atomic loads and stores.
765 if (!Subtarget->hasV8Ops()) {
766 // Automatically insert fences (dmb ist) around ATOMIC_SWAP etc.
767 setInsertFencesForAtomic(true);
769 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
771 // If there's anything we can use as a barrier, go through custom lowering
773 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other,
774 Subtarget->hasAnyDataBarrier() ? Custom : Expand);
776 // Set them all for expansion, which will force libcalls.
777 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
778 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
779 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
780 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
781 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
782 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
783 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
784 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
785 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
786 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
787 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
788 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
789 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
790 // Unordered/Monotonic case.
791 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
792 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
795 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
797 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
798 if (!Subtarget->hasV6Ops()) {
799 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
800 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
802 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
804 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
805 !Subtarget->isThumb1Only()) {
806 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
807 // iff target supports vfp2.
808 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
809 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
812 // We want to custom lower some of our intrinsics.
813 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
814 if (Subtarget->isTargetDarwin()) {
815 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
816 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
817 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
820 setOperationAction(ISD::SETCC, MVT::i32, Expand);
821 setOperationAction(ISD::SETCC, MVT::f32, Expand);
822 setOperationAction(ISD::SETCC, MVT::f64, Expand);
823 setOperationAction(ISD::SELECT, MVT::i32, Custom);
824 setOperationAction(ISD::SELECT, MVT::f32, Custom);
825 setOperationAction(ISD::SELECT, MVT::f64, Custom);
826 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
827 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
828 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
830 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
831 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
832 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
833 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
834 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
836 // We don't support sin/cos/fmod/copysign/pow
837 setOperationAction(ISD::FSIN, MVT::f64, Expand);
838 setOperationAction(ISD::FSIN, MVT::f32, Expand);
839 setOperationAction(ISD::FCOS, MVT::f32, Expand);
840 setOperationAction(ISD::FCOS, MVT::f64, Expand);
841 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
842 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
843 setOperationAction(ISD::FREM, MVT::f64, Expand);
844 setOperationAction(ISD::FREM, MVT::f32, Expand);
845 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
846 !Subtarget->isThumb1Only()) {
847 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
848 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
850 setOperationAction(ISD::FPOW, MVT::f64, Expand);
851 setOperationAction(ISD::FPOW, MVT::f32, Expand);
853 if (!Subtarget->hasVFP4()) {
854 setOperationAction(ISD::FMA, MVT::f64, Expand);
855 setOperationAction(ISD::FMA, MVT::f32, Expand);
858 // Various VFP goodness
859 if (!TM.Options.UseSoftFloat && !Subtarget->isThumb1Only()) {
860 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
861 if (Subtarget->hasVFP2()) {
862 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
863 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
864 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
865 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
867 // Special handling for half-precision FP.
868 if (!Subtarget->hasFP16()) {
869 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
870 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
874 // Combine sin / cos into one node or libcall if possible.
875 if (Subtarget->hasSinCos()) {
876 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
877 setLibcallName(RTLIB::SINCOS_F64, "sincos");
878 if (Subtarget->getTargetTriple().getOS() == Triple::IOS) {
879 // For iOS, we don't want to the normal expansion of a libcall to
880 // sincos. We want to issue a libcall to __sincos_stret.
881 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
882 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
886 // We have target-specific dag combine patterns for the following nodes:
887 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
888 setTargetDAGCombine(ISD::ADD);
889 setTargetDAGCombine(ISD::SUB);
890 setTargetDAGCombine(ISD::MUL);
891 setTargetDAGCombine(ISD::AND);
892 setTargetDAGCombine(ISD::OR);
893 setTargetDAGCombine(ISD::XOR);
895 if (Subtarget->hasV6Ops())
896 setTargetDAGCombine(ISD::SRL);
898 setStackPointerRegisterToSaveRestore(ARM::SP);
900 if (TM.Options.UseSoftFloat || Subtarget->isThumb1Only() ||
901 !Subtarget->hasVFP2())
902 setSchedulingPreference(Sched::RegPressure);
904 setSchedulingPreference(Sched::Hybrid);
906 //// temporary - rewrite interface to use type
907 MaxStoresPerMemset = 8;
908 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
909 MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
910 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 4 : 2;
911 MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
912 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 4 : 2;
914 // On ARM arguments smaller than 4 bytes are extended, so all arguments
915 // are at least 4 bytes aligned.
916 setMinStackArgumentAlignment(4);
918 // Prefer likely predicted branches to selects on out-of-order cores.
919 PredictableSelectIsExpensive = Subtarget->isLikeA9();
921 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2);
924 static void getExclusiveOperation(unsigned Size, AtomicOrdering Ord,
925 bool isThumb2, unsigned &LdrOpc,
927 static const unsigned LoadBares[4][2] = {{ARM::LDREXB, ARM::t2LDREXB},
928 {ARM::LDREXH, ARM::t2LDREXH},
929 {ARM::LDREX, ARM::t2LDREX},
930 {ARM::LDREXD, ARM::t2LDREXD}};
931 static const unsigned LoadAcqs[4][2] = {{ARM::LDAEXB, ARM::t2LDAEXB},
932 {ARM::LDAEXH, ARM::t2LDAEXH},
933 {ARM::LDAEX, ARM::t2LDAEX},
934 {ARM::LDAEXD, ARM::t2LDAEXD}};
935 static const unsigned StoreBares[4][2] = {{ARM::STREXB, ARM::t2STREXB},
936 {ARM::STREXH, ARM::t2STREXH},
937 {ARM::STREX, ARM::t2STREX},
938 {ARM::STREXD, ARM::t2STREXD}};
939 static const unsigned StoreRels[4][2] = {{ARM::STLEXB, ARM::t2STLEXB},
940 {ARM::STLEXH, ARM::t2STLEXH},
941 {ARM::STLEX, ARM::t2STLEX},
942 {ARM::STLEXD, ARM::t2STLEXD}};
944 const unsigned (*LoadOps)[2], (*StoreOps)[2];
945 if (Ord == Acquire || Ord == AcquireRelease || Ord == SequentiallyConsistent)
950 if (Ord == Release || Ord == AcquireRelease || Ord == SequentiallyConsistent)
951 StoreOps = StoreRels;
953 StoreOps = StoreBares;
955 assert(isPowerOf2_32(Size) && Size <= 8 &&
956 "unsupported size for atomic binary op!");
958 LdrOpc = LoadOps[Log2_32(Size)][isThumb2];
959 StrOpc = StoreOps[Log2_32(Size)][isThumb2];
962 // FIXME: It might make sense to define the representative register class as the
963 // nearest super-register that has a non-null superset. For example, DPR_VFP2 is
964 // a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
965 // SPR's representative would be DPR_VFP2. This should work well if register
966 // pressure tracking were modified such that a register use would increment the
967 // pressure of the register class's representative and all of it's super
968 // classes' representatives transitively. We have not implemented this because
969 // of the difficulty prior to coalescing of modeling operand register classes
970 // due to the common occurrence of cross class copies and subregister insertions
972 std::pair<const TargetRegisterClass*, uint8_t>
973 ARMTargetLowering::findRepresentativeClass(MVT VT) const{
974 const TargetRegisterClass *RRC = 0;
976 switch (VT.SimpleTy) {
978 return TargetLowering::findRepresentativeClass(VT);
979 // Use DPR as representative register class for all floating point
980 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
981 // the cost is 1 for both f32 and f64.
982 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
983 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
984 RRC = &ARM::DPRRegClass;
985 // When NEON is used for SP, only half of the register file is available
986 // because operations that define both SP and DP results will be constrained
987 // to the VFP2 class (D0-D15). We currently model this constraint prior to
988 // coalescing by double-counting the SP regs. See the FIXME above.
989 if (Subtarget->useNEONForSinglePrecisionFP())
992 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
993 case MVT::v4f32: case MVT::v2f64:
994 RRC = &ARM::DPRRegClass;
998 RRC = &ARM::DPRRegClass;
1002 RRC = &ARM::DPRRegClass;
1006 return std::make_pair(RRC, Cost);
1009 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1012 case ARMISD::Wrapper: return "ARMISD::Wrapper";
1013 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
1014 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
1015 case ARMISD::CALL: return "ARMISD::CALL";
1016 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
1017 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
1018 case ARMISD::tCALL: return "ARMISD::tCALL";
1019 case ARMISD::BRCOND: return "ARMISD::BRCOND";
1020 case ARMISD::BR_JT: return "ARMISD::BR_JT";
1021 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
1022 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
1023 case ARMISD::INTRET_FLAG: return "ARMISD::INTRET_FLAG";
1024 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
1025 case ARMISD::CMP: return "ARMISD::CMP";
1026 case ARMISD::CMN: return "ARMISD::CMN";
1027 case ARMISD::CMPZ: return "ARMISD::CMPZ";
1028 case ARMISD::CMPFP: return "ARMISD::CMPFP";
1029 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
1030 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
1031 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
1033 case ARMISD::CMOV: return "ARMISD::CMOV";
1035 case ARMISD::RBIT: return "ARMISD::RBIT";
1037 case ARMISD::FTOSI: return "ARMISD::FTOSI";
1038 case ARMISD::FTOUI: return "ARMISD::FTOUI";
1039 case ARMISD::SITOF: return "ARMISD::SITOF";
1040 case ARMISD::UITOF: return "ARMISD::UITOF";
1042 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
1043 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
1044 case ARMISD::RRX: return "ARMISD::RRX";
1046 case ARMISD::ADDC: return "ARMISD::ADDC";
1047 case ARMISD::ADDE: return "ARMISD::ADDE";
1048 case ARMISD::SUBC: return "ARMISD::SUBC";
1049 case ARMISD::SUBE: return "ARMISD::SUBE";
1051 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
1052 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
1054 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
1055 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
1057 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
1059 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
1061 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
1063 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
1065 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
1067 case ARMISD::VCEQ: return "ARMISD::VCEQ";
1068 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
1069 case ARMISD::VCGE: return "ARMISD::VCGE";
1070 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
1071 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
1072 case ARMISD::VCGEU: return "ARMISD::VCGEU";
1073 case ARMISD::VCGT: return "ARMISD::VCGT";
1074 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
1075 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
1076 case ARMISD::VCGTU: return "ARMISD::VCGTU";
1077 case ARMISD::VTST: return "ARMISD::VTST";
1079 case ARMISD::VSHL: return "ARMISD::VSHL";
1080 case ARMISD::VSHRs: return "ARMISD::VSHRs";
1081 case ARMISD::VSHRu: return "ARMISD::VSHRu";
1082 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
1083 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
1084 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
1085 case ARMISD::VSHRN: return "ARMISD::VSHRN";
1086 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
1087 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
1088 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
1089 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
1090 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
1091 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
1092 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
1093 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
1094 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
1095 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
1096 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
1097 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
1098 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
1099 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
1100 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
1101 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
1102 case ARMISD::VMOVFPIMM: return "ARMISD::VMOVFPIMM";
1103 case ARMISD::VDUP: return "ARMISD::VDUP";
1104 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
1105 case ARMISD::VEXT: return "ARMISD::VEXT";
1106 case ARMISD::VREV64: return "ARMISD::VREV64";
1107 case ARMISD::VREV32: return "ARMISD::VREV32";
1108 case ARMISD::VREV16: return "ARMISD::VREV16";
1109 case ARMISD::VZIP: return "ARMISD::VZIP";
1110 case ARMISD::VUZP: return "ARMISD::VUZP";
1111 case ARMISD::VTRN: return "ARMISD::VTRN";
1112 case ARMISD::VTBL1: return "ARMISD::VTBL1";
1113 case ARMISD::VTBL2: return "ARMISD::VTBL2";
1114 case ARMISD::VMULLs: return "ARMISD::VMULLs";
1115 case ARMISD::VMULLu: return "ARMISD::VMULLu";
1116 case ARMISD::UMLAL: return "ARMISD::UMLAL";
1117 case ARMISD::SMLAL: return "ARMISD::SMLAL";
1118 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
1119 case ARMISD::FMAX: return "ARMISD::FMAX";
1120 case ARMISD::FMIN: return "ARMISD::FMIN";
1121 case ARMISD::VMAXNM: return "ARMISD::VMAX";
1122 case ARMISD::VMINNM: return "ARMISD::VMIN";
1123 case ARMISD::BFI: return "ARMISD::BFI";
1124 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
1125 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
1126 case ARMISD::VBSL: return "ARMISD::VBSL";
1127 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
1128 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
1129 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
1130 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
1131 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
1132 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
1133 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
1134 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
1135 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
1136 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
1137 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
1138 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
1139 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
1140 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
1141 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
1142 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
1143 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
1144 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
1145 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
1146 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
1150 EVT ARMTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1151 if (!VT.isVector()) return getPointerTy();
1152 return VT.changeVectorElementTypeToInteger();
1155 /// getRegClassFor - Return the register class that should be used for the
1156 /// specified value type.
1157 const TargetRegisterClass *ARMTargetLowering::getRegClassFor(MVT VT) const {
1158 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1159 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1160 // load / store 4 to 8 consecutive D registers.
1161 if (Subtarget->hasNEON()) {
1162 if (VT == MVT::v4i64)
1163 return &ARM::QQPRRegClass;
1164 if (VT == MVT::v8i64)
1165 return &ARM::QQQQPRRegClass;
1167 return TargetLowering::getRegClassFor(VT);
1170 // Create a fast isel object.
1172 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1173 const TargetLibraryInfo *libInfo) const {
1174 return ARM::createFastISel(funcInfo, libInfo);
1177 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
1178 /// be used for loads / stores from the global.
1179 unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
1180 return (Subtarget->isThumb1Only() ? 127 : 4095);
1183 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1184 unsigned NumVals = N->getNumValues();
1186 return Sched::RegPressure;
1188 for (unsigned i = 0; i != NumVals; ++i) {
1189 EVT VT = N->getValueType(i);
1190 if (VT == MVT::Glue || VT == MVT::Other)
1192 if (VT.isFloatingPoint() || VT.isVector())
1196 if (!N->isMachineOpcode())
1197 return Sched::RegPressure;
1199 // Load are scheduled for latency even if there instruction itinerary
1200 // is not available.
1201 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1202 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1204 if (MCID.getNumDefs() == 0)
1205 return Sched::RegPressure;
1206 if (!Itins->isEmpty() &&
1207 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1210 return Sched::RegPressure;
1213 //===----------------------------------------------------------------------===//
1215 //===----------------------------------------------------------------------===//
1217 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1218 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1220 default: llvm_unreachable("Unknown condition code!");
1221 case ISD::SETNE: return ARMCC::NE;
1222 case ISD::SETEQ: return ARMCC::EQ;
1223 case ISD::SETGT: return ARMCC::GT;
1224 case ISD::SETGE: return ARMCC::GE;
1225 case ISD::SETLT: return ARMCC::LT;
1226 case ISD::SETLE: return ARMCC::LE;
1227 case ISD::SETUGT: return ARMCC::HI;
1228 case ISD::SETUGE: return ARMCC::HS;
1229 case ISD::SETULT: return ARMCC::LO;
1230 case ISD::SETULE: return ARMCC::LS;
1234 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1235 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1236 ARMCC::CondCodes &CondCode2) {
1237 CondCode2 = ARMCC::AL;
1239 default: llvm_unreachable("Unknown FP condition!");
1241 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1243 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1245 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1246 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1247 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1248 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
1249 case ISD::SETO: CondCode = ARMCC::VC; break;
1250 case ISD::SETUO: CondCode = ARMCC::VS; break;
1251 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1252 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1253 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1255 case ISD::SETULT: CondCode = ARMCC::LT; break;
1257 case ISD::SETULE: CondCode = ARMCC::LE; break;
1259 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1263 //===----------------------------------------------------------------------===//
1264 // Calling Convention Implementation
1265 //===----------------------------------------------------------------------===//
1267 #include "ARMGenCallingConv.inc"
1269 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1270 /// given CallingConvention value.
1271 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1273 bool isVarArg) const {
1276 llvm_unreachable("Unsupported calling convention");
1277 case CallingConv::Fast:
1278 if (Subtarget->hasVFP2() && !isVarArg) {
1279 if (!Subtarget->isAAPCS_ABI())
1280 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1281 // For AAPCS ABI targets, just use VFP variant of the calling convention.
1282 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1285 case CallingConv::C: {
1286 // Use target triple & subtarget features to do actual dispatch.
1287 if (!Subtarget->isAAPCS_ABI())
1288 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1289 else if (Subtarget->hasVFP2() &&
1290 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
1292 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1293 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1295 case CallingConv::ARM_AAPCS_VFP:
1297 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1299 case CallingConv::ARM_AAPCS:
1300 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1301 case CallingConv::ARM_APCS:
1302 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1303 case CallingConv::GHC:
1304 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
1308 /// LowerCallResult - Lower the result values of a call into the
1309 /// appropriate copies out of appropriate physical registers.
1311 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1312 CallingConv::ID CallConv, bool isVarArg,
1313 const SmallVectorImpl<ISD::InputArg> &Ins,
1314 SDLoc dl, SelectionDAG &DAG,
1315 SmallVectorImpl<SDValue> &InVals,
1316 bool isThisReturn, SDValue ThisVal) const {
1318 // Assign locations to each value returned by this call.
1319 SmallVector<CCValAssign, 16> RVLocs;
1320 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1321 getTargetMachine(), RVLocs, *DAG.getContext(), Call);
1322 CCInfo.AnalyzeCallResult(Ins,
1323 CCAssignFnForNode(CallConv, /* Return*/ true,
1326 // Copy all of the result registers out of their specified physreg.
1327 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1328 CCValAssign VA = RVLocs[i];
1330 // Pass 'this' value directly from the argument to return value, to avoid
1331 // reg unit interference
1332 if (i == 0 && isThisReturn) {
1333 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
1334 "unexpected return calling convention register assignment");
1335 InVals.push_back(ThisVal);
1340 if (VA.needsCustom()) {
1341 // Handle f64 or half of a v2f64.
1342 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1344 Chain = Lo.getValue(1);
1345 InFlag = Lo.getValue(2);
1346 VA = RVLocs[++i]; // skip ahead to next loc
1347 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1349 Chain = Hi.getValue(1);
1350 InFlag = Hi.getValue(2);
1351 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1353 if (VA.getLocVT() == MVT::v2f64) {
1354 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1355 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1356 DAG.getConstant(0, MVT::i32));
1358 VA = RVLocs[++i]; // skip ahead to next loc
1359 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1360 Chain = Lo.getValue(1);
1361 InFlag = Lo.getValue(2);
1362 VA = RVLocs[++i]; // skip ahead to next loc
1363 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1364 Chain = Hi.getValue(1);
1365 InFlag = Hi.getValue(2);
1366 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1367 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1368 DAG.getConstant(1, MVT::i32));
1371 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1373 Chain = Val.getValue(1);
1374 InFlag = Val.getValue(2);
1377 switch (VA.getLocInfo()) {
1378 default: llvm_unreachable("Unknown loc info!");
1379 case CCValAssign::Full: break;
1380 case CCValAssign::BCvt:
1381 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1385 InVals.push_back(Val);
1391 /// LowerMemOpCallTo - Store the argument to the stack.
1393 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1394 SDValue StackPtr, SDValue Arg,
1395 SDLoc dl, SelectionDAG &DAG,
1396 const CCValAssign &VA,
1397 ISD::ArgFlagsTy Flags) const {
1398 unsigned LocMemOffset = VA.getLocMemOffset();
1399 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1400 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1401 return DAG.getStore(Chain, dl, Arg, PtrOff,
1402 MachinePointerInfo::getStack(LocMemOffset),
1406 void ARMTargetLowering::PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG,
1407 SDValue Chain, SDValue &Arg,
1408 RegsToPassVector &RegsToPass,
1409 CCValAssign &VA, CCValAssign &NextVA,
1411 SmallVectorImpl<SDValue> &MemOpChains,
1412 ISD::ArgFlagsTy Flags) const {
1414 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1415 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1416 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1418 if (NextVA.isRegLoc())
1419 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1421 assert(NextVA.isMemLoc());
1422 if (StackPtr.getNode() == 0)
1423 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1425 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1431 /// LowerCall - Lowering a call into a callseq_start <-
1432 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1435 ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1436 SmallVectorImpl<SDValue> &InVals) const {
1437 SelectionDAG &DAG = CLI.DAG;
1439 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1440 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1441 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1442 SDValue Chain = CLI.Chain;
1443 SDValue Callee = CLI.Callee;
1444 bool &isTailCall = CLI.IsTailCall;
1445 CallingConv::ID CallConv = CLI.CallConv;
1446 bool doesNotRet = CLI.DoesNotReturn;
1447 bool isVarArg = CLI.IsVarArg;
1449 MachineFunction &MF = DAG.getMachineFunction();
1450 bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1451 bool isThisReturn = false;
1452 bool isSibCall = false;
1453 // Disable tail calls if they're not supported.
1454 if (!EnableARMTailCalls && !Subtarget->supportsTailCall())
1457 // Check if it's really possible to do a tail call.
1458 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1459 isVarArg, isStructRet, MF.getFunction()->hasStructRetAttr(),
1460 Outs, OutVals, Ins, DAG);
1461 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1462 // detected sibcalls.
1469 // Analyze operands of the call, assigning locations to each operand.
1470 SmallVector<CCValAssign, 16> ArgLocs;
1471 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1472 getTargetMachine(), ArgLocs, *DAG.getContext(), Call);
1473 CCInfo.AnalyzeCallOperands(Outs,
1474 CCAssignFnForNode(CallConv, /* Return*/ false,
1477 // Get a count of how many bytes are to be pushed on the stack.
1478 unsigned NumBytes = CCInfo.getNextStackOffset();
1480 // For tail calls, memory operands are available in our caller's stack.
1484 // Adjust the stack pointer for the new arguments...
1485 // These operations are automatically eliminated by the prolog/epilog pass
1487 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
1490 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1492 RegsToPassVector RegsToPass;
1493 SmallVector<SDValue, 8> MemOpChains;
1495 // Walk the register/memloc assignments, inserting copies/loads. In the case
1496 // of tail call optimization, arguments are handled later.
1497 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1499 ++i, ++realArgIdx) {
1500 CCValAssign &VA = ArgLocs[i];
1501 SDValue Arg = OutVals[realArgIdx];
1502 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1503 bool isByVal = Flags.isByVal();
1505 // Promote the value if needed.
1506 switch (VA.getLocInfo()) {
1507 default: llvm_unreachable("Unknown loc info!");
1508 case CCValAssign::Full: break;
1509 case CCValAssign::SExt:
1510 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1512 case CCValAssign::ZExt:
1513 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1515 case CCValAssign::AExt:
1516 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1518 case CCValAssign::BCvt:
1519 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1523 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1524 if (VA.needsCustom()) {
1525 if (VA.getLocVT() == MVT::v2f64) {
1526 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1527 DAG.getConstant(0, MVT::i32));
1528 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1529 DAG.getConstant(1, MVT::i32));
1531 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1532 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1534 VA = ArgLocs[++i]; // skip ahead to next loc
1535 if (VA.isRegLoc()) {
1536 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1537 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1539 assert(VA.isMemLoc());
1541 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1542 dl, DAG, VA, Flags));
1545 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1546 StackPtr, MemOpChains, Flags);
1548 } else if (VA.isRegLoc()) {
1549 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i32) {
1550 assert(VA.getLocVT() == MVT::i32 &&
1551 "unexpected calling convention register assignment");
1552 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&
1553 "unexpected use of 'returned'");
1554 isThisReturn = true;
1556 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1557 } else if (isByVal) {
1558 assert(VA.isMemLoc());
1559 unsigned offset = 0;
1561 // True if this byval aggregate will be split between registers
1563 unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
1564 unsigned CurByValIdx = CCInfo.getInRegsParamsProceed();
1566 if (CurByValIdx < ByValArgsCount) {
1568 unsigned RegBegin, RegEnd;
1569 CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
1571 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1573 for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
1574 SDValue Const = DAG.getConstant(4*i, MVT::i32);
1575 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1576 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
1577 MachinePointerInfo(),
1578 false, false, false,
1579 DAG.InferPtrAlignment(AddArg));
1580 MemOpChains.push_back(Load.getValue(1));
1581 RegsToPass.push_back(std::make_pair(j, Load));
1584 // If parameter size outsides register area, "offset" value
1585 // helps us to calculate stack slot for remained part properly.
1586 offset = RegEnd - RegBegin;
1588 CCInfo.nextInRegsParam();
1591 if (Flags.getByValSize() > 4*offset) {
1592 unsigned LocMemOffset = VA.getLocMemOffset();
1593 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset);
1594 SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
1596 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset);
1597 SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset);
1598 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset,
1600 SDValue AlignNode = DAG.getConstant(Flags.getByValAlign(), MVT::i32);
1602 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
1603 SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
1604 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
1605 Ops, array_lengthof(Ops)));
1607 } else if (!isSibCall) {
1608 assert(VA.isMemLoc());
1610 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1611 dl, DAG, VA, Flags));
1615 if (!MemOpChains.empty())
1616 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1617 &MemOpChains[0], MemOpChains.size());
1619 // Build a sequence of copy-to-reg nodes chained together with token chain
1620 // and flag operands which copy the outgoing args into the appropriate regs.
1622 // Tail call byval lowering might overwrite argument registers so in case of
1623 // tail call optimization the copies to registers are lowered later.
1625 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1626 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1627 RegsToPass[i].second, InFlag);
1628 InFlag = Chain.getValue(1);
1631 // For tail calls lower the arguments to the 'real' stack slot.
1633 // Force all the incoming stack arguments to be loaded from the stack
1634 // before any new outgoing arguments are stored to the stack, because the
1635 // outgoing stack slots may alias the incoming argument stack slots, and
1636 // the alias isn't otherwise explicit. This is slightly more conservative
1637 // than necessary, because it means that each store effectively depends
1638 // on every argument instead of just those arguments it would clobber.
1640 // Do not flag preceding copytoreg stuff together with the following stuff.
1642 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1643 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1644 RegsToPass[i].second, InFlag);
1645 InFlag = Chain.getValue(1);
1650 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1651 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1652 // node so that legalize doesn't hack it.
1653 bool isDirect = false;
1654 bool isARMFunc = false;
1655 bool isLocalARMFunc = false;
1656 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1658 if (EnableARMLongCalls) {
1659 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1660 && "long-calls with non-static relocation model!");
1661 // Handle a global address or an external symbol. If it's not one of
1662 // those, the target's already in a register, so we don't need to do
1664 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1665 const GlobalValue *GV = G->getGlobal();
1666 // Create a constant pool entry for the callee address
1667 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1668 ARMConstantPoolValue *CPV =
1669 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
1671 // Get the address of the callee into a register
1672 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1673 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1674 Callee = DAG.getLoad(getPointerTy(), dl,
1675 DAG.getEntryNode(), CPAddr,
1676 MachinePointerInfo::getConstantPool(),
1677 false, false, false, 0);
1678 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1679 const char *Sym = S->getSymbol();
1681 // Create a constant pool entry for the callee address
1682 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1683 ARMConstantPoolValue *CPV =
1684 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1685 ARMPCLabelIndex, 0);
1686 // Get the address of the callee into a register
1687 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1688 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1689 Callee = DAG.getLoad(getPointerTy(), dl,
1690 DAG.getEntryNode(), CPAddr,
1691 MachinePointerInfo::getConstantPool(),
1692 false, false, false, 0);
1694 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1695 const GlobalValue *GV = G->getGlobal();
1697 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1698 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1699 getTargetMachine().getRelocationModel() != Reloc::Static;
1700 isARMFunc = !Subtarget->isThumb() || isStub;
1701 // ARM call to a local ARM function is predicable.
1702 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1703 // tBX takes a register source operand.
1704 if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1705 assert(Subtarget->isTargetDarwin() && "WrapperPIC use on non-Darwin?");
1706 Callee = DAG.getNode(ARMISD::WrapperPIC, dl, getPointerTy(),
1707 DAG.getTargetGlobalAddress(GV, dl, getPointerTy()));
1709 // On ELF targets for PIC code, direct calls should go through the PLT
1710 unsigned OpFlags = 0;
1711 if (Subtarget->isTargetELF() &&
1712 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1713 OpFlags = ARMII::MO_PLT;
1714 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1716 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1718 bool isStub = Subtarget->isTargetDarwin() &&
1719 getTargetMachine().getRelocationModel() != Reloc::Static;
1720 isARMFunc = !Subtarget->isThumb() || isStub;
1721 // tBX takes a register source operand.
1722 const char *Sym = S->getSymbol();
1723 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1724 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1725 ARMConstantPoolValue *CPV =
1726 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1727 ARMPCLabelIndex, 4);
1728 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1729 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1730 Callee = DAG.getLoad(getPointerTy(), dl,
1731 DAG.getEntryNode(), CPAddr,
1732 MachinePointerInfo::getConstantPool(),
1733 false, false, false, 0);
1734 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1735 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1736 getPointerTy(), Callee, PICLabel);
1738 unsigned OpFlags = 0;
1739 // On ELF targets for PIC code, direct calls should go through the PLT
1740 if (Subtarget->isTargetELF() &&
1741 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1742 OpFlags = ARMII::MO_PLT;
1743 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1747 // FIXME: handle tail calls differently.
1749 bool HasMinSizeAttr = Subtarget->isMinSize();
1750 if (Subtarget->isThumb()) {
1751 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1752 CallOpc = ARMISD::CALL_NOLINK;
1754 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1756 if (!isDirect && !Subtarget->hasV5TOps())
1757 CallOpc = ARMISD::CALL_NOLINK;
1758 else if (doesNotRet && isDirect && Subtarget->hasRAS() &&
1759 // Emit regular call when code size is the priority
1761 // "mov lr, pc; b _foo" to avoid confusing the RSP
1762 CallOpc = ARMISD::CALL_NOLINK;
1764 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
1767 std::vector<SDValue> Ops;
1768 Ops.push_back(Chain);
1769 Ops.push_back(Callee);
1771 // Add argument registers to the end of the list so that they are known live
1773 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1774 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1775 RegsToPass[i].second.getValueType()));
1777 // Add a register mask operand representing the call-preserved registers.
1779 const uint32_t *Mask;
1780 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
1781 const ARMBaseRegisterInfo *ARI = static_cast<const ARMBaseRegisterInfo*>(TRI);
1783 // For 'this' returns, use the R0-preserving mask if applicable
1784 Mask = ARI->getThisReturnPreservedMask(CallConv);
1786 // Set isThisReturn to false if the calling convention is not one that
1787 // allows 'returned' to be modeled in this way, so LowerCallResult does
1788 // not try to pass 'this' straight through
1789 isThisReturn = false;
1790 Mask = ARI->getCallPreservedMask(CallConv);
1793 Mask = ARI->getCallPreservedMask(CallConv);
1795 assert(Mask && "Missing call preserved mask for calling convention");
1796 Ops.push_back(DAG.getRegisterMask(Mask));
1799 if (InFlag.getNode())
1800 Ops.push_back(InFlag);
1802 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1804 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1806 // Returns a chain and a flag for retval copy to use.
1807 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1808 InFlag = Chain.getValue(1);
1810 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1811 DAG.getIntPtrConstant(0, true), InFlag, dl);
1813 InFlag = Chain.getValue(1);
1815 // Handle result values, copying them out of physregs into vregs that we
1817 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
1818 InVals, isThisReturn,
1819 isThisReturn ? OutVals[0] : SDValue());
1822 /// HandleByVal - Every parameter *after* a byval parameter is passed
1823 /// on the stack. Remember the next parameter register to allocate,
1824 /// and then confiscate the rest of the parameter registers to insure
1827 ARMTargetLowering::HandleByVal(
1828 CCState *State, unsigned &size, unsigned Align) const {
1829 unsigned reg = State->AllocateReg(GPRArgRegs, 4);
1830 assert((State->getCallOrPrologue() == Prologue ||
1831 State->getCallOrPrologue() == Call) &&
1832 "unhandled ParmContext");
1834 // For in-prologue parameters handling, we also introduce stack offset
1835 // for byval registers: see CallingConvLower.cpp, CCState::HandleByVal.
1836 // This behaviour outsides AAPCS rules (5.5 Parameters Passing) of how
1837 // NSAA should be evaluted (NSAA means "next stacked argument address").
1838 // So: NextStackOffset = NSAAOffset + SizeOfByValParamsStoredInRegs.
1839 // Then: NSAAOffset = NextStackOffset - SizeOfByValParamsStoredInRegs.
1840 unsigned NSAAOffset = State->getNextStackOffset();
1841 if (State->getCallOrPrologue() != Call) {
1842 for (unsigned i = 0, e = State->getInRegsParamsCount(); i != e; ++i) {
1844 State->getInRegsParamInfo(i, RB, RE);
1845 assert(NSAAOffset >= (RE-RB)*4 &&
1846 "Stack offset for byval regs doesn't introduced anymore?");
1847 NSAAOffset -= (RE-RB)*4;
1850 if ((ARM::R0 <= reg) && (reg <= ARM::R3)) {
1851 if (Subtarget->isAAPCS_ABI() && Align > 4) {
1852 unsigned AlignInRegs = Align / 4;
1853 unsigned Waste = (ARM::R4 - reg) % AlignInRegs;
1854 for (unsigned i = 0; i < Waste; ++i)
1855 reg = State->AllocateReg(GPRArgRegs, 4);
1858 unsigned excess = 4 * (ARM::R4 - reg);
1860 // Special case when NSAA != SP and parameter size greater than size of
1861 // all remained GPR regs. In that case we can't split parameter, we must
1862 // send it to stack. We also must set NCRN to R4, so waste all
1863 // remained registers.
1864 if (Subtarget->isAAPCS_ABI() && NSAAOffset != 0 && size > excess) {
1865 while (State->AllocateReg(GPRArgRegs, 4))
1870 // First register for byval parameter is the first register that wasn't
1871 // allocated before this method call, so it would be "reg".
1872 // If parameter is small enough to be saved in range [reg, r4), then
1873 // the end (first after last) register would be reg + param-size-in-regs,
1874 // else parameter would be splitted between registers and stack,
1875 // end register would be r4 in this case.
1876 unsigned ByValRegBegin = reg;
1877 unsigned ByValRegEnd = (size < excess) ? reg + size/4 : (unsigned)ARM::R4;
1878 State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
1879 // Note, first register is allocated in the beginning of function already,
1880 // allocate remained amount of registers we need.
1881 for (unsigned i = reg+1; i != ByValRegEnd; ++i)
1882 State->AllocateReg(GPRArgRegs, 4);
1883 // At a call site, a byval parameter that is split between
1884 // registers and memory needs its size truncated here. In a
1885 // function prologue, such byval parameters are reassembled in
1886 // memory, and are not truncated.
1887 if (State->getCallOrPrologue() == Call) {
1888 // Make remained size equal to 0 in case, when
1889 // the whole structure may be stored into registers.
1899 /// MatchingStackOffset - Return true if the given stack call argument is
1900 /// already available in the same position (relatively) of the caller's
1901 /// incoming argument stack.
1903 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1904 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1905 const TargetInstrInfo *TII) {
1906 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1908 if (Arg.getOpcode() == ISD::CopyFromReg) {
1909 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1910 if (!TargetRegisterInfo::isVirtualRegister(VR))
1912 MachineInstr *Def = MRI->getVRegDef(VR);
1915 if (!Flags.isByVal()) {
1916 if (!TII->isLoadFromStackSlot(Def, FI))
1921 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1922 if (Flags.isByVal())
1923 // ByVal argument is passed in as a pointer but it's now being
1924 // dereferenced. e.g.
1925 // define @foo(%struct.X* %A) {
1926 // tail call @bar(%struct.X* byval %A)
1929 SDValue Ptr = Ld->getBasePtr();
1930 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1933 FI = FINode->getIndex();
1937 assert(FI != INT_MAX);
1938 if (!MFI->isFixedObjectIndex(FI))
1940 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1943 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1944 /// for tail call optimization. Targets which want to do tail call
1945 /// optimization should implement this function.
1947 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1948 CallingConv::ID CalleeCC,
1950 bool isCalleeStructRet,
1951 bool isCallerStructRet,
1952 const SmallVectorImpl<ISD::OutputArg> &Outs,
1953 const SmallVectorImpl<SDValue> &OutVals,
1954 const SmallVectorImpl<ISD::InputArg> &Ins,
1955 SelectionDAG& DAG) const {
1956 const Function *CallerF = DAG.getMachineFunction().getFunction();
1957 CallingConv::ID CallerCC = CallerF->getCallingConv();
1958 bool CCMatch = CallerCC == CalleeCC;
1960 // Look for obvious safe cases to perform tail call optimization that do not
1961 // require ABI changes. This is what gcc calls sibcall.
1963 // Do not sibcall optimize vararg calls unless the call site is not passing
1965 if (isVarArg && !Outs.empty())
1968 // Exception-handling functions need a special set of instructions to indicate
1969 // a return to the hardware. Tail-calling another function would probably
1971 if (CallerF->hasFnAttribute("interrupt"))
1974 // Also avoid sibcall optimization if either caller or callee uses struct
1975 // return semantics.
1976 if (isCalleeStructRet || isCallerStructRet)
1979 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1980 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
1981 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
1982 // support in the assembler and linker to be used. This would need to be
1983 // fixed to fully support tail calls in Thumb1.
1985 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1986 // LR. This means if we need to reload LR, it takes an extra instructions,
1987 // which outweighs the value of the tail call; but here we don't know yet
1988 // whether LR is going to be used. Probably the right approach is to
1989 // generate the tail call here and turn it back into CALL/RET in
1990 // emitEpilogue if LR is used.
1992 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1993 // but we need to make sure there are enough registers; the only valid
1994 // registers are the 4 used for parameters. We don't currently do this
1996 if (Subtarget->isThumb1Only())
1999 // If the calling conventions do not match, then we'd better make sure the
2000 // results are returned in the same way as what the caller expects.
2002 SmallVector<CCValAssign, 16> RVLocs1;
2003 ARMCCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2004 getTargetMachine(), RVLocs1, *DAG.getContext(), Call);
2005 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
2007 SmallVector<CCValAssign, 16> RVLocs2;
2008 ARMCCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2009 getTargetMachine(), RVLocs2, *DAG.getContext(), Call);
2010 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
2012 if (RVLocs1.size() != RVLocs2.size())
2014 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2015 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2017 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2019 if (RVLocs1[i].isRegLoc()) {
2020 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2023 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2029 // If Caller's vararg or byval argument has been split between registers and
2030 // stack, do not perform tail call, since part of the argument is in caller's
2032 const ARMFunctionInfo *AFI_Caller = DAG.getMachineFunction().
2033 getInfo<ARMFunctionInfo>();
2034 if (AFI_Caller->getArgRegsSaveSize())
2037 // If the callee takes no arguments then go on to check the results of the
2039 if (!Outs.empty()) {
2040 // Check if stack adjustment is needed. For now, do not do this if any
2041 // argument is passed on the stack.
2042 SmallVector<CCValAssign, 16> ArgLocs;
2043 ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2044 getTargetMachine(), ArgLocs, *DAG.getContext(), Call);
2045 CCInfo.AnalyzeCallOperands(Outs,
2046 CCAssignFnForNode(CalleeCC, false, isVarArg));
2047 if (CCInfo.getNextStackOffset()) {
2048 MachineFunction &MF = DAG.getMachineFunction();
2050 // Check if the arguments are already laid out in the right way as
2051 // the caller's fixed stack objects.
2052 MachineFrameInfo *MFI = MF.getFrameInfo();
2053 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2054 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2055 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2057 ++i, ++realArgIdx) {
2058 CCValAssign &VA = ArgLocs[i];
2059 EVT RegVT = VA.getLocVT();
2060 SDValue Arg = OutVals[realArgIdx];
2061 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2062 if (VA.getLocInfo() == CCValAssign::Indirect)
2064 if (VA.needsCustom()) {
2065 // f64 and vector types are split into multiple registers or
2066 // register/stack-slot combinations. The types will not match
2067 // the registers; give up on memory f64 refs until we figure
2068 // out what to do about this.
2071 if (!ArgLocs[++i].isRegLoc())
2073 if (RegVT == MVT::v2f64) {
2074 if (!ArgLocs[++i].isRegLoc())
2076 if (!ArgLocs[++i].isRegLoc())
2079 } else if (!VA.isRegLoc()) {
2080 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2092 ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2093 MachineFunction &MF, bool isVarArg,
2094 const SmallVectorImpl<ISD::OutputArg> &Outs,
2095 LLVMContext &Context) const {
2096 SmallVector<CCValAssign, 16> RVLocs;
2097 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context);
2098 return CCInfo.CheckReturn(Outs, CCAssignFnForNode(CallConv, /*Return=*/true,
2102 static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
2103 SDLoc DL, SelectionDAG &DAG) {
2104 const MachineFunction &MF = DAG.getMachineFunction();
2105 const Function *F = MF.getFunction();
2107 StringRef IntKind = F->getFnAttribute("interrupt").getValueAsString();
2109 // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset
2110 // version of the "preferred return address". These offsets affect the return
2111 // instruction if this is a return from PL1 without hypervisor extensions.
2112 // IRQ/FIQ: +4 "subs pc, lr, #4"
2113 // SWI: 0 "subs pc, lr, #0"
2114 // ABORT: +4 "subs pc, lr, #4"
2115 // UNDEF: +4/+2 "subs pc, lr, #0"
2116 // UNDEF varies depending on where the exception came from ARM or Thumb
2117 // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0.
2120 if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" ||
2123 else if (IntKind == "SWI" || IntKind == "UNDEF")
2126 report_fatal_error("Unsupported interrupt attribute. If present, value "
2127 "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF");
2129 RetOps.insert(RetOps.begin() + 1, DAG.getConstant(LROffset, MVT::i32, false));
2131 return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other,
2132 RetOps.data(), RetOps.size());
2136 ARMTargetLowering::LowerReturn(SDValue Chain,
2137 CallingConv::ID CallConv, bool isVarArg,
2138 const SmallVectorImpl<ISD::OutputArg> &Outs,
2139 const SmallVectorImpl<SDValue> &OutVals,
2140 SDLoc dl, SelectionDAG &DAG) const {
2142 // CCValAssign - represent the assignment of the return value to a location.
2143 SmallVector<CCValAssign, 16> RVLocs;
2145 // CCState - Info about the registers and stack slots.
2146 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2147 getTargetMachine(), RVLocs, *DAG.getContext(), Call);
2149 // Analyze outgoing return values.
2150 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
2154 SmallVector<SDValue, 4> RetOps;
2155 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2157 // Copy the result values into the output registers.
2158 for (unsigned i = 0, realRVLocIdx = 0;
2160 ++i, ++realRVLocIdx) {
2161 CCValAssign &VA = RVLocs[i];
2162 assert(VA.isRegLoc() && "Can only return in registers!");
2164 SDValue Arg = OutVals[realRVLocIdx];
2166 switch (VA.getLocInfo()) {
2167 default: llvm_unreachable("Unknown loc info!");
2168 case CCValAssign::Full: break;
2169 case CCValAssign::BCvt:
2170 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2174 if (VA.needsCustom()) {
2175 if (VA.getLocVT() == MVT::v2f64) {
2176 // Extract the first half and return it in two registers.
2177 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2178 DAG.getConstant(0, MVT::i32));
2179 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
2180 DAG.getVTList(MVT::i32, MVT::i32), Half);
2182 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
2183 Flag = Chain.getValue(1);
2184 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2185 VA = RVLocs[++i]; // skip ahead to next loc
2186 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2187 HalfGPRs.getValue(1), Flag);
2188 Flag = Chain.getValue(1);
2189 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2190 VA = RVLocs[++i]; // skip ahead to next loc
2192 // Extract the 2nd half and fall through to handle it as an f64 value.
2193 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2194 DAG.getConstant(1, MVT::i32));
2196 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
2198 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2199 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
2200 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
2201 Flag = Chain.getValue(1);
2202 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2203 VA = RVLocs[++i]; // skip ahead to next loc
2204 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
2207 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
2209 // Guarantee that all emitted copies are
2210 // stuck together, avoiding something bad.
2211 Flag = Chain.getValue(1);
2212 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2215 // Update chain and glue.
2218 RetOps.push_back(Flag);
2220 // CPUs which aren't M-class use a special sequence to return from
2221 // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
2222 // though we use "subs pc, lr, #N").
2224 // M-class CPUs actually use a normal return sequence with a special
2225 // (hardware-provided) value in LR, so the normal code path works.
2226 if (DAG.getMachineFunction().getFunction()->hasFnAttribute("interrupt") &&
2227 !Subtarget->isMClass()) {
2228 if (Subtarget->isThumb1Only())
2229 report_fatal_error("interrupt attribute is not supported in Thumb1");
2230 return LowerInterruptReturn(RetOps, dl, DAG);
2233 return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other,
2234 RetOps.data(), RetOps.size());
2237 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2238 if (N->getNumValues() != 1)
2240 if (!N->hasNUsesOfValue(1, 0))
2243 SDValue TCChain = Chain;
2244 SDNode *Copy = *N->use_begin();
2245 if (Copy->getOpcode() == ISD::CopyToReg) {
2246 // If the copy has a glue operand, we conservatively assume it isn't safe to
2247 // perform a tail call.
2248 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2250 TCChain = Copy->getOperand(0);
2251 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
2252 SDNode *VMov = Copy;
2253 // f64 returned in a pair of GPRs.
2254 SmallPtrSet<SDNode*, 2> Copies;
2255 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2257 if (UI->getOpcode() != ISD::CopyToReg)
2261 if (Copies.size() > 2)
2264 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2266 SDValue UseChain = UI->getOperand(0);
2267 if (Copies.count(UseChain.getNode()))
2274 } else if (Copy->getOpcode() == ISD::BITCAST) {
2275 // f32 returned in a single GPR.
2276 if (!Copy->hasOneUse())
2278 Copy = *Copy->use_begin();
2279 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
2281 TCChain = Copy->getOperand(0);
2286 bool HasRet = false;
2287 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2289 if (UI->getOpcode() != ARMISD::RET_FLAG &&
2290 UI->getOpcode() != ARMISD::INTRET_FLAG)
2302 bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2303 if (!EnableARMTailCalls && !Subtarget->supportsTailCall())
2306 if (!CI->isTailCall())
2309 return !Subtarget->isThumb1Only();
2312 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
2313 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
2314 // one of the above mentioned nodes. It has to be wrapped because otherwise
2315 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
2316 // be used to form addressing mode. These wrapped nodes will be selected
2318 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
2319 EVT PtrVT = Op.getValueType();
2320 // FIXME there is no actual debug info here
2322 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2324 if (CP->isMachineConstantPoolEntry())
2325 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
2326 CP->getAlignment());
2328 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
2329 CP->getAlignment());
2330 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
2333 unsigned ARMTargetLowering::getJumpTableEncoding() const {
2334 return MachineJumpTableInfo::EK_Inline;
2337 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
2338 SelectionDAG &DAG) const {
2339 MachineFunction &MF = DAG.getMachineFunction();
2340 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2341 unsigned ARMPCLabelIndex = 0;
2343 EVT PtrVT = getPointerTy();
2344 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
2345 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2347 if (RelocM == Reloc::Static) {
2348 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
2350 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2351 ARMPCLabelIndex = AFI->createPICLabelUId();
2352 ARMConstantPoolValue *CPV =
2353 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
2354 ARMCP::CPBlockAddress, PCAdj);
2355 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2357 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
2358 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
2359 MachinePointerInfo::getConstantPool(),
2360 false, false, false, 0);
2361 if (RelocM == Reloc::Static)
2363 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2364 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
2367 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
2369 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
2370 SelectionDAG &DAG) const {
2372 EVT PtrVT = getPointerTy();
2373 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2374 MachineFunction &MF = DAG.getMachineFunction();
2375 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2376 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2377 ARMConstantPoolValue *CPV =
2378 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2379 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
2380 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2381 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
2382 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
2383 MachinePointerInfo::getConstantPool(),
2384 false, false, false, 0);
2385 SDValue Chain = Argument.getValue(1);
2387 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2388 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
2390 // call __tls_get_addr.
2393 Entry.Node = Argument;
2394 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
2395 Args.push_back(Entry);
2396 // FIXME: is there useful debug info available here?
2397 TargetLowering::CallLoweringInfo CLI(Chain,
2398 (Type *) Type::getInt32Ty(*DAG.getContext()),
2399 false, false, false, false,
2400 0, CallingConv::C, /*isTailCall=*/false,
2401 /*doesNotRet=*/false, /*isReturnValueUsed=*/true,
2402 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
2403 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2404 return CallResult.first;
2407 // Lower ISD::GlobalTLSAddress using the "initial exec" or
2408 // "local exec" model.
2410 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
2412 TLSModel::Model model) const {
2413 const GlobalValue *GV = GA->getGlobal();
2416 SDValue Chain = DAG.getEntryNode();
2417 EVT PtrVT = getPointerTy();
2418 // Get the Thread Pointer
2419 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2421 if (model == TLSModel::InitialExec) {
2422 MachineFunction &MF = DAG.getMachineFunction();
2423 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2424 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2425 // Initial exec model.
2426 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2427 ARMConstantPoolValue *CPV =
2428 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2429 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
2431 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2432 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2433 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2434 MachinePointerInfo::getConstantPool(),
2435 false, false, false, 0);
2436 Chain = Offset.getValue(1);
2438 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2439 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
2441 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2442 MachinePointerInfo::getConstantPool(),
2443 false, false, false, 0);
2446 assert(model == TLSModel::LocalExec);
2447 ARMConstantPoolValue *CPV =
2448 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
2449 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2450 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2451 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2452 MachinePointerInfo::getConstantPool(),
2453 false, false, false, 0);
2456 // The address of the thread local variable is the add of the thread
2457 // pointer with the offset of the variable.
2458 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
2462 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
2463 // TODO: implement the "local dynamic" model
2464 assert(Subtarget->isTargetELF() &&
2465 "TLS not implemented for non-ELF targets");
2466 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2468 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
2471 case TLSModel::GeneralDynamic:
2472 case TLSModel::LocalDynamic:
2473 return LowerToTLSGeneralDynamicModel(GA, DAG);
2474 case TLSModel::InitialExec:
2475 case TLSModel::LocalExec:
2476 return LowerToTLSExecModels(GA, DAG, model);
2478 llvm_unreachable("bogus TLS model");
2481 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
2482 SelectionDAG &DAG) const {
2483 EVT PtrVT = getPointerTy();
2485 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2486 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2487 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
2488 ARMConstantPoolValue *CPV =
2489 ARMConstantPoolConstant::Create(GV,
2490 UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
2491 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2492 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2493 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
2495 MachinePointerInfo::getConstantPool(),
2496 false, false, false, 0);
2497 SDValue Chain = Result.getValue(1);
2498 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
2499 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
2501 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
2502 MachinePointerInfo::getGOT(),
2503 false, false, false, 0);
2507 // If we have T2 ops, we can materialize the address directly via movt/movw
2508 // pair. This is always cheaper.
2509 if (Subtarget->useMovt()) {
2511 // FIXME: Once remat is capable of dealing with instructions with register
2512 // operands, expand this into two nodes.
2513 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2514 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2516 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2517 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2518 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2519 MachinePointerInfo::getConstantPool(),
2520 false, false, false, 0);
2524 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
2525 SelectionDAG &DAG) const {
2526 EVT PtrVT = getPointerTy();
2528 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2529 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2531 if (Subtarget->useMovt())
2534 // FIXME: Once remat is capable of dealing with instructions with register
2535 // operands, expand this into multiple nodes
2537 RelocM == Reloc::PIC_ ? ARMISD::WrapperPIC : ARMISD::Wrapper;
2539 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
2540 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
2542 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2543 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
2544 MachinePointerInfo::getGOT(), false, false, false, 0);
2548 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
2549 SelectionDAG &DAG) const {
2550 assert(Subtarget->isTargetELF() &&
2551 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
2552 MachineFunction &MF = DAG.getMachineFunction();
2553 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2554 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2555 EVT PtrVT = getPointerTy();
2557 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2558 ARMConstantPoolValue *CPV =
2559 ARMConstantPoolSymbol::Create(*DAG.getContext(), "_GLOBAL_OFFSET_TABLE_",
2560 ARMPCLabelIndex, PCAdj);
2561 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2562 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2563 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2564 MachinePointerInfo::getConstantPool(),
2565 false, false, false, 0);
2566 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2567 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2571 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
2573 SDValue Val = DAG.getConstant(0, MVT::i32);
2574 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
2575 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
2576 Op.getOperand(1), Val);
2580 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
2582 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2583 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
2587 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
2588 const ARMSubtarget *Subtarget) const {
2589 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2592 default: return SDValue(); // Don't custom lower most intrinsics.
2593 case Intrinsic::arm_thread_pointer: {
2594 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2595 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2597 case Intrinsic::eh_sjlj_lsda: {
2598 MachineFunction &MF = DAG.getMachineFunction();
2599 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2600 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2601 EVT PtrVT = getPointerTy();
2602 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2604 unsigned PCAdj = (RelocM != Reloc::PIC_)
2605 ? 0 : (Subtarget->isThumb() ? 4 : 8);
2606 ARMConstantPoolValue *CPV =
2607 ARMConstantPoolConstant::Create(MF.getFunction(), ARMPCLabelIndex,
2608 ARMCP::CPLSDA, PCAdj);
2609 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2610 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2612 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2613 MachinePointerInfo::getConstantPool(),
2614 false, false, false, 0);
2616 if (RelocM == Reloc::PIC_) {
2617 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2618 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2622 case Intrinsic::arm_neon_vmulls:
2623 case Intrinsic::arm_neon_vmullu: {
2624 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
2625 ? ARMISD::VMULLs : ARMISD::VMULLu;
2626 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
2627 Op.getOperand(1), Op.getOperand(2));
2632 static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
2633 const ARMSubtarget *Subtarget) {
2634 // FIXME: handle "fence singlethread" more efficiently.
2636 if (!Subtarget->hasDataBarrier()) {
2637 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2638 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2640 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2641 "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!");
2642 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2643 DAG.getConstant(0, MVT::i32));
2646 ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
2647 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
2648 unsigned Domain = ARM_MB::ISH;
2649 if (Subtarget->isMClass()) {
2650 // Only a full system barrier exists in the M-class architectures.
2651 Domain = ARM_MB::SY;
2652 } else if (Subtarget->isSwift() && Ord == Release) {
2653 // Swift happens to implement ISHST barriers in a way that's compatible with
2654 // Release semantics but weaker than ISH so we'd be fools not to use
2655 // it. Beware: other processors probably don't!
2656 Domain = ARM_MB::ISHST;
2659 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
2660 DAG.getConstant(Intrinsic::arm_dmb, MVT::i32),
2661 DAG.getConstant(Domain, MVT::i32));
2664 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2665 const ARMSubtarget *Subtarget) {
2666 // ARM pre v5TE and Thumb1 does not have preload instructions.
2667 if (!(Subtarget->isThumb2() ||
2668 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2669 // Just preserve the chain.
2670 return Op.getOperand(0);
2673 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
2675 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
2676 // ARMv7 with MP extension has PLDW.
2677 return Op.getOperand(0);
2679 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
2680 if (Subtarget->isThumb()) {
2682 isRead = ~isRead & 1;
2683 isData = ~isData & 1;
2686 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2687 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32),
2688 DAG.getConstant(isData, MVT::i32));
2691 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2692 MachineFunction &MF = DAG.getMachineFunction();
2693 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2695 // vastart just stores the address of the VarArgsFrameIndex slot into the
2696 // memory location argument.
2698 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2699 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2700 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2701 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2702 MachinePointerInfo(SV), false, false, 0);
2706 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2707 SDValue &Root, SelectionDAG &DAG,
2709 MachineFunction &MF = DAG.getMachineFunction();
2710 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2712 const TargetRegisterClass *RC;
2713 if (AFI->isThumb1OnlyFunction())
2714 RC = &ARM::tGPRRegClass;
2716 RC = &ARM::GPRRegClass;
2718 // Transform the arguments stored in physical registers into virtual ones.
2719 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2720 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2723 if (NextVA.isMemLoc()) {
2724 MachineFrameInfo *MFI = MF.getFrameInfo();
2725 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2727 // Create load node to retrieve arguments from the stack.
2728 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2729 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2730 MachinePointerInfo::getFixedStack(FI),
2731 false, false, false, 0);
2733 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2734 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2737 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2741 ARMTargetLowering::computeRegArea(CCState &CCInfo, MachineFunction &MF,
2742 unsigned InRegsParamRecordIdx,
2744 unsigned &ArgRegsSize,
2745 unsigned &ArgRegsSaveSize)
2748 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
2749 unsigned RBegin, REnd;
2750 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
2751 NumGPRs = REnd - RBegin;
2753 unsigned int firstUnalloced;
2754 firstUnalloced = CCInfo.getFirstUnallocated(GPRArgRegs,
2755 sizeof(GPRArgRegs) /
2756 sizeof(GPRArgRegs[0]));
2757 NumGPRs = (firstUnalloced <= 3) ? (4 - firstUnalloced) : 0;
2760 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
2761 ArgRegsSize = NumGPRs * 4;
2763 // If parameter is split between stack and GPRs...
2764 if (NumGPRs && Align == 8 &&
2765 (ArgRegsSize < ArgSize ||
2766 InRegsParamRecordIdx >= CCInfo.getInRegsParamsCount())) {
2767 // Add padding for part of param recovered from GPRs, so
2768 // its last byte must be at address K*8 - 1.
2769 // We need to do it, since remained (stack) part of parameter has
2770 // stack alignment, and we need to "attach" "GPRs head" without gaps
2773 // |---- 8 bytes block ----| |---- 8 bytes block ----| |---- 8 bytes...
2774 // [ [padding] [GPRs head] ] [ Tail passed via stack ....
2776 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2778 ((ArgRegsSize + AFI->getArgRegsSaveSize() + Align - 1) & ~(Align-1)) -
2779 (ArgRegsSize + AFI->getArgRegsSaveSize());
2780 ArgRegsSaveSize = ArgRegsSize + Padding;
2782 // We don't need to extend regs save size for byval parameters if they
2783 // are passed via GPRs only.
2784 ArgRegsSaveSize = ArgRegsSize;
2787 // The remaining GPRs hold either the beginning of variable-argument
2788 // data, or the beginning of an aggregate passed by value (usually
2789 // byval). Either way, we allocate stack slots adjacent to the data
2790 // provided by our caller, and store the unallocated registers there.
2791 // If this is a variadic function, the va_list pointer will begin with
2792 // these values; otherwise, this reassembles a (byval) structure that
2793 // was split between registers and memory.
2794 // Return: The frame index registers were stored into.
2796 ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
2797 SDLoc dl, SDValue &Chain,
2798 const Value *OrigArg,
2799 unsigned InRegsParamRecordIdx,
2800 unsigned OffsetFromOrigArg,
2803 bool ForceMutable) const {
2805 // Currently, two use-cases possible:
2806 // Case #1. Non-var-args function, and we meet first byval parameter.
2807 // Setup first unallocated register as first byval register;
2808 // eat all remained registers
2809 // (these two actions are performed by HandleByVal method).
2810 // Then, here, we initialize stack frame with
2811 // "store-reg" instructions.
2812 // Case #2. Var-args function, that doesn't contain byval parameters.
2813 // The same: eat all remained unallocated registers,
2814 // initialize stack frame.
2816 MachineFunction &MF = DAG.getMachineFunction();
2817 MachineFrameInfo *MFI = MF.getFrameInfo();
2818 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2819 unsigned firstRegToSaveIndex, lastRegToSaveIndex;
2820 unsigned RBegin, REnd;
2821 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
2822 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
2823 firstRegToSaveIndex = RBegin - ARM::R0;
2824 lastRegToSaveIndex = REnd - ARM::R0;
2826 firstRegToSaveIndex = CCInfo.getFirstUnallocated
2827 (GPRArgRegs, array_lengthof(GPRArgRegs));
2828 lastRegToSaveIndex = 4;
2831 unsigned ArgRegsSize, ArgRegsSaveSize;
2832 computeRegArea(CCInfo, MF, InRegsParamRecordIdx, ArgSize,
2833 ArgRegsSize, ArgRegsSaveSize);
2835 // Store any by-val regs to their spots on the stack so that they may be
2836 // loaded by deferencing the result of formal parameter pointer or va_next.
2837 // Note: once stack area for byval/varargs registers
2838 // was initialized, it can't be initialized again.
2839 if (ArgRegsSaveSize) {
2841 unsigned Padding = ArgRegsSaveSize - ArgRegsSize;
2844 assert(AFI->getStoredByValParamsPadding() == 0 &&
2845 "The only parameter may be padded.");
2846 AFI->setStoredByValParamsPadding(Padding);
2849 int FrameIndex = MFI->CreateFixedObject(
2851 Padding + ArgOffset,
2853 SDValue FIN = DAG.getFrameIndex(FrameIndex, getPointerTy());
2855 SmallVector<SDValue, 4> MemOps;
2856 for (unsigned i = 0; firstRegToSaveIndex < lastRegToSaveIndex;
2857 ++firstRegToSaveIndex, ++i) {
2858 const TargetRegisterClass *RC;
2859 if (AFI->isThumb1OnlyFunction())
2860 RC = &ARM::tGPRRegClass;
2862 RC = &ARM::GPRRegClass;
2864 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC);
2865 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2867 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2868 MachinePointerInfo(OrigArg, OffsetFromOrigArg + 4*i),
2870 MemOps.push_back(Store);
2871 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2872 DAG.getConstant(4, getPointerTy()));
2875 AFI->setArgRegsSaveSize(ArgRegsSaveSize + AFI->getArgRegsSaveSize());
2877 if (!MemOps.empty())
2878 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2879 &MemOps[0], MemOps.size());
2882 // This will point to the next argument passed via stack.
2883 return MFI->CreateFixedObject(
2884 4, AFI->getStoredByValParamsPadding() + ArgOffset, !ForceMutable);
2887 // Setup stack frame, the va_list pointer will start from.
2889 ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
2890 SDLoc dl, SDValue &Chain,
2892 bool ForceMutable) const {
2893 MachineFunction &MF = DAG.getMachineFunction();
2894 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2896 // Try to store any remaining integer argument regs
2897 // to their spots on the stack so that they may be loaded by deferencing
2898 // the result of va_next.
2899 // If there is no regs to be stored, just point address after last
2900 // argument passed via stack.
2902 StoreByValRegs(CCInfo, DAG, dl, Chain, 0, CCInfo.getInRegsParamsCount(),
2903 0, ArgOffset, 0, ForceMutable);
2905 AFI->setVarArgsFrameIndex(FrameIndex);
2909 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2910 CallingConv::ID CallConv, bool isVarArg,
2911 const SmallVectorImpl<ISD::InputArg>
2913 SDLoc dl, SelectionDAG &DAG,
2914 SmallVectorImpl<SDValue> &InVals)
2916 MachineFunction &MF = DAG.getMachineFunction();
2917 MachineFrameInfo *MFI = MF.getFrameInfo();
2919 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2921 // Assign locations to all of the incoming arguments.
2922 SmallVector<CCValAssign, 16> ArgLocs;
2923 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2924 getTargetMachine(), ArgLocs, *DAG.getContext(), Prologue);
2925 CCInfo.AnalyzeFormalArguments(Ins,
2926 CCAssignFnForNode(CallConv, /* Return*/ false,
2929 SmallVector<SDValue, 16> ArgValues;
2930 int lastInsIndex = -1;
2932 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
2933 unsigned CurArgIdx = 0;
2935 // Initially ArgRegsSaveSize is zero.
2936 // Then we increase this value each time we meet byval parameter.
2937 // We also increase this value in case of varargs function.
2938 AFI->setArgRegsSaveSize(0);
2940 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2941 CCValAssign &VA = ArgLocs[i];
2942 std::advance(CurOrigArg, Ins[VA.getValNo()].OrigArgIndex - CurArgIdx);
2943 CurArgIdx = Ins[VA.getValNo()].OrigArgIndex;
2944 // Arguments stored in registers.
2945 if (VA.isRegLoc()) {
2946 EVT RegVT = VA.getLocVT();
2948 if (VA.needsCustom()) {
2949 // f64 and vector types are split up into multiple registers or
2950 // combinations of registers and stack slots.
2951 if (VA.getLocVT() == MVT::v2f64) {
2952 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2954 VA = ArgLocs[++i]; // skip ahead to next loc
2956 if (VA.isMemLoc()) {
2957 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2958 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2959 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2960 MachinePointerInfo::getFixedStack(FI),
2961 false, false, false, 0);
2963 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2966 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2967 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2968 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2969 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2970 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2972 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2975 const TargetRegisterClass *RC;
2977 if (RegVT == MVT::f32)
2978 RC = &ARM::SPRRegClass;
2979 else if (RegVT == MVT::f64)
2980 RC = &ARM::DPRRegClass;
2981 else if (RegVT == MVT::v2f64)
2982 RC = &ARM::QPRRegClass;
2983 else if (RegVT == MVT::i32)
2984 RC = AFI->isThumb1OnlyFunction() ?
2985 (const TargetRegisterClass*)&ARM::tGPRRegClass :
2986 (const TargetRegisterClass*)&ARM::GPRRegClass;
2988 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2990 // Transform the arguments in physical registers into virtual ones.
2991 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2992 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2995 // If this is an 8 or 16-bit value, it is really passed promoted
2996 // to 32 bits. Insert an assert[sz]ext to capture this, then
2997 // truncate to the right size.
2998 switch (VA.getLocInfo()) {
2999 default: llvm_unreachable("Unknown loc info!");
3000 case CCValAssign::Full: break;
3001 case CCValAssign::BCvt:
3002 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
3004 case CCValAssign::SExt:
3005 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
3006 DAG.getValueType(VA.getValVT()));
3007 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3009 case CCValAssign::ZExt:
3010 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
3011 DAG.getValueType(VA.getValVT()));
3012 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3016 InVals.push_back(ArgValue);
3018 } else { // VA.isRegLoc()
3021 assert(VA.isMemLoc());
3022 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
3024 int index = ArgLocs[i].getValNo();
3026 // Some Ins[] entries become multiple ArgLoc[] entries.
3027 // Process them only once.
3028 if (index != lastInsIndex)
3030 ISD::ArgFlagsTy Flags = Ins[index].Flags;
3031 // FIXME: For now, all byval parameter objects are marked mutable.
3032 // This can be changed with more analysis.
3033 // In case of tail call optimization mark all arguments mutable.
3034 // Since they could be overwritten by lowering of arguments in case of
3036 if (Flags.isByVal()) {
3037 unsigned CurByValIndex = CCInfo.getInRegsParamsProceed();
3038 int FrameIndex = StoreByValRegs(
3039 CCInfo, DAG, dl, Chain, CurOrigArg,
3041 Ins[VA.getValNo()].PartOffset,
3042 VA.getLocMemOffset(),
3043 Flags.getByValSize(),
3044 true /*force mutable frames*/);
3045 InVals.push_back(DAG.getFrameIndex(FrameIndex, getPointerTy()));
3046 CCInfo.nextInRegsParam();
3048 unsigned FIOffset = VA.getLocMemOffset() +
3049 AFI->getStoredByValParamsPadding();
3050 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
3053 // Create load nodes to retrieve arguments from the stack.
3054 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
3055 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
3056 MachinePointerInfo::getFixedStack(FI),
3057 false, false, false, 0));
3059 lastInsIndex = index;
3066 VarArgStyleRegisters(CCInfo, DAG, dl, Chain,
3067 CCInfo.getNextStackOffset());
3072 /// isFloatingPointZero - Return true if this is +0.0.
3073 static bool isFloatingPointZero(SDValue Op) {
3074 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
3075 return CFP->getValueAPF().isPosZero();
3076 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
3077 // Maybe this has already been legalized into the constant pool?
3078 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
3079 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
3080 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
3081 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
3082 return CFP->getValueAPF().isPosZero();
3088 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
3089 /// the given operands.
3091 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
3092 SDValue &ARMcc, SelectionDAG &DAG,
3094 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
3095 unsigned C = RHSC->getZExtValue();
3096 if (!isLegalICmpImmediate(C)) {
3097 // Constant does not fit, try adjusting it by one?
3102 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
3103 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
3104 RHS = DAG.getConstant(C-1, MVT::i32);
3109 if (C != 0 && isLegalICmpImmediate(C-1)) {
3110 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
3111 RHS = DAG.getConstant(C-1, MVT::i32);
3116 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
3117 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
3118 RHS = DAG.getConstant(C+1, MVT::i32);
3123 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
3124 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
3125 RHS = DAG.getConstant(C+1, MVT::i32);
3132 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3133 ARMISD::NodeType CompareType;
3136 CompareType = ARMISD::CMP;
3141 CompareType = ARMISD::CMPZ;
3144 ARMcc = DAG.getConstant(CondCode, MVT::i32);
3145 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
3148 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
3150 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
3153 if (!isFloatingPointZero(RHS))
3154 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
3156 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
3157 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
3160 /// duplicateCmp - Glue values can have only one use, so this function
3161 /// duplicates a comparison node.
3163 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
3164 unsigned Opc = Cmp.getOpcode();
3166 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
3167 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3169 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
3170 Cmp = Cmp.getOperand(0);
3171 Opc = Cmp.getOpcode();
3172 if (Opc == ARMISD::CMPFP)
3173 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3175 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
3176 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
3178 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
3181 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
3182 SDValue Cond = Op.getOperand(0);
3183 SDValue SelectTrue = Op.getOperand(1);
3184 SDValue SelectFalse = Op.getOperand(2);
3189 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
3190 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
3192 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
3193 const ConstantSDNode *CMOVTrue =
3194 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
3195 const ConstantSDNode *CMOVFalse =
3196 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
3198 if (CMOVTrue && CMOVFalse) {
3199 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
3200 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
3204 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
3206 False = SelectFalse;
3207 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
3212 if (True.getNode() && False.getNode()) {
3213 EVT VT = Op.getValueType();
3214 SDValue ARMcc = Cond.getOperand(2);
3215 SDValue CCR = Cond.getOperand(3);
3216 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
3217 assert(True.getValueType() == VT);
3218 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
3223 // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
3224 // undefined bits before doing a full-word comparison with zero.
3225 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
3226 DAG.getConstant(1, Cond.getValueType()));
3228 return DAG.getSelectCC(dl, Cond,
3229 DAG.getConstant(0, Cond.getValueType()),
3230 SelectTrue, SelectFalse, ISD::SETNE);
3233 static ISD::CondCode getInverseCCForVSEL(ISD::CondCode CC) {
3234 if (CC == ISD::SETNE)
3236 return ISD::getSetCCInverse(CC, true);
3239 static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
3240 bool &swpCmpOps, bool &swpVselOps) {
3241 // Start by selecting the GE condition code for opcodes that return true for
3243 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
3245 CondCode = ARMCC::GE;
3247 // and GT for opcodes that return false for 'equality'.
3248 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
3250 CondCode = ARMCC::GT;
3252 // Since we are constrained to GE/GT, if the opcode contains 'less', we need
3253 // to swap the compare operands.
3254 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
3258 // Both GT and GE are ordered comparisons, and return false for 'unordered'.
3259 // If we have an unordered opcode, we need to swap the operands to the VSEL
3260 // instruction (effectively negating the condition).
3262 // This also has the effect of swapping which one of 'less' or 'greater'
3263 // returns true, so we also swap the compare operands. It also switches
3264 // whether we return true for 'equality', so we compensate by picking the
3265 // opposite condition code to our original choice.
3266 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
3267 CC == ISD::SETUGT) {
3268 swpCmpOps = !swpCmpOps;
3269 swpVselOps = !swpVselOps;
3270 CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
3273 // 'ordered' is 'anything but unordered', so use the VS condition code and
3274 // swap the VSEL operands.
3275 if (CC == ISD::SETO) {
3276 CondCode = ARMCC::VS;
3280 // 'unordered or not equal' is 'anything but equal', so use the EQ condition
3281 // code and swap the VSEL operands.
3282 if (CC == ISD::SETUNE) {
3283 CondCode = ARMCC::EQ;
3288 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
3289 EVT VT = Op.getValueType();
3290 SDValue LHS = Op.getOperand(0);
3291 SDValue RHS = Op.getOperand(1);
3292 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3293 SDValue TrueVal = Op.getOperand(2);
3294 SDValue FalseVal = Op.getOperand(3);
3297 if (LHS.getValueType() == MVT::i32) {
3298 // Try to generate VSEL on ARMv8.
3299 // The VSEL instruction can't use all the usual ARM condition
3300 // codes: it only has two bits to select the condition code, so it's
3301 // constrained to use only GE, GT, VS and EQ.
3303 // To implement all the various ISD::SETXXX opcodes, we sometimes need to
3304 // swap the operands of the previous compare instruction (effectively
3305 // inverting the compare condition, swapping 'less' and 'greater') and
3306 // sometimes need to swap the operands to the VSEL (which inverts the
3307 // condition in the sense of firing whenever the previous condition didn't)
3308 if (getSubtarget()->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
3309 TrueVal.getValueType() == MVT::f64)) {
3310 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3311 if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
3312 CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
3313 CC = getInverseCCForVSEL(CC);
3314 std::swap(TrueVal, FalseVal);
3319 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3320 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3321 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
3325 ARMCC::CondCodes CondCode, CondCode2;
3326 FPCCToARMCC(CC, CondCode, CondCode2);
3328 // Try to generate VSEL on ARMv8.
3329 if (getSubtarget()->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
3330 TrueVal.getValueType() == MVT::f64)) {
3331 // We can select VMAXNM/VMINNM from a compare followed by a select with the
3332 // same operands, as follows:
3333 // c = fcmp [ogt, olt, ugt, ult] a, b
3335 // We only do this in unsafe-fp-math, because signed zeros and NaNs are
3336 // handled differently than the original code sequence.
3337 if (getTargetMachine().Options.UnsafeFPMath && LHS == TrueVal &&
3339 if (CC == ISD::SETOGT || CC == ISD::SETUGT)
3340 return DAG.getNode(ARMISD::VMAXNM, dl, VT, TrueVal, FalseVal);
3341 if (CC == ISD::SETOLT || CC == ISD::SETULT)
3342 return DAG.getNode(ARMISD::VMINNM, dl, VT, TrueVal, FalseVal);
3345 bool swpCmpOps = false;
3346 bool swpVselOps = false;
3347 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
3349 if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
3350 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
3352 std::swap(LHS, RHS);
3354 std::swap(TrueVal, FalseVal);
3358 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
3359 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
3360 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3361 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
3363 if (CondCode2 != ARMCC::AL) {
3364 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
3365 // FIXME: Needs another CMP because flag can have but one use.
3366 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
3367 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
3368 Result, TrueVal, ARMcc2, CCR, Cmp2);
3373 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
3374 /// to morph to an integer compare sequence.
3375 static bool canChangeToInt(SDValue Op, bool &SeenZero,
3376 const ARMSubtarget *Subtarget) {
3377 SDNode *N = Op.getNode();
3378 if (!N->hasOneUse())
3379 // Otherwise it requires moving the value from fp to integer registers.
3381 if (!N->getNumValues())
3383 EVT VT = Op.getValueType();
3384 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
3385 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
3386 // vmrs are very slow, e.g. cortex-a8.
3389 if (isFloatingPointZero(Op)) {
3393 return ISD::isNormalLoad(N);
3396 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
3397 if (isFloatingPointZero(Op))
3398 return DAG.getConstant(0, MVT::i32);
3400 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
3401 return DAG.getLoad(MVT::i32, SDLoc(Op),
3402 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
3403 Ld->isVolatile(), Ld->isNonTemporal(),
3404 Ld->isInvariant(), Ld->getAlignment());
3406 llvm_unreachable("Unknown VFP cmp argument!");
3409 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
3410 SDValue &RetVal1, SDValue &RetVal2) {
3411 if (isFloatingPointZero(Op)) {
3412 RetVal1 = DAG.getConstant(0, MVT::i32);
3413 RetVal2 = DAG.getConstant(0, MVT::i32);
3417 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
3418 SDValue Ptr = Ld->getBasePtr();
3419 RetVal1 = DAG.getLoad(MVT::i32, SDLoc(Op),
3420 Ld->getChain(), Ptr,
3421 Ld->getPointerInfo(),
3422 Ld->isVolatile(), Ld->isNonTemporal(),
3423 Ld->isInvariant(), Ld->getAlignment());
3425 EVT PtrType = Ptr.getValueType();
3426 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
3427 SDValue NewPtr = DAG.getNode(ISD::ADD, SDLoc(Op),
3428 PtrType, Ptr, DAG.getConstant(4, PtrType));
3429 RetVal2 = DAG.getLoad(MVT::i32, SDLoc(Op),
3430 Ld->getChain(), NewPtr,
3431 Ld->getPointerInfo().getWithOffset(4),
3432 Ld->isVolatile(), Ld->isNonTemporal(),
3433 Ld->isInvariant(), NewAlign);
3437 llvm_unreachable("Unknown VFP cmp argument!");
3440 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
3441 /// f32 and even f64 comparisons to integer ones.
3443 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
3444 SDValue Chain = Op.getOperand(0);
3445 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3446 SDValue LHS = Op.getOperand(2);
3447 SDValue RHS = Op.getOperand(3);
3448 SDValue Dest = Op.getOperand(4);
3451 bool LHSSeenZero = false;
3452 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
3453 bool RHSSeenZero = false;
3454 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
3455 if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
3456 // If unsafe fp math optimization is enabled and there are no other uses of
3457 // the CMP operands, and the condition code is EQ or NE, we can optimize it
3458 // to an integer comparison.
3459 if (CC == ISD::SETOEQ)
3461 else if (CC == ISD::SETUNE)
3464 SDValue Mask = DAG.getConstant(0x7fffffff, MVT::i32);
3466 if (LHS.getValueType() == MVT::f32) {
3467 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3468 bitcastf32Toi32(LHS, DAG), Mask);
3469 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3470 bitcastf32Toi32(RHS, DAG), Mask);
3471 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3472 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3473 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3474 Chain, Dest, ARMcc, CCR, Cmp);
3479 expandf64Toi32(LHS, DAG, LHS1, LHS2);
3480 expandf64Toi32(RHS, DAG, RHS1, RHS2);
3481 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
3482 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
3483 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3484 ARMcc = DAG.getConstant(CondCode, MVT::i32);
3485 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
3486 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
3487 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
3493 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3494 SDValue Chain = Op.getOperand(0);
3495 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3496 SDValue LHS = Op.getOperand(2);
3497 SDValue RHS = Op.getOperand(3);
3498 SDValue Dest = Op.getOperand(4);
3501 if (LHS.getValueType() == MVT::i32) {
3503 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3504 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3505 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3506 Chain, Dest, ARMcc, CCR, Cmp);
3509 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3511 if (getTargetMachine().Options.UnsafeFPMath &&
3512 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
3513 CC == ISD::SETNE || CC == ISD::SETUNE)) {
3514 SDValue Result = OptimizeVFPBrcond(Op, DAG);
3515 if (Result.getNode())
3519 ARMCC::CondCodes CondCode, CondCode2;
3520 FPCCToARMCC(CC, CondCode, CondCode2);
3522 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
3523 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
3524 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3525 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
3526 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
3527 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
3528 if (CondCode2 != ARMCC::AL) {
3529 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
3530 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
3531 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
3536 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
3537 SDValue Chain = Op.getOperand(0);
3538 SDValue Table = Op.getOperand(1);
3539 SDValue Index = Op.getOperand(2);
3542 EVT PTy = getPointerTy();
3543 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
3544 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
3545 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
3546 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
3547 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
3548 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
3549 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3550 if (Subtarget->isThumb2()) {
3551 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
3552 // which does another jump to the destination. This also makes it easier
3553 // to translate it to TBB / TBH later.
3554 // FIXME: This might not work if the function is extremely large.
3555 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
3556 Addr, Op.getOperand(2), JTI, UId);
3558 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
3559 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
3560 MachinePointerInfo::getJumpTable(),
3561 false, false, false, 0);
3562 Chain = Addr.getValue(1);
3563 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
3564 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
3566 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
3567 MachinePointerInfo::getJumpTable(),
3568 false, false, false, 0);
3569 Chain = Addr.getValue(1);
3570 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
3574 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
3575 EVT VT = Op.getValueType();
3578 if (Op.getValueType().getVectorElementType() == MVT::i32) {
3579 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
3581 return DAG.UnrollVectorOp(Op.getNode());
3584 assert(Op.getOperand(0).getValueType() == MVT::v4f32 &&
3585 "Invalid type for custom lowering!");
3586 if (VT != MVT::v4i16)
3587 return DAG.UnrollVectorOp(Op.getNode());
3589 Op = DAG.getNode(Op.getOpcode(), dl, MVT::v4i32, Op.getOperand(0));
3590 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
3593 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
3594 EVT VT = Op.getValueType();
3596 return LowerVectorFP_TO_INT(Op, DAG);
3601 switch (Op.getOpcode()) {
3602 default: llvm_unreachable("Invalid opcode!");
3603 case ISD::FP_TO_SINT:
3604 Opc = ARMISD::FTOSI;
3606 case ISD::FP_TO_UINT:
3607 Opc = ARMISD::FTOUI;
3610 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
3611 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3614 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3615 EVT VT = Op.getValueType();
3618 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
3619 if (VT.getVectorElementType() == MVT::f32)
3621 return DAG.UnrollVectorOp(Op.getNode());
3624 assert(Op.getOperand(0).getValueType() == MVT::v4i16 &&
3625 "Invalid type for custom lowering!");
3626 if (VT != MVT::v4f32)
3627 return DAG.UnrollVectorOp(Op.getNode());
3631 switch (Op.getOpcode()) {
3632 default: llvm_unreachable("Invalid opcode!");
3633 case ISD::SINT_TO_FP:
3634 CastOpc = ISD::SIGN_EXTEND;
3635 Opc = ISD::SINT_TO_FP;
3637 case ISD::UINT_TO_FP:
3638 CastOpc = ISD::ZERO_EXTEND;
3639 Opc = ISD::UINT_TO_FP;
3643 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
3644 return DAG.getNode(Opc, dl, VT, Op);
3647 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3648 EVT VT = Op.getValueType();
3650 return LowerVectorINT_TO_FP(Op, DAG);
3655 switch (Op.getOpcode()) {
3656 default: llvm_unreachable("Invalid opcode!");
3657 case ISD::SINT_TO_FP:
3658 Opc = ARMISD::SITOF;
3660 case ISD::UINT_TO_FP:
3661 Opc = ARMISD::UITOF;
3665 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
3666 return DAG.getNode(Opc, dl, VT, Op);
3669 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
3670 // Implement fcopysign with a fabs and a conditional fneg.
3671 SDValue Tmp0 = Op.getOperand(0);
3672 SDValue Tmp1 = Op.getOperand(1);
3674 EVT VT = Op.getValueType();
3675 EVT SrcVT = Tmp1.getValueType();
3676 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
3677 Tmp0.getOpcode() == ARMISD::VMOVDRR;
3678 bool UseNEON = !InGPR && Subtarget->hasNEON();
3681 // Use VBSL to copy the sign bit.
3682 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
3683 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
3684 DAG.getTargetConstant(EncodedVal, MVT::i32));
3685 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
3687 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3688 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
3689 DAG.getConstant(32, MVT::i32));
3690 else /*if (VT == MVT::f32)*/
3691 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
3692 if (SrcVT == MVT::f32) {
3693 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
3695 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3696 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
3697 DAG.getConstant(32, MVT::i32));
3698 } else if (VT == MVT::f32)
3699 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
3700 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
3701 DAG.getConstant(32, MVT::i32));
3702 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
3703 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
3705 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
3707 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
3708 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
3709 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
3711 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
3712 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
3713 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
3714 if (VT == MVT::f32) {
3715 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
3716 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
3717 DAG.getConstant(0, MVT::i32));
3719 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
3725 // Bitcast operand 1 to i32.
3726 if (SrcVT == MVT::f64)
3727 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3728 &Tmp1, 1).getValue(1);
3729 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
3731 // Or in the signbit with integer operations.
3732 SDValue Mask1 = DAG.getConstant(0x80000000, MVT::i32);
3733 SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32);
3734 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
3735 if (VT == MVT::f32) {
3736 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
3737 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
3738 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3739 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
3742 // f64: Or the high part with signbit and then combine two parts.
3743 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3745 SDValue Lo = Tmp0.getValue(0);
3746 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
3747 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
3748 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
3751 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
3752 MachineFunction &MF = DAG.getMachineFunction();
3753 MachineFrameInfo *MFI = MF.getFrameInfo();
3754 MFI->setReturnAddressIsTaken(true);
3756 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
3759 EVT VT = Op.getValueType();
3761 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3763 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
3764 SDValue Offset = DAG.getConstant(4, MVT::i32);
3765 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
3766 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
3767 MachinePointerInfo(), false, false, false, 0);
3770 // Return LR, which contains the return address. Mark it an implicit live-in.
3771 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
3772 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
3775 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
3776 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3777 MFI->setFrameAddressIsTaken(true);
3779 EVT VT = Op.getValueType();
3780 SDLoc dl(Op); // FIXME probably not meaningful
3781 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3782 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
3783 ? ARM::R7 : ARM::R11;
3784 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
3786 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
3787 MachinePointerInfo(),
3788 false, false, false, 0);
3792 /// ExpandBITCAST - If the target supports VFP, this function is called to
3793 /// expand a bit convert where either the source or destination type is i64 to
3794 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
3795 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
3796 /// vectors), since the legalizer won't know what to do with that.
3797 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
3798 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3800 SDValue Op = N->getOperand(0);
3802 // This function is only supposed to be called for i64 types, either as the
3803 // source or destination of the bit convert.
3804 EVT SrcVT = Op.getValueType();
3805 EVT DstVT = N->getValueType(0);
3806 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
3807 "ExpandBITCAST called for non-i64 type");
3809 // Turn i64->f64 into VMOVDRR.
3810 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
3811 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3812 DAG.getConstant(0, MVT::i32));
3813 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3814 DAG.getConstant(1, MVT::i32));
3815 return DAG.getNode(ISD::BITCAST, dl, DstVT,
3816 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
3819 // Turn f64->i64 into VMOVRRD.
3820 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
3821 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
3822 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
3823 // Merge the pieces into a single i64 value.
3824 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
3830 /// getZeroVector - Returns a vector of specified type with all zero elements.
3831 /// Zero vectors are used to represent vector negation and in those cases
3832 /// will be implemented with the NEON VNEG instruction. However, VNEG does
3833 /// not support i64 elements, so sometimes the zero vectors will need to be
3834 /// explicitly constructed. Regardless, use a canonical VMOV to create the
3836 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, SDLoc dl) {
3837 assert(VT.isVector() && "Expected a vector type");
3838 // The canonical modified immediate encoding of a zero vector is....0!
3839 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
3840 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
3841 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
3842 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3845 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
3846 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3847 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
3848 SelectionDAG &DAG) const {
3849 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3850 EVT VT = Op.getValueType();
3851 unsigned VTBits = VT.getSizeInBits();
3853 SDValue ShOpLo = Op.getOperand(0);
3854 SDValue ShOpHi = Op.getOperand(1);
3855 SDValue ShAmt = Op.getOperand(2);
3857 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
3859 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
3861 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3862 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3863 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
3864 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3865 DAG.getConstant(VTBits, MVT::i32));
3866 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
3867 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3868 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
3870 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3871 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3873 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
3874 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
3877 SDValue Ops[2] = { Lo, Hi };
3878 return DAG.getMergeValues(Ops, 2, dl);
3881 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
3882 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3883 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
3884 SelectionDAG &DAG) const {
3885 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3886 EVT VT = Op.getValueType();
3887 unsigned VTBits = VT.getSizeInBits();
3889 SDValue ShOpLo = Op.getOperand(0);
3890 SDValue ShOpHi = Op.getOperand(1);
3891 SDValue ShAmt = Op.getOperand(2);
3894 assert(Op.getOpcode() == ISD::SHL_PARTS);
3895 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3896 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3897 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
3898 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3899 DAG.getConstant(VTBits, MVT::i32));
3900 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
3901 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
3903 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3904 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3905 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3907 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
3908 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
3911 SDValue Ops[2] = { Lo, Hi };
3912 return DAG.getMergeValues(Ops, 2, dl);
3915 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
3916 SelectionDAG &DAG) const {
3917 // The rounding mode is in bits 23:22 of the FPSCR.
3918 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
3919 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
3920 // so that the shift + and get folded into a bitfield extract.
3922 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
3923 DAG.getConstant(Intrinsic::arm_get_fpscr,
3925 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
3926 DAG.getConstant(1U << 22, MVT::i32));
3927 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
3928 DAG.getConstant(22, MVT::i32));
3929 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
3930 DAG.getConstant(3, MVT::i32));
3933 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
3934 const ARMSubtarget *ST) {
3935 EVT VT = N->getValueType(0);
3938 if (!ST->hasV6T2Ops())
3941 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
3942 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
3945 /// getCTPOP16BitCounts - Returns a v8i8/v16i8 vector containing the bit-count
3946 /// for each 16-bit element from operand, repeated. The basic idea is to
3947 /// leverage vcnt to get the 8-bit counts, gather and add the results.
3949 /// Trace for v4i16:
3950 /// input = [v0 v1 v2 v3 ] (vi 16-bit element)
3951 /// cast: N0 = [w0 w1 w2 w3 w4 w5 w6 w7] (v0 = [w0 w1], wi 8-bit element)
3952 /// vcnt: N1 = [b0 b1 b2 b3 b4 b5 b6 b7] (bi = bit-count of 8-bit element wi)
3953 /// vrev: N2 = [b1 b0 b3 b2 b5 b4 b7 b6]
3954 /// [b0 b1 b2 b3 b4 b5 b6 b7]
3955 /// +[b1 b0 b3 b2 b5 b4 b7 b6]
3956 /// N3=N1+N2 = [k0 k0 k1 k1 k2 k2 k3 k3] (k0 = b0+b1 = bit-count of 16-bit v0,
3957 /// vuzp: = [k0 k1 k2 k3 k0 k1 k2 k3] each ki is 8-bits)
3958 static SDValue getCTPOP16BitCounts(SDNode *N, SelectionDAG &DAG) {
3959 EVT VT = N->getValueType(0);
3962 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
3963 SDValue N0 = DAG.getNode(ISD::BITCAST, DL, VT8Bit, N->getOperand(0));
3964 SDValue N1 = DAG.getNode(ISD::CTPOP, DL, VT8Bit, N0);
3965 SDValue N2 = DAG.getNode(ARMISD::VREV16, DL, VT8Bit, N1);
3966 SDValue N3 = DAG.getNode(ISD::ADD, DL, VT8Bit, N1, N2);
3967 return DAG.getNode(ARMISD::VUZP, DL, VT8Bit, N3, N3);
3970 /// lowerCTPOP16BitElements - Returns a v4i16/v8i16 vector containing the
3971 /// bit-count for each 16-bit element from the operand. We need slightly
3972 /// different sequencing for v4i16 and v8i16 to stay within NEON's available
3973 /// 64/128-bit registers.
3975 /// Trace for v4i16:
3976 /// input = [v0 v1 v2 v3 ] (vi 16-bit element)
3977 /// v8i8: BitCounts = [k0 k1 k2 k3 k0 k1 k2 k3 ] (ki is the bit-count of vi)
3978 /// v8i16:Extended = [k0 k1 k2 k3 k0 k1 k2 k3 ]
3979 /// v4i16:Extracted = [k0 k1 k2 k3 ]
3980 static SDValue lowerCTPOP16BitElements(SDNode *N, SelectionDAG &DAG) {
3981 EVT VT = N->getValueType(0);
3984 SDValue BitCounts = getCTPOP16BitCounts(N, DAG);
3985 if (VT.is64BitVector()) {
3986 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, BitCounts);
3987 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, Extended,
3988 DAG.getIntPtrConstant(0));
3990 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v8i8,
3991 BitCounts, DAG.getIntPtrConstant(0));
3992 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, Extracted);
3996 /// lowerCTPOP32BitElements - Returns a v2i32/v4i32 vector containing the
3997 /// bit-count for each 32-bit element from the operand. The idea here is
3998 /// to split the vector into 16-bit elements, leverage the 16-bit count
3999 /// routine, and then combine the results.
4001 /// Trace for v2i32 (v4i32 similar with Extracted/Extended exchanged):
4002 /// input = [v0 v1 ] (vi: 32-bit elements)
4003 /// Bitcast = [w0 w1 w2 w3 ] (wi: 16-bit elements, v0 = [w0 w1])
4004 /// Counts16 = [k0 k1 k2 k3 ] (ki: 16-bit elements, bit-count of wi)
4005 /// vrev: N0 = [k1 k0 k3 k2 ]
4007 /// N1 =+[k1 k0 k3 k2 ]
4009 /// N2 =+[k1 k3 k0 k2 ]
4011 /// Extended =+[k1 k3 k0 k2 ]
4013 /// Extracted=+[k1 k3 ]
4015 static SDValue lowerCTPOP32BitElements(SDNode *N, SelectionDAG &DAG) {
4016 EVT VT = N->getValueType(0);
4019 EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16;
4021 SDValue Bitcast = DAG.getNode(ISD::BITCAST, DL, VT16Bit, N->getOperand(0));
4022 SDValue Counts16 = lowerCTPOP16BitElements(Bitcast.getNode(), DAG);
4023 SDValue N0 = DAG.getNode(ARMISD::VREV32, DL, VT16Bit, Counts16);
4024 SDValue N1 = DAG.getNode(ISD::ADD, DL, VT16Bit, Counts16, N0);
4025 SDValue N2 = DAG.getNode(ARMISD::VUZP, DL, VT16Bit, N1, N1);
4027 if (VT.is64BitVector()) {
4028 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, N2);
4029 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i32, Extended,
4030 DAG.getIntPtrConstant(0));
4032 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, N2,
4033 DAG.getIntPtrConstant(0));
4034 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, Extracted);
4038 static SDValue LowerCTPOP(SDNode *N, SelectionDAG &DAG,
4039 const ARMSubtarget *ST) {
4040 EVT VT = N->getValueType(0);
4042 assert(ST->hasNEON() && "Custom ctpop lowering requires NEON.");
4043 assert((VT == MVT::v2i32 || VT == MVT::v4i32 ||
4044 VT == MVT::v4i16 || VT == MVT::v8i16) &&
4045 "Unexpected type for custom ctpop lowering");
4047 if (VT.getVectorElementType() == MVT::i32)
4048 return lowerCTPOP32BitElements(N, DAG);
4050 return lowerCTPOP16BitElements(N, DAG);
4053 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
4054 const ARMSubtarget *ST) {
4055 EVT VT = N->getValueType(0);
4061 // Lower vector shifts on NEON to use VSHL.
4062 assert(ST->hasNEON() && "unexpected vector shift");
4064 // Left shifts translate directly to the vshiftu intrinsic.
4065 if (N->getOpcode() == ISD::SHL)
4066 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
4067 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
4068 N->getOperand(0), N->getOperand(1));
4070 assert((N->getOpcode() == ISD::SRA ||
4071 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
4073 // NEON uses the same intrinsics for both left and right shifts. For
4074 // right shifts, the shift amounts are negative, so negate the vector of
4076 EVT ShiftVT = N->getOperand(1).getValueType();
4077 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
4078 getZeroVector(ShiftVT, DAG, dl),
4080 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
4081 Intrinsic::arm_neon_vshifts :
4082 Intrinsic::arm_neon_vshiftu);
4083 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
4084 DAG.getConstant(vshiftInt, MVT::i32),
4085 N->getOperand(0), NegatedCount);
4088 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
4089 const ARMSubtarget *ST) {
4090 EVT VT = N->getValueType(0);
4093 // We can get here for a node like i32 = ISD::SHL i32, i64
4097 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
4098 "Unknown shift to lower!");
4100 // We only lower SRA, SRL of 1 here, all others use generic lowering.
4101 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
4102 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
4105 // If we are in thumb mode, we don't have RRX.
4106 if (ST->isThumb1Only()) return SDValue();
4108 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
4109 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
4110 DAG.getConstant(0, MVT::i32));
4111 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
4112 DAG.getConstant(1, MVT::i32));
4114 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
4115 // captures the result into a carry flag.
4116 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
4117 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), &Hi, 1);
4119 // The low part is an ARMISD::RRX operand, which shifts the carry in.
4120 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
4122 // Merge the pieces into a single i64 value.
4123 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4126 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
4127 SDValue TmpOp0, TmpOp1;
4128 bool Invert = false;
4132 SDValue Op0 = Op.getOperand(0);
4133 SDValue Op1 = Op.getOperand(1);
4134 SDValue CC = Op.getOperand(2);
4135 EVT VT = Op.getValueType();
4136 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
4139 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
4140 switch (SetCCOpcode) {
4141 default: llvm_unreachable("Illegal FP comparison");
4143 case ISD::SETNE: Invert = true; // Fallthrough
4145 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
4147 case ISD::SETLT: Swap = true; // Fallthrough
4149 case ISD::SETGT: Opc = ARMISD::VCGT; break;
4151 case ISD::SETLE: Swap = true; // Fallthrough
4153 case ISD::SETGE: Opc = ARMISD::VCGE; break;
4154 case ISD::SETUGE: Swap = true; // Fallthrough
4155 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
4156 case ISD::SETUGT: Swap = true; // Fallthrough
4157 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
4158 case ISD::SETUEQ: Invert = true; // Fallthrough
4160 // Expand this to (OLT | OGT).
4164 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
4165 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
4167 case ISD::SETUO: Invert = true; // Fallthrough
4169 // Expand this to (OLT | OGE).
4173 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
4174 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
4178 // Integer comparisons.
4179 switch (SetCCOpcode) {
4180 default: llvm_unreachable("Illegal integer comparison");
4181 case ISD::SETNE: Invert = true;
4182 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
4183 case ISD::SETLT: Swap = true;
4184 case ISD::SETGT: Opc = ARMISD::VCGT; break;
4185 case ISD::SETLE: Swap = true;
4186 case ISD::SETGE: Opc = ARMISD::VCGE; break;
4187 case ISD::SETULT: Swap = true;
4188 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
4189 case ISD::SETULE: Swap = true;
4190 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
4193 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
4194 if (Opc == ARMISD::VCEQ) {
4197 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
4199 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
4202 // Ignore bitconvert.
4203 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
4204 AndOp = AndOp.getOperand(0);
4206 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
4208 Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0));
4209 Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1));
4216 std::swap(Op0, Op1);
4218 // If one of the operands is a constant vector zero, attempt to fold the
4219 // comparison to a specialized compare-against-zero form.
4221 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
4223 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
4224 if (Opc == ARMISD::VCGE)
4225 Opc = ARMISD::VCLEZ;
4226 else if (Opc == ARMISD::VCGT)
4227 Opc = ARMISD::VCLTZ;
4232 if (SingleOp.getNode()) {
4235 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break;
4237 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break;
4239 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break;
4241 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break;
4243 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break;
4245 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
4248 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
4252 Result = DAG.getNOT(dl, Result, VT);
4257 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
4258 /// valid vector constant for a NEON instruction with a "modified immediate"
4259 /// operand (e.g., VMOV). If so, return the encoded value.
4260 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
4261 unsigned SplatBitSize, SelectionDAG &DAG,
4262 EVT &VT, bool is128Bits, NEONModImmType type) {
4263 unsigned OpCmode, Imm;
4265 // SplatBitSize is set to the smallest size that splats the vector, so a
4266 // zero vector will always have SplatBitSize == 8. However, NEON modified
4267 // immediate instructions others than VMOV do not support the 8-bit encoding
4268 // of a zero vector, and the default encoding of zero is supposed to be the
4273 switch (SplatBitSize) {
4275 if (type != VMOVModImm)
4277 // Any 1-byte value is OK. Op=0, Cmode=1110.
4278 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
4281 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
4285 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
4286 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
4287 if ((SplatBits & ~0xff) == 0) {
4288 // Value = 0x00nn: Op=x, Cmode=100x.
4293 if ((SplatBits & ~0xff00) == 0) {
4294 // Value = 0xnn00: Op=x, Cmode=101x.
4296 Imm = SplatBits >> 8;
4302 // NEON's 32-bit VMOV supports splat values where:
4303 // * only one byte is nonzero, or
4304 // * the least significant byte is 0xff and the second byte is nonzero, or
4305 // * the least significant 2 bytes are 0xff and the third is nonzero.
4306 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
4307 if ((SplatBits & ~0xff) == 0) {
4308 // Value = 0x000000nn: Op=x, Cmode=000x.
4313 if ((SplatBits & ~0xff00) == 0) {
4314 // Value = 0x0000nn00: Op=x, Cmode=001x.
4316 Imm = SplatBits >> 8;
4319 if ((SplatBits & ~0xff0000) == 0) {
4320 // Value = 0x00nn0000: Op=x, Cmode=010x.
4322 Imm = SplatBits >> 16;
4325 if ((SplatBits & ~0xff000000) == 0) {
4326 // Value = 0xnn000000: Op=x, Cmode=011x.
4328 Imm = SplatBits >> 24;
4332 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
4333 if (type == OtherModImm) return SDValue();
4335 if ((SplatBits & ~0xffff) == 0 &&
4336 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
4337 // Value = 0x0000nnff: Op=x, Cmode=1100.
4339 Imm = SplatBits >> 8;
4344 if ((SplatBits & ~0xffffff) == 0 &&
4345 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
4346 // Value = 0x00nnffff: Op=x, Cmode=1101.
4348 Imm = SplatBits >> 16;
4349 SplatBits |= 0xffff;
4353 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
4354 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
4355 // VMOV.I32. A (very) minor optimization would be to replicate the value
4356 // and fall through here to test for a valid 64-bit splat. But, then the
4357 // caller would also need to check and handle the change in size.
4361 if (type != VMOVModImm)
4363 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
4364 uint64_t BitMask = 0xff;
4366 unsigned ImmMask = 1;
4368 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
4369 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
4372 } else if ((SplatBits & BitMask) != 0) {
4378 // Op=1, Cmode=1110.
4381 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
4386 llvm_unreachable("unexpected size for isNEONModifiedImm");
4389 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
4390 return DAG.getTargetConstant(EncodedVal, MVT::i32);
4393 SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG,
4394 const ARMSubtarget *ST) const {
4398 bool IsDouble = Op.getValueType() == MVT::f64;
4399 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Op);
4401 // Try splatting with a VMOV.f32...
4402 APFloat FPVal = CFP->getValueAPF();
4403 int ImmVal = IsDouble ? ARM_AM::getFP64Imm(FPVal) : ARM_AM::getFP32Imm(FPVal);
4406 if (IsDouble || !ST->useNEONForSinglePrecisionFP()) {
4407 // We have code in place to select a valid ConstantFP already, no need to
4412 // It's a float and we are trying to use NEON operations where
4413 // possible. Lower it to a splat followed by an extract.
4415 SDValue NewVal = DAG.getTargetConstant(ImmVal, MVT::i32);
4416 SDValue VecConstant = DAG.getNode(ARMISD::VMOVFPIMM, DL, MVT::v2f32,
4418 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecConstant,
4419 DAG.getConstant(0, MVT::i32));
4422 // The rest of our options are NEON only, make sure that's allowed before
4424 if (!ST->hasNEON() || (!IsDouble && !ST->useNEONForSinglePrecisionFP()))
4428 uint64_t iVal = FPVal.bitcastToAPInt().getZExtValue();
4430 // It wouldn't really be worth bothering for doubles except for one very
4431 // important value, which does happen to match: 0.0. So make sure we don't do
4433 if (IsDouble && (iVal & 0xffffffff) != (iVal >> 32))
4436 // Try a VMOV.i32 (FIXME: i8, i16, or i64 could work too).
4437 SDValue NewVal = isNEONModifiedImm(iVal & 0xffffffffU, 0, 32, DAG, VMovVT,
4439 if (NewVal != SDValue()) {
4441 SDValue VecConstant = DAG.getNode(ARMISD::VMOVIMM, DL, VMovVT,
4444 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
4446 // It's a float: cast and extract a vector element.
4447 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
4449 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
4450 DAG.getConstant(0, MVT::i32));
4453 // Finally, try a VMVN.i32
4454 NewVal = isNEONModifiedImm(~iVal & 0xffffffffU, 0, 32, DAG, VMovVT,
4456 if (NewVal != SDValue()) {
4458 SDValue VecConstant = DAG.getNode(ARMISD::VMVNIMM, DL, VMovVT, NewVal);
4461 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
4463 // It's a float: cast and extract a vector element.
4464 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
4466 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
4467 DAG.getConstant(0, MVT::i32));
4473 // check if an VEXT instruction can handle the shuffle mask when the
4474 // vector sources of the shuffle are the same.
4475 static bool isSingletonVEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4476 unsigned NumElts = VT.getVectorNumElements();
4478 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4484 // If this is a VEXT shuffle, the immediate value is the index of the first
4485 // element. The other shuffle indices must be the successive elements after
4487 unsigned ExpectedElt = Imm;
4488 for (unsigned i = 1; i < NumElts; ++i) {
4489 // Increment the expected index. If it wraps around, just follow it
4490 // back to index zero and keep going.
4492 if (ExpectedElt == NumElts)
4495 if (M[i] < 0) continue; // ignore UNDEF indices
4496 if (ExpectedElt != static_cast<unsigned>(M[i]))
4504 static bool isVEXTMask(ArrayRef<int> M, EVT VT,
4505 bool &ReverseVEXT, unsigned &Imm) {
4506 unsigned NumElts = VT.getVectorNumElements();
4507 ReverseVEXT = false;
4509 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4515 // If this is a VEXT shuffle, the immediate value is the index of the first
4516 // element. The other shuffle indices must be the successive elements after
4518 unsigned ExpectedElt = Imm;
4519 for (unsigned i = 1; i < NumElts; ++i) {
4520 // Increment the expected index. If it wraps around, it may still be
4521 // a VEXT but the source vectors must be swapped.
4523 if (ExpectedElt == NumElts * 2) {
4528 if (M[i] < 0) continue; // ignore UNDEF indices
4529 if (ExpectedElt != static_cast<unsigned>(M[i]))
4533 // Adjust the index value if the source operands will be swapped.
4540 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
4541 /// instruction with the specified blocksize. (The order of the elements
4542 /// within each block of the vector is reversed.)
4543 static bool isVREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4544 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
4545 "Only possible block sizes for VREV are: 16, 32, 64");
4547 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4551 unsigned NumElts = VT.getVectorNumElements();
4552 unsigned BlockElts = M[0] + 1;
4553 // If the first shuffle index is UNDEF, be optimistic.
4555 BlockElts = BlockSize / EltSz;
4557 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4560 for (unsigned i = 0; i < NumElts; ++i) {
4561 if (M[i] < 0) continue; // ignore UNDEF indices
4562 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
4569 static bool isVTBLMask(ArrayRef<int> M, EVT VT) {
4570 // We can handle <8 x i8> vector shuffles. If the index in the mask is out of
4571 // range, then 0 is placed into the resulting vector. So pretty much any mask
4572 // of 8 elements can work here.
4573 return VT == MVT::v8i8 && M.size() == 8;
4576 static bool isVTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4577 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4581 unsigned NumElts = VT.getVectorNumElements();
4582 WhichResult = (M[0] == 0 ? 0 : 1);
4583 for (unsigned i = 0; i < NumElts; i += 2) {
4584 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
4585 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
4591 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
4592 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4593 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
4594 static bool isVTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
4595 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4599 unsigned NumElts = VT.getVectorNumElements();
4600 WhichResult = (M[0] == 0 ? 0 : 1);
4601 for (unsigned i = 0; i < NumElts; i += 2) {
4602 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
4603 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
4609 static bool isVUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4610 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4614 unsigned NumElts = VT.getVectorNumElements();
4615 WhichResult = (M[0] == 0 ? 0 : 1);
4616 for (unsigned i = 0; i != NumElts; ++i) {
4617 if (M[i] < 0) continue; // ignore UNDEF indices
4618 if ((unsigned) M[i] != 2 * i + WhichResult)
4622 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
4623 if (VT.is64BitVector() && EltSz == 32)
4629 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
4630 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4631 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
4632 static bool isVUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
4633 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4637 unsigned Half = VT.getVectorNumElements() / 2;
4638 WhichResult = (M[0] == 0 ? 0 : 1);
4639 for (unsigned j = 0; j != 2; ++j) {
4640 unsigned Idx = WhichResult;
4641 for (unsigned i = 0; i != Half; ++i) {
4642 int MIdx = M[i + j * Half];
4643 if (MIdx >= 0 && (unsigned) MIdx != Idx)
4649 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
4650 if (VT.is64BitVector() && EltSz == 32)
4656 static bool isVZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4657 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4661 unsigned NumElts = VT.getVectorNumElements();
4662 WhichResult = (M[0] == 0 ? 0 : 1);
4663 unsigned Idx = WhichResult * NumElts / 2;
4664 for (unsigned i = 0; i != NumElts; i += 2) {
4665 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
4666 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
4671 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
4672 if (VT.is64BitVector() && EltSz == 32)
4678 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
4679 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4680 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
4681 static bool isVZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
4682 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4686 unsigned NumElts = VT.getVectorNumElements();
4687 WhichResult = (M[0] == 0 ? 0 : 1);
4688 unsigned Idx = WhichResult * NumElts / 2;
4689 for (unsigned i = 0; i != NumElts; i += 2) {
4690 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
4691 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
4696 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
4697 if (VT.is64BitVector() && EltSz == 32)
4703 /// \return true if this is a reverse operation on an vector.
4704 static bool isReverseMask(ArrayRef<int> M, EVT VT) {
4705 unsigned NumElts = VT.getVectorNumElements();
4706 // Make sure the mask has the right size.
4707 if (NumElts != M.size())
4710 // Look for <15, ..., 3, -1, 1, 0>.
4711 for (unsigned i = 0; i != NumElts; ++i)
4712 if (M[i] >= 0 && M[i] != (int) (NumElts - 1 - i))
4718 // If N is an integer constant that can be moved into a register in one
4719 // instruction, return an SDValue of such a constant (will become a MOV
4720 // instruction). Otherwise return null.
4721 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
4722 const ARMSubtarget *ST, SDLoc dl) {
4724 if (!isa<ConstantSDNode>(N))
4726 Val = cast<ConstantSDNode>(N)->getZExtValue();
4728 if (ST->isThumb1Only()) {
4729 if (Val <= 255 || ~Val <= 255)
4730 return DAG.getConstant(Val, MVT::i32);
4732 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
4733 return DAG.getConstant(Val, MVT::i32);
4738 // If this is a case we can't handle, return null and let the default
4739 // expansion code take care of it.
4740 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
4741 const ARMSubtarget *ST) const {
4742 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
4744 EVT VT = Op.getValueType();
4746 APInt SplatBits, SplatUndef;
4747 unsigned SplatBitSize;
4749 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
4750 if (SplatBitSize <= 64) {
4751 // Check if an immediate VMOV works.
4753 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
4754 SplatUndef.getZExtValue(), SplatBitSize,
4755 DAG, VmovVT, VT.is128BitVector(),
4757 if (Val.getNode()) {
4758 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
4759 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
4762 // Try an immediate VMVN.
4763 uint64_t NegatedImm = (~SplatBits).getZExtValue();
4764 Val = isNEONModifiedImm(NegatedImm,
4765 SplatUndef.getZExtValue(), SplatBitSize,
4766 DAG, VmovVT, VT.is128BitVector(),
4768 if (Val.getNode()) {
4769 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
4770 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
4773 // Use vmov.f32 to materialize other v2f32 and v4f32 splats.
4774 if ((VT == MVT::v2f32 || VT == MVT::v4f32) && SplatBitSize == 32) {
4775 int ImmVal = ARM_AM::getFP32Imm(SplatBits);
4777 SDValue Val = DAG.getTargetConstant(ImmVal, MVT::i32);
4778 return DAG.getNode(ARMISD::VMOVFPIMM, dl, VT, Val);
4784 // Scan through the operands to see if only one value is used.
4786 // As an optimisation, even if more than one value is used it may be more
4787 // profitable to splat with one value then change some lanes.
4789 // Heuristically we decide to do this if the vector has a "dominant" value,
4790 // defined as splatted to more than half of the lanes.
4791 unsigned NumElts = VT.getVectorNumElements();
4792 bool isOnlyLowElement = true;
4793 bool usesOnlyOneValue = true;
4794 bool hasDominantValue = false;
4795 bool isConstant = true;
4797 // Map of the number of times a particular SDValue appears in the
4799 DenseMap<SDValue, unsigned> ValueCounts;
4801 for (unsigned i = 0; i < NumElts; ++i) {
4802 SDValue V = Op.getOperand(i);
4803 if (V.getOpcode() == ISD::UNDEF)
4806 isOnlyLowElement = false;
4807 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
4810 ValueCounts.insert(std::make_pair(V, 0));
4811 unsigned &Count = ValueCounts[V];
4813 // Is this value dominant? (takes up more than half of the lanes)
4814 if (++Count > (NumElts / 2)) {
4815 hasDominantValue = true;
4819 if (ValueCounts.size() != 1)
4820 usesOnlyOneValue = false;
4821 if (!Value.getNode() && ValueCounts.size() > 0)
4822 Value = ValueCounts.begin()->first;
4824 if (ValueCounts.size() == 0)
4825 return DAG.getUNDEF(VT);
4827 // Loads are better lowered with insert_vector_elt/ARMISD::BUILD_VECTOR.
4828 // Keep going if we are hitting this case.
4829 if (isOnlyLowElement && !ISD::isNormalLoad(Value.getNode()))
4830 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
4832 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4834 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
4835 // i32 and try again.
4836 if (hasDominantValue && EltSize <= 32) {
4840 // If we are VDUPing a value that comes directly from a vector, that will
4841 // cause an unnecessary move to and from a GPR, where instead we could
4842 // just use VDUPLANE. We can only do this if the lane being extracted
4843 // is at a constant index, as the VDUP from lane instructions only have
4844 // constant-index forms.
4845 if (Value->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
4846 isa<ConstantSDNode>(Value->getOperand(1))) {
4847 // We need to create a new undef vector to use for the VDUPLANE if the
4848 // size of the vector from which we get the value is different than the
4849 // size of the vector that we need to create. We will insert the element
4850 // such that the register coalescer will remove unnecessary copies.
4851 if (VT != Value->getOperand(0).getValueType()) {
4852 ConstantSDNode *constIndex;
4853 constIndex = dyn_cast<ConstantSDNode>(Value->getOperand(1));
4854 assert(constIndex && "The index is not a constant!");
4855 unsigned index = constIndex->getAPIntValue().getLimitedValue() %
4856 VT.getVectorNumElements();
4857 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
4858 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DAG.getUNDEF(VT),
4859 Value, DAG.getConstant(index, MVT::i32)),
4860 DAG.getConstant(index, MVT::i32));
4862 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
4863 Value->getOperand(0), Value->getOperand(1));
4865 N = DAG.getNode(ARMISD::VDUP, dl, VT, Value);
4867 if (!usesOnlyOneValue) {
4868 // The dominant value was splatted as 'N', but we now have to insert
4869 // all differing elements.
4870 for (unsigned I = 0; I < NumElts; ++I) {
4871 if (Op.getOperand(I) == Value)
4873 SmallVector<SDValue, 3> Ops;
4875 Ops.push_back(Op.getOperand(I));
4876 Ops.push_back(DAG.getConstant(I, MVT::i32));
4877 N = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, &Ops[0], 3);
4882 if (VT.getVectorElementType().isFloatingPoint()) {
4883 SmallVector<SDValue, 8> Ops;
4884 for (unsigned i = 0; i < NumElts; ++i)
4885 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
4887 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
4888 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts);
4889 Val = LowerBUILD_VECTOR(Val, DAG, ST);
4891 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4893 if (usesOnlyOneValue) {
4894 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
4895 if (isConstant && Val.getNode())
4896 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
4900 // If all elements are constants and the case above didn't get hit, fall back
4901 // to the default expansion, which will generate a load from the constant
4906 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
4908 SDValue shuffle = ReconstructShuffle(Op, DAG);
4909 if (shuffle != SDValue())
4913 // Vectors with 32- or 64-bit elements can be built by directly assigning
4914 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
4915 // will be legalized.
4916 if (EltSize >= 32) {
4917 // Do the expansion with floating-point types, since that is what the VFP
4918 // registers are defined to use, and since i64 is not legal.
4919 EVT EltVT = EVT::getFloatingPointVT(EltSize);
4920 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
4921 SmallVector<SDValue, 8> Ops;
4922 for (unsigned i = 0; i < NumElts; ++i)
4923 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
4924 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
4925 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4928 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
4929 // know the default expansion would otherwise fall back on something even
4930 // worse. For a vector with one or two non-undef values, that's
4931 // scalar_to_vector for the elements followed by a shuffle (provided the
4932 // shuffle is valid for the target) and materialization element by element
4933 // on the stack followed by a load for everything else.
4934 if (!isConstant && !usesOnlyOneValue) {
4935 SDValue Vec = DAG.getUNDEF(VT);
4936 for (unsigned i = 0 ; i < NumElts; ++i) {
4937 SDValue V = Op.getOperand(i);
4938 if (V.getOpcode() == ISD::UNDEF)
4940 SDValue LaneIdx = DAG.getConstant(i, MVT::i32);
4941 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
4949 // Gather data to see if the operation can be modelled as a
4950 // shuffle in combination with VEXTs.
4951 SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
4952 SelectionDAG &DAG) const {
4954 EVT VT = Op.getValueType();
4955 unsigned NumElts = VT.getVectorNumElements();
4957 SmallVector<SDValue, 2> SourceVecs;
4958 SmallVector<unsigned, 2> MinElts;
4959 SmallVector<unsigned, 2> MaxElts;
4961 for (unsigned i = 0; i < NumElts; ++i) {
4962 SDValue V = Op.getOperand(i);
4963 if (V.getOpcode() == ISD::UNDEF)
4965 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4966 // A shuffle can only come from building a vector from various
4967 // elements of other vectors.
4969 } else if (V.getOperand(0).getValueType().getVectorElementType() !=
4970 VT.getVectorElementType()) {
4971 // This code doesn't know how to handle shuffles where the vector
4972 // element types do not match (this happens because type legalization
4973 // promotes the return type of EXTRACT_VECTOR_ELT).
4974 // FIXME: It might be appropriate to extend this code to handle
4975 // mismatched types.
4979 // Record this extraction against the appropriate vector if possible...
4980 SDValue SourceVec = V.getOperand(0);
4981 // If the element number isn't a constant, we can't effectively
4982 // analyze what's going on.
4983 if (!isa<ConstantSDNode>(V.getOperand(1)))
4985 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4986 bool FoundSource = false;
4987 for (unsigned j = 0; j < SourceVecs.size(); ++j) {
4988 if (SourceVecs[j] == SourceVec) {
4989 if (MinElts[j] > EltNo)
4991 if (MaxElts[j] < EltNo)
4998 // Or record a new source if not...
5000 SourceVecs.push_back(SourceVec);
5001 MinElts.push_back(EltNo);
5002 MaxElts.push_back(EltNo);
5006 // Currently only do something sane when at most two source vectors
5008 if (SourceVecs.size() > 2)
5011 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
5012 int VEXTOffsets[2] = {0, 0};
5014 // This loop extracts the usage patterns of the source vectors
5015 // and prepares appropriate SDValues for a shuffle if possible.
5016 for (unsigned i = 0; i < SourceVecs.size(); ++i) {
5017 if (SourceVecs[i].getValueType() == VT) {
5018 // No VEXT necessary
5019 ShuffleSrcs[i] = SourceVecs[i];
5022 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) {
5023 // It probably isn't worth padding out a smaller vector just to
5024 // break it down again in a shuffle.
5028 // Since only 64-bit and 128-bit vectors are legal on ARM and
5029 // we've eliminated the other cases...
5030 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts &&
5031 "unexpected vector sizes in ReconstructShuffle");
5033 if (MaxElts[i] - MinElts[i] >= NumElts) {
5034 // Span too large for a VEXT to cope
5038 if (MinElts[i] >= NumElts) {
5039 // The extraction can just take the second half
5040 VEXTOffsets[i] = NumElts;
5041 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5043 DAG.getIntPtrConstant(NumElts));
5044 } else if (MaxElts[i] < NumElts) {
5045 // The extraction can just take the first half
5047 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5049 DAG.getIntPtrConstant(0));
5051 // An actual VEXT is needed
5052 VEXTOffsets[i] = MinElts[i];
5053 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5055 DAG.getIntPtrConstant(0));
5056 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5058 DAG.getIntPtrConstant(NumElts));
5059 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2,
5060 DAG.getConstant(VEXTOffsets[i], MVT::i32));
5064 SmallVector<int, 8> Mask;
5066 for (unsigned i = 0; i < NumElts; ++i) {
5067 SDValue Entry = Op.getOperand(i);
5068 if (Entry.getOpcode() == ISD::UNDEF) {
5073 SDValue ExtractVec = Entry.getOperand(0);
5074 int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i)
5075 .getOperand(1))->getSExtValue();
5076 if (ExtractVec == SourceVecs[0]) {
5077 Mask.push_back(ExtractElt - VEXTOffsets[0]);
5079 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]);
5083 // Final check before we try to produce nonsense...
5084 if (isShuffleMaskLegal(Mask, VT))
5085 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
5091 /// isShuffleMaskLegal - Targets can use this to indicate that they only
5092 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
5093 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
5094 /// are assumed to be legal.
5096 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
5098 if (VT.getVectorNumElements() == 4 &&
5099 (VT.is128BitVector() || VT.is64BitVector())) {
5100 unsigned PFIndexes[4];
5101 for (unsigned i = 0; i != 4; ++i) {
5105 PFIndexes[i] = M[i];
5108 // Compute the index in the perfect shuffle table.
5109 unsigned PFTableIndex =
5110 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5111 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5112 unsigned Cost = (PFEntry >> 30);
5119 unsigned Imm, WhichResult;
5121 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5122 return (EltSize >= 32 ||
5123 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
5124 isVREVMask(M, VT, 64) ||
5125 isVREVMask(M, VT, 32) ||
5126 isVREVMask(M, VT, 16) ||
5127 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
5128 isVTBLMask(M, VT) ||
5129 isVTRNMask(M, VT, WhichResult) ||
5130 isVUZPMask(M, VT, WhichResult) ||
5131 isVZIPMask(M, VT, WhichResult) ||
5132 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
5133 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
5134 isVZIP_v_undef_Mask(M, VT, WhichResult) ||
5135 ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(M, VT)));
5138 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5139 /// the specified operations to build the shuffle.
5140 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5141 SDValue RHS, SelectionDAG &DAG,
5143 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5144 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5145 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5148 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5157 OP_VUZPL, // VUZP, left result
5158 OP_VUZPR, // VUZP, right result
5159 OP_VZIPL, // VZIP, left result
5160 OP_VZIPR, // VZIP, right result
5161 OP_VTRNL, // VTRN, left result
5162 OP_VTRNR // VTRN, right result
5165 if (OpNum == OP_COPY) {
5166 if (LHSID == (1*9+2)*9+3) return LHS;
5167 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5171 SDValue OpLHS, OpRHS;
5172 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5173 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5174 EVT VT = OpLHS.getValueType();
5177 default: llvm_unreachable("Unknown shuffle opcode!");
5179 // VREV divides the vector in half and swaps within the half.
5180 if (VT.getVectorElementType() == MVT::i32 ||
5181 VT.getVectorElementType() == MVT::f32)
5182 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
5183 // vrev <4 x i16> -> VREV32
5184 if (VT.getVectorElementType() == MVT::i16)
5185 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS);
5186 // vrev <4 x i8> -> VREV16
5187 assert(VT.getVectorElementType() == MVT::i8);
5188 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS);
5193 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
5194 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
5198 return DAG.getNode(ARMISD::VEXT, dl, VT,
5200 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
5203 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
5204 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
5207 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
5208 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
5211 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
5212 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
5216 static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
5217 ArrayRef<int> ShuffleMask,
5218 SelectionDAG &DAG) {
5219 // Check to see if we can use the VTBL instruction.
5220 SDValue V1 = Op.getOperand(0);
5221 SDValue V2 = Op.getOperand(1);
5224 SmallVector<SDValue, 8> VTBLMask;
5225 for (ArrayRef<int>::iterator
5226 I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I)
5227 VTBLMask.push_back(DAG.getConstant(*I, MVT::i32));
5229 if (V2.getNode()->getOpcode() == ISD::UNDEF)
5230 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
5231 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
5234 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
5235 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
5239 static SDValue LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(SDValue Op,
5240 SelectionDAG &DAG) {
5242 SDValue OpLHS = Op.getOperand(0);
5243 EVT VT = OpLHS.getValueType();
5245 assert((VT == MVT::v8i16 || VT == MVT::v16i8) &&
5246 "Expect an v8i16/v16i8 type");
5247 OpLHS = DAG.getNode(ARMISD::VREV64, DL, VT, OpLHS);
5248 // For a v16i8 type: After the VREV, we have got <8, ...15, 8, ..., 0>. Now,
5249 // extract the first 8 bytes into the top double word and the last 8 bytes
5250 // into the bottom double word. The v8i16 case is similar.
5251 unsigned ExtractNum = (VT == MVT::v16i8) ? 8 : 4;
5252 return DAG.getNode(ARMISD::VEXT, DL, VT, OpLHS, OpLHS,
5253 DAG.getConstant(ExtractNum, MVT::i32));
5256 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
5257 SDValue V1 = Op.getOperand(0);
5258 SDValue V2 = Op.getOperand(1);
5260 EVT VT = Op.getValueType();
5261 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
5263 // Convert shuffles that are directly supported on NEON to target-specific
5264 // DAG nodes, instead of keeping them as shuffles and matching them again
5265 // during code selection. This is more efficient and avoids the possibility
5266 // of inconsistencies between legalization and selection.
5267 // FIXME: floating-point vectors should be canonicalized to integer vectors
5268 // of the same time so that they get CSEd properly.
5269 ArrayRef<int> ShuffleMask = SVN->getMask();
5271 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5272 if (EltSize <= 32) {
5273 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
5274 int Lane = SVN->getSplatIndex();
5275 // If this is undef splat, generate it via "just" vdup, if possible.
5276 if (Lane == -1) Lane = 0;
5278 // Test if V1 is a SCALAR_TO_VECTOR.
5279 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5280 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
5282 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
5283 // (and probably will turn into a SCALAR_TO_VECTOR once legalization
5285 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
5286 !isa<ConstantSDNode>(V1.getOperand(0))) {
5287 bool IsScalarToVector = true;
5288 for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i)
5289 if (V1.getOperand(i).getOpcode() != ISD::UNDEF) {
5290 IsScalarToVector = false;
5293 if (IsScalarToVector)
5294 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
5296 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
5297 DAG.getConstant(Lane, MVT::i32));
5302 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
5305 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
5306 DAG.getConstant(Imm, MVT::i32));
5309 if (isVREVMask(ShuffleMask, VT, 64))
5310 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
5311 if (isVREVMask(ShuffleMask, VT, 32))
5312 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
5313 if (isVREVMask(ShuffleMask, VT, 16))
5314 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
5316 if (V2->getOpcode() == ISD::UNDEF &&
5317 isSingletonVEXTMask(ShuffleMask, VT, Imm)) {
5318 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V1,
5319 DAG.getConstant(Imm, MVT::i32));
5322 // Check for Neon shuffles that modify both input vectors in place.
5323 // If both results are used, i.e., if there are two shuffles with the same
5324 // source operands and with masks corresponding to both results of one of
5325 // these operations, DAG memoization will ensure that a single node is
5326 // used for both shuffles.
5327 unsigned WhichResult;
5328 if (isVTRNMask(ShuffleMask, VT, WhichResult))
5329 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
5330 V1, V2).getValue(WhichResult);
5331 if (isVUZPMask(ShuffleMask, VT, WhichResult))
5332 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
5333 V1, V2).getValue(WhichResult);
5334 if (isVZIPMask(ShuffleMask, VT, WhichResult))
5335 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
5336 V1, V2).getValue(WhichResult);
5338 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
5339 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
5340 V1, V1).getValue(WhichResult);
5341 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
5342 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
5343 V1, V1).getValue(WhichResult);
5344 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
5345 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
5346 V1, V1).getValue(WhichResult);
5349 // If the shuffle is not directly supported and it has 4 elements, use
5350 // the PerfectShuffle-generated table to synthesize it from other shuffles.
5351 unsigned NumElts = VT.getVectorNumElements();
5353 unsigned PFIndexes[4];
5354 for (unsigned i = 0; i != 4; ++i) {
5355 if (ShuffleMask[i] < 0)
5358 PFIndexes[i] = ShuffleMask[i];
5361 // Compute the index in the perfect shuffle table.
5362 unsigned PFTableIndex =
5363 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5364 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5365 unsigned Cost = (PFEntry >> 30);
5368 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5371 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
5372 if (EltSize >= 32) {
5373 // Do the expansion with floating-point types, since that is what the VFP
5374 // registers are defined to use, and since i64 is not legal.
5375 EVT EltVT = EVT::getFloatingPointVT(EltSize);
5376 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
5377 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
5378 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
5379 SmallVector<SDValue, 8> Ops;
5380 for (unsigned i = 0; i < NumElts; ++i) {
5381 if (ShuffleMask[i] < 0)
5382 Ops.push_back(DAG.getUNDEF(EltVT));
5384 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
5385 ShuffleMask[i] < (int)NumElts ? V1 : V2,
5386 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
5389 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
5390 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5393 if ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(ShuffleMask, VT))
5394 return LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(Op, DAG);
5396 if (VT == MVT::v8i8) {
5397 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG);
5398 if (NewOp.getNode())
5405 static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
5406 // INSERT_VECTOR_ELT is legal only for immediate indexes.
5407 SDValue Lane = Op.getOperand(2);
5408 if (!isa<ConstantSDNode>(Lane))
5414 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
5415 // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
5416 SDValue Lane = Op.getOperand(1);
5417 if (!isa<ConstantSDNode>(Lane))
5420 SDValue Vec = Op.getOperand(0);
5421 if (Op.getValueType() == MVT::i32 &&
5422 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) {
5424 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
5430 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5431 // The only time a CONCAT_VECTORS operation can have legal types is when
5432 // two 64-bit vectors are concatenated to a 128-bit vector.
5433 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
5434 "unexpected CONCAT_VECTORS");
5436 SDValue Val = DAG.getUNDEF(MVT::v2f64);
5437 SDValue Op0 = Op.getOperand(0);
5438 SDValue Op1 = Op.getOperand(1);
5439 if (Op0.getOpcode() != ISD::UNDEF)
5440 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
5441 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
5442 DAG.getIntPtrConstant(0));
5443 if (Op1.getOpcode() != ISD::UNDEF)
5444 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
5445 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
5446 DAG.getIntPtrConstant(1));
5447 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
5450 /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
5451 /// element has been zero/sign-extended, depending on the isSigned parameter,
5452 /// from an integer type half its size.
5453 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
5455 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
5456 EVT VT = N->getValueType(0);
5457 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
5458 SDNode *BVN = N->getOperand(0).getNode();
5459 if (BVN->getValueType(0) != MVT::v4i32 ||
5460 BVN->getOpcode() != ISD::BUILD_VECTOR)
5462 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
5463 unsigned HiElt = 1 - LoElt;
5464 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
5465 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
5466 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
5467 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
5468 if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
5471 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 &&
5472 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
5475 if (Hi0->isNullValue() && Hi1->isNullValue())
5481 if (N->getOpcode() != ISD::BUILD_VECTOR)
5484 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
5485 SDNode *Elt = N->getOperand(i).getNode();
5486 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
5487 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5488 unsigned HalfSize = EltSize / 2;
5490 if (!isIntN(HalfSize, C->getSExtValue()))
5493 if (!isUIntN(HalfSize, C->getZExtValue()))
5504 /// isSignExtended - Check if a node is a vector value that is sign-extended
5505 /// or a constant BUILD_VECTOR with sign-extended elements.
5506 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
5507 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
5509 if (isExtendedBUILD_VECTOR(N, DAG, true))
5514 /// isZeroExtended - Check if a node is a vector value that is zero-extended
5515 /// or a constant BUILD_VECTOR with zero-extended elements.
5516 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
5517 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
5519 if (isExtendedBUILD_VECTOR(N, DAG, false))
5524 static EVT getExtensionTo64Bits(const EVT &OrigVT) {
5525 if (OrigVT.getSizeInBits() >= 64)
5528 assert(OrigVT.isSimple() && "Expecting a simple value type");
5530 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
5531 switch (OrigSimpleTy) {
5532 default: llvm_unreachable("Unexpected Vector Type");
5541 /// AddRequiredExtensionForVMULL - Add a sign/zero extension to extend the total
5542 /// value size to 64 bits. We need a 64-bit D register as an operand to VMULL.
5543 /// We insert the required extension here to get the vector to fill a D register.
5544 static SDValue AddRequiredExtensionForVMULL(SDValue N, SelectionDAG &DAG,
5547 unsigned ExtOpcode) {
5548 // The vector originally had a size of OrigTy. It was then extended to ExtTy.
5549 // We expect the ExtTy to be 128-bits total. If the OrigTy is less than
5550 // 64-bits we need to insert a new extension so that it will be 64-bits.
5551 assert(ExtTy.is128BitVector() && "Unexpected extension size");
5552 if (OrigTy.getSizeInBits() >= 64)
5555 // Must extend size to at least 64 bits to be used as an operand for VMULL.
5556 EVT NewVT = getExtensionTo64Bits(OrigTy);
5558 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
5561 /// SkipLoadExtensionForVMULL - return a load of the original vector size that
5562 /// does not do any sign/zero extension. If the original vector is less
5563 /// than 64 bits, an appropriate extension will be added after the load to
5564 /// reach a total size of 64 bits. We have to add the extension separately
5565 /// because ARM does not have a sign/zero extending load for vectors.
5566 static SDValue SkipLoadExtensionForVMULL(LoadSDNode *LD, SelectionDAG& DAG) {
5567 EVT ExtendedTy = getExtensionTo64Bits(LD->getMemoryVT());
5569 // The load already has the right type.
5570 if (ExtendedTy == LD->getMemoryVT())
5571 return DAG.getLoad(LD->getMemoryVT(), SDLoc(LD), LD->getChain(),
5572 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
5573 LD->isNonTemporal(), LD->isInvariant(),
5574 LD->getAlignment());
5576 // We need to create a zextload/sextload. We cannot just create a load
5577 // followed by a zext/zext node because LowerMUL is also run during normal
5578 // operation legalization where we can't create illegal types.
5579 return DAG.getExtLoad(LD->getExtensionType(), SDLoc(LD), ExtendedTy,
5580 LD->getChain(), LD->getBasePtr(), LD->getPointerInfo(),
5581 LD->getMemoryVT(), LD->isVolatile(),
5582 LD->isNonTemporal(), LD->getAlignment());
5585 /// SkipExtensionForVMULL - For a node that is a SIGN_EXTEND, ZERO_EXTEND,
5586 /// extending load, or BUILD_VECTOR with extended elements, return the
5587 /// unextended value. The unextended vector should be 64 bits so that it can
5588 /// be used as an operand to a VMULL instruction. If the original vector size
5589 /// before extension is less than 64 bits we add a an extension to resize
5590 /// the vector to 64 bits.
5591 static SDValue SkipExtensionForVMULL(SDNode *N, SelectionDAG &DAG) {
5592 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
5593 return AddRequiredExtensionForVMULL(N->getOperand(0), DAG,
5594 N->getOperand(0)->getValueType(0),
5598 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
5599 return SkipLoadExtensionForVMULL(LD, DAG);
5601 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
5602 // have been legalized as a BITCAST from v4i32.
5603 if (N->getOpcode() == ISD::BITCAST) {
5604 SDNode *BVN = N->getOperand(0).getNode();
5605 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
5606 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
5607 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
5608 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), MVT::v2i32,
5609 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2));
5611 // Construct a new BUILD_VECTOR with elements truncated to half the size.
5612 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
5613 EVT VT = N->getValueType(0);
5614 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
5615 unsigned NumElts = VT.getVectorNumElements();
5616 MVT TruncVT = MVT::getIntegerVT(EltSize);
5617 SmallVector<SDValue, 8> Ops;
5618 for (unsigned i = 0; i != NumElts; ++i) {
5619 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
5620 const APInt &CInt = C->getAPIntValue();
5621 // Element types smaller than 32 bits are not legal, so use i32 elements.
5622 // The values are implicitly truncated so sext vs. zext doesn't matter.
5623 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), MVT::i32));
5625 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N),
5626 MVT::getVectorVT(TruncVT, NumElts), Ops.data(), NumElts);
5629 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
5630 unsigned Opcode = N->getOpcode();
5631 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
5632 SDNode *N0 = N->getOperand(0).getNode();
5633 SDNode *N1 = N->getOperand(1).getNode();
5634 return N0->hasOneUse() && N1->hasOneUse() &&
5635 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
5640 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
5641 unsigned Opcode = N->getOpcode();
5642 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
5643 SDNode *N0 = N->getOperand(0).getNode();
5644 SDNode *N1 = N->getOperand(1).getNode();
5645 return N0->hasOneUse() && N1->hasOneUse() &&
5646 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
5651 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
5652 // Multiplications are only custom-lowered for 128-bit vectors so that
5653 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
5654 EVT VT = Op.getValueType();
5655 assert(VT.is128BitVector() && VT.isInteger() &&
5656 "unexpected type for custom-lowering ISD::MUL");
5657 SDNode *N0 = Op.getOperand(0).getNode();
5658 SDNode *N1 = Op.getOperand(1).getNode();
5659 unsigned NewOpc = 0;
5661 bool isN0SExt = isSignExtended(N0, DAG);
5662 bool isN1SExt = isSignExtended(N1, DAG);
5663 if (isN0SExt && isN1SExt)
5664 NewOpc = ARMISD::VMULLs;
5666 bool isN0ZExt = isZeroExtended(N0, DAG);
5667 bool isN1ZExt = isZeroExtended(N1, DAG);
5668 if (isN0ZExt && isN1ZExt)
5669 NewOpc = ARMISD::VMULLu;
5670 else if (isN1SExt || isN1ZExt) {
5671 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
5672 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
5673 if (isN1SExt && isAddSubSExt(N0, DAG)) {
5674 NewOpc = ARMISD::VMULLs;
5676 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
5677 NewOpc = ARMISD::VMULLu;
5679 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
5681 NewOpc = ARMISD::VMULLu;
5687 if (VT == MVT::v2i64)
5688 // Fall through to expand this. It is not legal.
5691 // Other vector multiplications are legal.
5696 // Legalize to a VMULL instruction.
5699 SDValue Op1 = SkipExtensionForVMULL(N1, DAG);
5701 Op0 = SkipExtensionForVMULL(N0, DAG);
5702 assert(Op0.getValueType().is64BitVector() &&
5703 Op1.getValueType().is64BitVector() &&
5704 "unexpected types for extended operands to VMULL");
5705 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
5708 // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during
5709 // isel lowering to take advantage of no-stall back to back vmul + vmla.
5716 SDValue N00 = SkipExtensionForVMULL(N0->getOperand(0).getNode(), DAG);
5717 SDValue N01 = SkipExtensionForVMULL(N0->getOperand(1).getNode(), DAG);
5718 EVT Op1VT = Op1.getValueType();
5719 return DAG.getNode(N0->getOpcode(), DL, VT,
5720 DAG.getNode(NewOpc, DL, VT,
5721 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
5722 DAG.getNode(NewOpc, DL, VT,
5723 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
5727 LowerSDIV_v4i8(SDValue X, SDValue Y, SDLoc dl, SelectionDAG &DAG) {
5729 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo));
5730 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo));
5731 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
5732 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
5733 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X);
5734 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y);
5735 // Get reciprocal estimate.
5736 // float4 recip = vrecpeq_f32(yf);
5737 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5738 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y);
5739 // Because char has a smaller range than uchar, we can actually get away
5740 // without any newton steps. This requires that we use a weird bias
5741 // of 0xb000, however (again, this has been exhaustively tested).
5742 // float4 result = as_float4(as_int4(xf*recip) + 0xb000);
5743 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y);
5744 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X);
5745 Y = DAG.getConstant(0xb000, MVT::i32);
5746 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y);
5747 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y);
5748 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X);
5749 // Convert back to short.
5750 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
5751 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X);
5756 LowerSDIV_v4i16(SDValue N0, SDValue N1, SDLoc dl, SelectionDAG &DAG) {
5758 // Convert to float.
5759 // float4 yf = vcvt_f32_s32(vmovl_s16(y));
5760 // float4 xf = vcvt_f32_s32(vmovl_s16(x));
5761 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
5762 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
5763 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
5764 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
5766 // Use reciprocal estimate and one refinement step.
5767 // float4 recip = vrecpeq_f32(yf);
5768 // recip *= vrecpsq_f32(yf, recip);
5769 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5770 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
5771 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5772 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
5774 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
5775 // Because short has a smaller range than ushort, we can actually get away
5776 // with only a single newton step. This requires that we use a weird bias
5777 // of 89, however (again, this has been exhaustively tested).
5778 // float4 result = as_float4(as_int4(xf*recip) + 0x89);
5779 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
5780 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
5781 N1 = DAG.getConstant(0x89, MVT::i32);
5782 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
5783 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
5784 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
5785 // Convert back to integer and return.
5786 // return vmovn_s32(vcvt_s32_f32(result));
5787 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
5788 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
5792 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
5793 EVT VT = Op.getValueType();
5794 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
5795 "unexpected type for custom-lowering ISD::SDIV");
5798 SDValue N0 = Op.getOperand(0);
5799 SDValue N1 = Op.getOperand(1);
5802 if (VT == MVT::v8i8) {
5803 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
5804 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
5806 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
5807 DAG.getIntPtrConstant(4));
5808 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
5809 DAG.getIntPtrConstant(4));
5810 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
5811 DAG.getIntPtrConstant(0));
5812 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
5813 DAG.getIntPtrConstant(0));
5815 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
5816 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16
5818 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
5819 N0 = LowerCONCAT_VECTORS(N0, DAG);
5821 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
5824 return LowerSDIV_v4i16(N0, N1, dl, DAG);
5827 static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) {
5828 EVT VT = Op.getValueType();
5829 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
5830 "unexpected type for custom-lowering ISD::UDIV");
5833 SDValue N0 = Op.getOperand(0);
5834 SDValue N1 = Op.getOperand(1);
5837 if (VT == MVT::v8i8) {
5838 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
5839 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
5841 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
5842 DAG.getIntPtrConstant(4));
5843 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
5844 DAG.getIntPtrConstant(4));
5845 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
5846 DAG.getIntPtrConstant(0));
5847 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
5848 DAG.getIntPtrConstant(0));
5850 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
5851 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
5853 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
5854 N0 = LowerCONCAT_VECTORS(N0, DAG);
5856 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
5857 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32),
5862 // v4i16 sdiv ... Convert to float.
5863 // float4 yf = vcvt_f32_s32(vmovl_u16(y));
5864 // float4 xf = vcvt_f32_s32(vmovl_u16(x));
5865 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
5866 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
5867 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
5868 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
5870 // Use reciprocal estimate and two refinement steps.
5871 // float4 recip = vrecpeq_f32(yf);
5872 // recip *= vrecpsq_f32(yf, recip);
5873 // recip *= vrecpsq_f32(yf, recip);
5874 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5875 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), BN1);
5876 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5877 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
5879 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
5880 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5881 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
5883 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
5884 // Simply multiplying by the reciprocal estimate can leave us a few ulps
5885 // too low, so we add 2 ulps (exhaustive testing shows that this is enough,
5886 // and that it will never cause us to return an answer too large).
5887 // float4 result = as_float4(as_int4(xf*recip) + 2);
5888 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
5889 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
5890 N1 = DAG.getConstant(2, MVT::i32);
5891 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
5892 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
5893 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
5894 // Convert back to integer and return.
5895 // return vmovn_u32(vcvt_s32_f32(result));
5896 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
5897 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
5901 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
5902 EVT VT = Op.getNode()->getValueType(0);
5903 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
5906 bool ExtraOp = false;
5907 switch (Op.getOpcode()) {
5908 default: llvm_unreachable("Invalid code");
5909 case ISD::ADDC: Opc = ARMISD::ADDC; break;
5910 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break;
5911 case ISD::SUBC: Opc = ARMISD::SUBC; break;
5912 case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break;
5916 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
5918 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
5919 Op.getOperand(1), Op.getOperand(2));
5922 SDValue ARMTargetLowering::LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const {
5923 assert(Subtarget->isTargetDarwin());
5925 // For iOS, we want to call an alternative entry point: __sincos_stret,
5926 // return values are passed via sret.
5928 SDValue Arg = Op.getOperand(0);
5929 EVT ArgVT = Arg.getValueType();
5930 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
5932 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
5933 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5935 // Pair of floats / doubles used to pass the result.
5936 StructType *RetTy = StructType::get(ArgTy, ArgTy, NULL);
5938 // Create stack object for sret.
5939 const uint64_t ByteSize = TLI.getDataLayout()->getTypeAllocSize(RetTy);
5940 const unsigned StackAlign = TLI.getDataLayout()->getPrefTypeAlignment(RetTy);
5941 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign, false);
5942 SDValue SRet = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
5948 Entry.Ty = RetTy->getPointerTo();
5949 Entry.isSExt = false;
5950 Entry.isZExt = false;
5951 Entry.isSRet = true;
5952 Args.push_back(Entry);
5956 Entry.isSExt = false;
5957 Entry.isZExt = false;
5958 Args.push_back(Entry);
5960 const char *LibcallName = (ArgVT == MVT::f64)
5961 ? "__sincos_stret" : "__sincosf_stret";
5962 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
5965 CallLoweringInfo CLI(DAG.getEntryNode(), Type::getVoidTy(*DAG.getContext()),
5966 false, false, false, false, 0,
5967 CallingConv::C, /*isTaillCall=*/false,
5968 /*doesNotRet=*/false, /*isReturnValueUsed*/false,
5969 Callee, Args, DAG, dl);
5970 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
5972 SDValue LoadSin = DAG.getLoad(ArgVT, dl, CallResult.second, SRet,
5973 MachinePointerInfo(), false, false, false, 0);
5975 // Address of cos field.
5976 SDValue Add = DAG.getNode(ISD::ADD, dl, getPointerTy(), SRet,
5977 DAG.getIntPtrConstant(ArgVT.getStoreSize()));
5978 SDValue LoadCos = DAG.getLoad(ArgVT, dl, LoadSin.getValue(1), Add,
5979 MachinePointerInfo(), false, false, false, 0);
5981 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
5982 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys,
5983 LoadSin.getValue(0), LoadCos.getValue(0));
5986 static SDValue LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) {
5987 // Monotonic load/store is legal for all targets
5988 if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic)
5991 // Aquire/Release load/store is not legal for targets without a
5992 // dmb or equivalent available.
5997 ReplaceATOMIC_OP_64(SDNode *Node, SmallVectorImpl<SDValue>& Results,
5998 SelectionDAG &DAG) {
6000 assert (Node->getValueType(0) == MVT::i64 &&
6001 "Only know how to expand i64 atomics");
6002 AtomicSDNode *AN = cast<AtomicSDNode>(Node);
6004 SmallVector<SDValue, 6> Ops;
6005 Ops.push_back(Node->getOperand(0)); // Chain
6006 Ops.push_back(Node->getOperand(1)); // Ptr
6007 for(unsigned i=2; i<Node->getNumOperands(); i++) {
6009 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6010 Node->getOperand(i), DAG.getIntPtrConstant(0)));
6012 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6013 Node->getOperand(i), DAG.getIntPtrConstant(1)));
6015 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
6017 DAG.getAtomic(Node->getOpcode(), dl, MVT::i64, Tys, Ops.data(), Ops.size(),
6018 cast<MemSDNode>(Node)->getMemOperand(), AN->getOrdering(),
6019 AN->getSynchScope());
6020 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1) };
6021 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
6022 Results.push_back(Result.getValue(2));
6025 static void ReplaceREADCYCLECOUNTER(SDNode *N,
6026 SmallVectorImpl<SDValue> &Results,
6028 const ARMSubtarget *Subtarget) {
6030 SDValue Cycles32, OutChain;
6032 if (Subtarget->hasPerfMon()) {
6033 // Under Power Management extensions, the cycle-count is:
6034 // mrc p15, #0, <Rt>, c9, c13, #0
6035 SDValue Ops[] = { N->getOperand(0), // Chain
6036 DAG.getConstant(Intrinsic::arm_mrc, MVT::i32),
6037 DAG.getConstant(15, MVT::i32),
6038 DAG.getConstant(0, MVT::i32),
6039 DAG.getConstant(9, MVT::i32),
6040 DAG.getConstant(13, MVT::i32),
6041 DAG.getConstant(0, MVT::i32)
6044 Cycles32 = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
6045 DAG.getVTList(MVT::i32, MVT::Other), &Ops[0],
6046 array_lengthof(Ops));
6047 OutChain = Cycles32.getValue(1);
6049 // Intrinsic is defined to return 0 on unsupported platforms. Technically
6050 // there are older ARM CPUs that have implementation-specific ways of
6051 // obtaining this information (FIXME!).
6052 Cycles32 = DAG.getConstant(0, MVT::i32);
6053 OutChain = DAG.getEntryNode();
6057 SDValue Cycles64 = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64,
6058 Cycles32, DAG.getConstant(0, MVT::i32));
6059 Results.push_back(Cycles64);
6060 Results.push_back(OutChain);
6063 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6064 switch (Op.getOpcode()) {
6065 default: llvm_unreachable("Don't know how to custom lower this!");
6066 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6067 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6068 case ISD::GlobalAddress:
6069 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
6070 LowerGlobalAddressELF(Op, DAG);
6071 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6072 case ISD::SELECT: return LowerSELECT(Op, DAG);
6073 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6074 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
6075 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
6076 case ISD::VASTART: return LowerVASTART(Op, DAG);
6077 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget);
6078 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
6079 case ISD::SINT_TO_FP:
6080 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6081 case ISD::FP_TO_SINT:
6082 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
6083 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
6084 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6085 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6086 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
6087 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
6088 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
6089 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
6091 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG);
6094 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
6095 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
6096 case ISD::SRL_PARTS:
6097 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
6098 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
6099 case ISD::CTPOP: return LowerCTPOP(Op.getNode(), DAG, Subtarget);
6100 case ISD::SETCC: return LowerVSETCC(Op, DAG);
6101 case ISD::ConstantFP: return LowerConstantFP(Op, DAG, Subtarget);
6102 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
6103 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6104 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
6105 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
6106 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
6107 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6108 case ISD::MUL: return LowerMUL(Op, DAG);
6109 case ISD::SDIV: return LowerSDIV(Op, DAG);
6110 case ISD::UDIV: return LowerUDIV(Op, DAG);
6114 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
6115 case ISD::ATOMIC_LOAD:
6116 case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG);
6117 case ISD::FSINCOS: return LowerFSINCOS(Op, DAG);
6119 case ISD::UDIVREM: return LowerDivRem(Op, DAG);
6123 /// ReplaceNodeResults - Replace the results of node with an illegal result
6124 /// type with new values built out of custom code.
6125 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
6126 SmallVectorImpl<SDValue>&Results,
6127 SelectionDAG &DAG) const {
6129 switch (N->getOpcode()) {
6131 llvm_unreachable("Don't know how to custom expand this!");
6133 Res = ExpandBITCAST(N, DAG);
6137 Res = Expand64BitShift(N, DAG, Subtarget);
6139 case ISD::READCYCLECOUNTER:
6140 ReplaceREADCYCLECOUNTER(N, Results, DAG, Subtarget);
6142 case ISD::ATOMIC_STORE:
6143 case ISD::ATOMIC_LOAD:
6144 case ISD::ATOMIC_LOAD_ADD:
6145 case ISD::ATOMIC_LOAD_AND:
6146 case ISD::ATOMIC_LOAD_NAND:
6147 case ISD::ATOMIC_LOAD_OR:
6148 case ISD::ATOMIC_LOAD_SUB:
6149 case ISD::ATOMIC_LOAD_XOR:
6150 case ISD::ATOMIC_SWAP:
6151 case ISD::ATOMIC_CMP_SWAP:
6152 case ISD::ATOMIC_LOAD_MIN:
6153 case ISD::ATOMIC_LOAD_UMIN:
6154 case ISD::ATOMIC_LOAD_MAX:
6155 case ISD::ATOMIC_LOAD_UMAX:
6156 ReplaceATOMIC_OP_64(N, Results, DAG);
6160 Results.push_back(Res);
6163 //===----------------------------------------------------------------------===//
6164 // ARM Scheduler Hooks
6165 //===----------------------------------------------------------------------===//
6168 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
6169 MachineBasicBlock *BB,
6170 unsigned Size) const {
6171 unsigned dest = MI->getOperand(0).getReg();
6172 unsigned ptr = MI->getOperand(1).getReg();
6173 unsigned oldval = MI->getOperand(2).getReg();
6174 unsigned newval = MI->getOperand(3).getReg();
6175 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6176 AtomicOrdering Ord = static_cast<AtomicOrdering>(MI->getOperand(4).getImm());
6177 DebugLoc dl = MI->getDebugLoc();
6178 bool isThumb2 = Subtarget->isThumb2();
6180 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
6181 unsigned scratch = MRI.createVirtualRegister(isThumb2 ?
6182 (const TargetRegisterClass*)&ARM::rGPRRegClass :
6183 (const TargetRegisterClass*)&ARM::GPRRegClass);
6186 MRI.constrainRegClass(dest, &ARM::rGPRRegClass);
6187 MRI.constrainRegClass(oldval, &ARM::rGPRRegClass);
6188 MRI.constrainRegClass(newval, &ARM::rGPRRegClass);
6191 unsigned ldrOpc, strOpc;
6192 getExclusiveOperation(Size, Ord, isThumb2, ldrOpc, strOpc);
6194 MachineFunction *MF = BB->getParent();
6195 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6196 MachineFunction::iterator It = BB;
6197 ++It; // insert the new blocks after the current block
6199 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
6200 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
6201 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
6202 MF->insert(It, loop1MBB);
6203 MF->insert(It, loop2MBB);
6204 MF->insert(It, exitMBB);
6206 // Transfer the remainder of BB and its successor edges to exitMBB.
6207 exitMBB->splice(exitMBB->begin(), BB,
6208 llvm::next(MachineBasicBlock::iterator(MI)),
6210 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6214 // fallthrough --> loop1MBB
6215 BB->addSuccessor(loop1MBB);
6218 // ldrex dest, [ptr]
6222 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
6223 if (ldrOpc == ARM::t2LDREX)
6225 AddDefaultPred(MIB);
6226 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
6227 .addReg(dest).addReg(oldval));
6228 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
6229 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
6230 BB->addSuccessor(loop2MBB);
6231 BB->addSuccessor(exitMBB);
6234 // strex scratch, newval, [ptr]
6238 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval).addReg(ptr);
6239 if (strOpc == ARM::t2STREX)
6241 AddDefaultPred(MIB);
6242 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
6243 .addReg(scratch).addImm(0));
6244 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
6245 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
6246 BB->addSuccessor(loop1MBB);
6247 BB->addSuccessor(exitMBB);
6253 MI->eraseFromParent(); // The instruction is gone now.
6259 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
6260 unsigned Size, unsigned BinOpcode) const {
6261 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6262 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6264 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6265 MachineFunction *MF = BB->getParent();
6266 MachineFunction::iterator It = BB;
6269 unsigned dest = MI->getOperand(0).getReg();
6270 unsigned ptr = MI->getOperand(1).getReg();
6271 unsigned incr = MI->getOperand(2).getReg();
6272 AtomicOrdering Ord = static_cast<AtomicOrdering>(MI->getOperand(3).getImm());
6273 DebugLoc dl = MI->getDebugLoc();
6274 bool isThumb2 = Subtarget->isThumb2();
6276 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
6278 MRI.constrainRegClass(dest, &ARM::rGPRRegClass);
6279 MRI.constrainRegClass(ptr, &ARM::rGPRRegClass);
6280 MRI.constrainRegClass(incr, &ARM::rGPRRegClass);
6283 unsigned ldrOpc, strOpc;
6284 getExclusiveOperation(Size, Ord, isThumb2, ldrOpc, strOpc);
6286 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
6287 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
6288 MF->insert(It, loopMBB);
6289 MF->insert(It, exitMBB);
6291 // Transfer the remainder of BB and its successor edges to exitMBB.
6292 exitMBB->splice(exitMBB->begin(), BB,
6293 llvm::next(MachineBasicBlock::iterator(MI)),
6295 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6297 const TargetRegisterClass *TRC = isThumb2 ?
6298 (const TargetRegisterClass*)&ARM::rGPRRegClass :
6299 (const TargetRegisterClass*)&ARM::GPRRegClass;
6300 unsigned scratch = MRI.createVirtualRegister(TRC);
6301 unsigned scratch2 = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC);
6305 // fallthrough --> loopMBB
6306 BB->addSuccessor(loopMBB);
6310 // <binop> scratch2, dest, incr
6311 // strex scratch, scratch2, ptr
6314 // fallthrough --> exitMBB
6316 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
6317 if (ldrOpc == ARM::t2LDREX)
6319 AddDefaultPred(MIB);
6321 // operand order needs to go the other way for NAND
6322 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
6323 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
6324 addReg(incr).addReg(dest)).addReg(0);
6326 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
6327 addReg(dest).addReg(incr)).addReg(0);
6330 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr);
6331 if (strOpc == ARM::t2STREX)
6333 AddDefaultPred(MIB);
6334 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
6335 .addReg(scratch).addImm(0));
6336 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
6337 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
6339 BB->addSuccessor(loopMBB);
6340 BB->addSuccessor(exitMBB);
6346 MI->eraseFromParent(); // The instruction is gone now.
6352 ARMTargetLowering::EmitAtomicBinaryMinMax(MachineInstr *MI,
6353 MachineBasicBlock *BB,
6356 ARMCC::CondCodes Cond) const {
6357 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6359 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6360 MachineFunction *MF = BB->getParent();
6361 MachineFunction::iterator It = BB;
6364 unsigned dest = MI->getOperand(0).getReg();
6365 unsigned ptr = MI->getOperand(1).getReg();
6366 unsigned incr = MI->getOperand(2).getReg();
6367 unsigned oldval = dest;
6368 AtomicOrdering Ord = static_cast<AtomicOrdering>(MI->getOperand(3).getImm());
6369 DebugLoc dl = MI->getDebugLoc();
6370 bool isThumb2 = Subtarget->isThumb2();
6372 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
6374 MRI.constrainRegClass(dest, &ARM::rGPRRegClass);
6375 MRI.constrainRegClass(ptr, &ARM::rGPRRegClass);
6376 MRI.constrainRegClass(incr, &ARM::rGPRRegClass);
6379 unsigned ldrOpc, strOpc, extendOpc;
6380 getExclusiveOperation(Size, Ord, isThumb2, ldrOpc, strOpc);
6382 default: llvm_unreachable("unsupported size for AtomicBinaryMinMax!");
6384 extendOpc = isThumb2 ? ARM::t2SXTB : ARM::SXTB;
6387 extendOpc = isThumb2 ? ARM::t2SXTH : ARM::SXTH;
6394 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
6395 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
6396 MF->insert(It, loopMBB);
6397 MF->insert(It, exitMBB);
6399 // Transfer the remainder of BB and its successor edges to exitMBB.
6400 exitMBB->splice(exitMBB->begin(), BB,
6401 llvm::next(MachineBasicBlock::iterator(MI)),
6403 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6405 const TargetRegisterClass *TRC = isThumb2 ?
6406 (const TargetRegisterClass*)&ARM::rGPRRegClass :
6407 (const TargetRegisterClass*)&ARM::GPRRegClass;
6408 unsigned scratch = MRI.createVirtualRegister(TRC);
6409 unsigned scratch2 = MRI.createVirtualRegister(TRC);
6413 // fallthrough --> loopMBB
6414 BB->addSuccessor(loopMBB);
6418 // (sign extend dest, if required)
6420 // cmov.cond scratch2, incr, dest
6421 // strex scratch, scratch2, ptr
6424 // fallthrough --> exitMBB
6426 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
6427 if (ldrOpc == ARM::t2LDREX)
6429 AddDefaultPred(MIB);
6431 // Sign extend the value, if necessary.
6432 if (signExtend && extendOpc) {
6433 oldval = MRI.createVirtualRegister(isThumb2 ? &ARM::rGPRRegClass
6434 : &ARM::GPRnopcRegClass);
6436 MRI.constrainRegClass(dest, &ARM::GPRnopcRegClass);
6437 AddDefaultPred(BuildMI(BB, dl, TII->get(extendOpc), oldval)
6442 // Build compare and cmov instructions.
6443 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
6444 .addReg(oldval).addReg(incr));
6445 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr), scratch2)
6446 .addReg(incr).addReg(oldval).addImm(Cond).addReg(ARM::CPSR);
6448 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr);
6449 if (strOpc == ARM::t2STREX)
6451 AddDefaultPred(MIB);
6452 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
6453 .addReg(scratch).addImm(0));
6454 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
6455 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
6457 BB->addSuccessor(loopMBB);
6458 BB->addSuccessor(exitMBB);
6464 MI->eraseFromParent(); // The instruction is gone now.
6470 ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB,
6471 unsigned Op1, unsigned Op2,
6472 bool NeedsCarry, bool IsCmpxchg,
6473 bool IsMinMax, ARMCC::CondCodes CC) const {
6474 // This also handles ATOMIC_SWAP and ATOMIC_STORE, indicated by Op1==0.
6475 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6477 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6478 MachineFunction *MF = BB->getParent();
6479 MachineFunction::iterator It = BB;
6482 bool isStore = (MI->getOpcode() == ARM::ATOMIC_STORE_I64);
6483 unsigned offset = (isStore ? -2 : 0);
6484 unsigned destlo = MI->getOperand(0).getReg();
6485 unsigned desthi = MI->getOperand(1).getReg();
6486 unsigned ptr = MI->getOperand(offset+2).getReg();
6487 unsigned vallo = MI->getOperand(offset+3).getReg();
6488 unsigned valhi = MI->getOperand(offset+4).getReg();
6489 unsigned OrdIdx = offset + (IsCmpxchg ? 7 : 5);
6490 AtomicOrdering Ord = static_cast<AtomicOrdering>(MI->getOperand(OrdIdx).getImm());
6491 DebugLoc dl = MI->getDebugLoc();
6492 bool isThumb2 = Subtarget->isThumb2();
6494 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
6496 MRI.constrainRegClass(destlo, &ARM::rGPRRegClass);
6497 MRI.constrainRegClass(desthi, &ARM::rGPRRegClass);
6498 MRI.constrainRegClass(ptr, &ARM::rGPRRegClass);
6499 MRI.constrainRegClass(vallo, &ARM::rGPRRegClass);
6500 MRI.constrainRegClass(valhi, &ARM::rGPRRegClass);
6503 unsigned ldrOpc, strOpc;
6504 getExclusiveOperation(8, Ord, isThumb2, ldrOpc, strOpc);
6506 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
6507 MachineBasicBlock *contBB = 0, *cont2BB = 0;
6508 if (IsCmpxchg || IsMinMax)
6509 contBB = MF->CreateMachineBasicBlock(LLVM_BB);
6511 cont2BB = MF->CreateMachineBasicBlock(LLVM_BB);
6512 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
6514 MF->insert(It, loopMBB);
6515 if (IsCmpxchg || IsMinMax) MF->insert(It, contBB);
6516 if (IsCmpxchg) MF->insert(It, cont2BB);
6517 MF->insert(It, exitMBB);
6519 // Transfer the remainder of BB and its successor edges to exitMBB.
6520 exitMBB->splice(exitMBB->begin(), BB,
6521 llvm::next(MachineBasicBlock::iterator(MI)),
6523 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6525 const TargetRegisterClass *TRC = isThumb2 ?
6526 (const TargetRegisterClass*)&ARM::tGPRRegClass :
6527 (const TargetRegisterClass*)&ARM::GPRRegClass;
6528 unsigned storesuccess = MRI.createVirtualRegister(TRC);
6532 // fallthrough --> loopMBB
6533 BB->addSuccessor(loopMBB);
6536 // ldrexd r2, r3, ptr
6537 // <binopa> r0, r2, incr
6538 // <binopb> r1, r3, incr
6539 // strexd storesuccess, r0, r1, ptr
6540 // cmp storesuccess, #0
6542 // fallthrough --> exitMBB
6548 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc))
6549 .addReg(destlo, RegState::Define)
6550 .addReg(desthi, RegState::Define)
6553 unsigned GPRPair0 = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
6554 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc))
6555 .addReg(GPRPair0, RegState::Define).addReg(ptr));
6556 // Copy r2/r3 into dest. (This copy will normally be coalesced.)
6557 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), destlo)
6558 .addReg(GPRPair0, 0, ARM::gsub_0);
6559 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), desthi)
6560 .addReg(GPRPair0, 0, ARM::gsub_1);
6564 unsigned StoreLo, StoreHi;
6567 for (unsigned i = 0; i < 2; i++) {
6568 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr :
6570 .addReg(i == 0 ? destlo : desthi)
6571 .addReg(i == 0 ? vallo : valhi));
6572 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
6573 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
6574 BB->addSuccessor(exitMBB);
6575 BB->addSuccessor(i == 0 ? contBB : cont2BB);
6576 BB = (i == 0 ? contBB : cont2BB);
6579 // Copy to physregs for strexd
6580 StoreLo = MI->getOperand(5).getReg();
6581 StoreHi = MI->getOperand(6).getReg();
6583 // Perform binary operation
6584 unsigned tmpRegLo = MRI.createVirtualRegister(TRC);
6585 AddDefaultPred(BuildMI(BB, dl, TII->get(Op1), tmpRegLo)
6586 .addReg(destlo).addReg(vallo))
6587 .addReg(NeedsCarry ? ARM::CPSR : 0, getDefRegState(NeedsCarry));
6588 unsigned tmpRegHi = MRI.createVirtualRegister(TRC);
6589 AddDefaultPred(BuildMI(BB, dl, TII->get(Op2), tmpRegHi)
6590 .addReg(desthi).addReg(valhi))
6591 .addReg(IsMinMax ? ARM::CPSR : 0, getDefRegState(IsMinMax));
6596 // Copy to physregs for strexd
6601 // Compare and branch to exit block.
6602 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
6603 .addMBB(exitMBB).addImm(CC).addReg(ARM::CPSR);
6604 BB->addSuccessor(exitMBB);
6605 BB->addSuccessor(contBB);
6613 MRI.constrainRegClass(StoreLo, &ARM::rGPRRegClass);
6614 MRI.constrainRegClass(StoreHi, &ARM::rGPRRegClass);
6615 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), storesuccess)
6616 .addReg(StoreLo).addReg(StoreHi).addReg(ptr));
6618 // Marshal a pair...
6619 unsigned StorePair = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
6620 unsigned UndefPair = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
6621 unsigned r1 = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
6622 BuildMI(BB, dl, TII->get(TargetOpcode::IMPLICIT_DEF), UndefPair);
6623 BuildMI(BB, dl, TII->get(TargetOpcode::INSERT_SUBREG), r1)
6626 .addImm(ARM::gsub_0);
6627 BuildMI(BB, dl, TII->get(TargetOpcode::INSERT_SUBREG), StorePair)
6630 .addImm(ARM::gsub_1);
6633 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), storesuccess)
6634 .addReg(StorePair).addReg(ptr));
6637 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
6638 .addReg(storesuccess).addImm(0));
6639 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
6640 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
6642 BB->addSuccessor(loopMBB);
6643 BB->addSuccessor(exitMBB);
6649 MI->eraseFromParent(); // The instruction is gone now.
6655 ARMTargetLowering::EmitAtomicLoad64(MachineInstr *MI, MachineBasicBlock *BB) const {
6657 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6659 unsigned destlo = MI->getOperand(0).getReg();
6660 unsigned desthi = MI->getOperand(1).getReg();
6661 unsigned ptr = MI->getOperand(2).getReg();
6662 AtomicOrdering Ord = static_cast<AtomicOrdering>(MI->getOperand(3).getImm());
6663 DebugLoc dl = MI->getDebugLoc();
6664 bool isThumb2 = Subtarget->isThumb2();
6666 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
6668 MRI.constrainRegClass(destlo, &ARM::rGPRRegClass);
6669 MRI.constrainRegClass(desthi, &ARM::rGPRRegClass);
6670 MRI.constrainRegClass(ptr, &ARM::rGPRRegClass);
6672 unsigned ldrOpc, strOpc;
6673 getExclusiveOperation(8, Ord, isThumb2, ldrOpc, strOpc);
6675 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(ldrOpc));
6678 MIB.addReg(destlo, RegState::Define)
6679 .addReg(desthi, RegState::Define)
6683 unsigned GPRPair0 = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
6684 MIB.addReg(GPRPair0, RegState::Define).addReg(ptr);
6686 // Copy GPRPair0 into dest. (This copy will normally be coalesced.)
6687 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), destlo)
6688 .addReg(GPRPair0, 0, ARM::gsub_0);
6689 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), desthi)
6690 .addReg(GPRPair0, 0, ARM::gsub_1);
6692 AddDefaultPred(MIB);
6694 MI->eraseFromParent(); // The instruction is gone now.
6699 /// SetupEntryBlockForSjLj - Insert code into the entry block that creates and
6700 /// registers the function context.
6701 void ARMTargetLowering::
6702 SetupEntryBlockForSjLj(MachineInstr *MI, MachineBasicBlock *MBB,
6703 MachineBasicBlock *DispatchBB, int FI) const {
6704 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6705 DebugLoc dl = MI->getDebugLoc();
6706 MachineFunction *MF = MBB->getParent();
6707 MachineRegisterInfo *MRI = &MF->getRegInfo();
6708 MachineConstantPool *MCP = MF->getConstantPool();
6709 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
6710 const Function *F = MF->getFunction();
6712 bool isThumb = Subtarget->isThumb();
6713 bool isThumb2 = Subtarget->isThumb2();
6715 unsigned PCLabelId = AFI->createPICLabelUId();
6716 unsigned PCAdj = (isThumb || isThumb2) ? 4 : 8;
6717 ARMConstantPoolValue *CPV =
6718 ARMConstantPoolMBB::Create(F->getContext(), DispatchBB, PCLabelId, PCAdj);
6719 unsigned CPI = MCP->getConstantPoolIndex(CPV, 4);
6721 const TargetRegisterClass *TRC = isThumb ?
6722 (const TargetRegisterClass*)&ARM::tGPRRegClass :
6723 (const TargetRegisterClass*)&ARM::GPRRegClass;
6725 // Grab constant pool and fixed stack memory operands.
6726 MachineMemOperand *CPMMO =
6727 MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(),
6728 MachineMemOperand::MOLoad, 4, 4);
6730 MachineMemOperand *FIMMOSt =
6731 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
6732 MachineMemOperand::MOStore, 4, 4);
6734 // Load the address of the dispatch MBB into the jump buffer.
6736 // Incoming value: jbuf
6737 // ldr.n r5, LCPI1_1
6740 // str r5, [$jbuf, #+4] ; &jbuf[1]
6741 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6742 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1)
6743 .addConstantPoolIndex(CPI)
6744 .addMemOperand(CPMMO));
6745 // Set the low bit because of thumb mode.
6746 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6748 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2)
6749 .addReg(NewVReg1, RegState::Kill)
6751 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6752 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3)
6753 .addReg(NewVReg2, RegState::Kill)
6755 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12))
6756 .addReg(NewVReg3, RegState::Kill)
6758 .addImm(36) // &jbuf[1] :: pc
6759 .addMemOperand(FIMMOSt));
6760 } else if (isThumb) {
6761 // Incoming value: jbuf
6762 // ldr.n r1, LCPI1_4
6766 // add r2, $jbuf, #+4 ; &jbuf[1]
6768 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6769 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1)
6770 .addConstantPoolIndex(CPI)
6771 .addMemOperand(CPMMO));
6772 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6773 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2)
6774 .addReg(NewVReg1, RegState::Kill)
6776 // Set the low bit because of thumb mode.
6777 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6778 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3)
6779 .addReg(ARM::CPSR, RegState::Define)
6781 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6782 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4)
6783 .addReg(ARM::CPSR, RegState::Define)
6784 .addReg(NewVReg2, RegState::Kill)
6785 .addReg(NewVReg3, RegState::Kill));
6786 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
6787 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tADDrSPi), NewVReg5)
6789 .addImm(36)); // &jbuf[1] :: pc
6790 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi))
6791 .addReg(NewVReg4, RegState::Kill)
6792 .addReg(NewVReg5, RegState::Kill)
6794 .addMemOperand(FIMMOSt));
6796 // Incoming value: jbuf
6799 // str r1, [$jbuf, #+4] ; &jbuf[1]
6800 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6801 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1)
6802 .addConstantPoolIndex(CPI)
6804 .addMemOperand(CPMMO));
6805 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6806 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2)
6807 .addReg(NewVReg1, RegState::Kill)
6808 .addImm(PCLabelId));
6809 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12))
6810 .addReg(NewVReg2, RegState::Kill)
6812 .addImm(36) // &jbuf[1] :: pc
6813 .addMemOperand(FIMMOSt));
6817 MachineBasicBlock *ARMTargetLowering::
6818 EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
6819 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6820 DebugLoc dl = MI->getDebugLoc();
6821 MachineFunction *MF = MBB->getParent();
6822 MachineRegisterInfo *MRI = &MF->getRegInfo();
6823 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
6824 MachineFrameInfo *MFI = MF->getFrameInfo();
6825 int FI = MFI->getFunctionContextIndex();
6827 const TargetRegisterClass *TRC = Subtarget->isThumb() ?
6828 (const TargetRegisterClass*)&ARM::tGPRRegClass :
6829 (const TargetRegisterClass*)&ARM::GPRnopcRegClass;
6831 // Get a mapping of the call site numbers to all of the landing pads they're
6833 DenseMap<unsigned, SmallVector<MachineBasicBlock*, 2> > CallSiteNumToLPad;
6834 unsigned MaxCSNum = 0;
6835 MachineModuleInfo &MMI = MF->getMMI();
6836 for (MachineFunction::iterator BB = MF->begin(), E = MF->end(); BB != E;
6838 if (!BB->isLandingPad()) continue;
6840 // FIXME: We should assert that the EH_LABEL is the first MI in the landing
6842 for (MachineBasicBlock::iterator
6843 II = BB->begin(), IE = BB->end(); II != IE; ++II) {
6844 if (!II->isEHLabel()) continue;
6846 MCSymbol *Sym = II->getOperand(0).getMCSymbol();
6847 if (!MMI.hasCallSiteLandingPad(Sym)) continue;
6849 SmallVectorImpl<unsigned> &CallSiteIdxs = MMI.getCallSiteLandingPad(Sym);
6850 for (SmallVectorImpl<unsigned>::iterator
6851 CSI = CallSiteIdxs.begin(), CSE = CallSiteIdxs.end();
6852 CSI != CSE; ++CSI) {
6853 CallSiteNumToLPad[*CSI].push_back(BB);
6854 MaxCSNum = std::max(MaxCSNum, *CSI);
6860 // Get an ordered list of the machine basic blocks for the jump table.
6861 std::vector<MachineBasicBlock*> LPadList;
6862 SmallPtrSet<MachineBasicBlock*, 64> InvokeBBs;
6863 LPadList.reserve(CallSiteNumToLPad.size());
6864 for (unsigned I = 1; I <= MaxCSNum; ++I) {
6865 SmallVectorImpl<MachineBasicBlock*> &MBBList = CallSiteNumToLPad[I];
6866 for (SmallVectorImpl<MachineBasicBlock*>::iterator
6867 II = MBBList.begin(), IE = MBBList.end(); II != IE; ++II) {
6868 LPadList.push_back(*II);
6869 InvokeBBs.insert((*II)->pred_begin(), (*II)->pred_end());
6873 assert(!LPadList.empty() &&
6874 "No landing pad destinations for the dispatch jump table!");
6876 // Create the jump table and associated information.
6877 MachineJumpTableInfo *JTI =
6878 MF->getOrCreateJumpTableInfo(MachineJumpTableInfo::EK_Inline);
6879 unsigned MJTI = JTI->createJumpTableIndex(LPadList);
6880 unsigned UId = AFI->createJumpTableUId();
6881 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
6883 // Create the MBBs for the dispatch code.
6885 // Shove the dispatch's address into the return slot in the function context.
6886 MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock();
6887 DispatchBB->setIsLandingPad();
6889 MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
6890 unsigned trap_opcode;
6891 if (Subtarget->isThumb())
6892 trap_opcode = ARM::tTRAP;
6894 trap_opcode = Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP;
6896 BuildMI(TrapBB, dl, TII->get(trap_opcode));
6897 DispatchBB->addSuccessor(TrapBB);
6899 MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock();
6900 DispatchBB->addSuccessor(DispContBB);
6903 MF->insert(MF->end(), DispatchBB);
6904 MF->insert(MF->end(), DispContBB);
6905 MF->insert(MF->end(), TrapBB);
6907 // Insert code into the entry block that creates and registers the function
6909 SetupEntryBlockForSjLj(MI, MBB, DispatchBB, FI);
6911 MachineMemOperand *FIMMOLd =
6912 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
6913 MachineMemOperand::MOLoad |
6914 MachineMemOperand::MOVolatile, 4, 4);
6916 MachineInstrBuilder MIB;
6917 MIB = BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup));
6919 const ARMBaseInstrInfo *AII = static_cast<const ARMBaseInstrInfo*>(TII);
6920 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
6922 // Add a register mask with no preserved registers. This results in all
6923 // registers being marked as clobbered.
6924 MIB.addRegMask(RI.getNoPreservedMask());
6926 unsigned NumLPads = LPadList.size();
6927 if (Subtarget->isThumb2()) {
6928 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6929 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1)
6932 .addMemOperand(FIMMOLd));
6934 if (NumLPads < 256) {
6935 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri))
6937 .addImm(LPadList.size()));
6939 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6940 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVi16), VReg1)
6941 .addImm(NumLPads & 0xFFFF));
6943 unsigned VReg2 = VReg1;
6944 if ((NumLPads & 0xFFFF0000) != 0) {
6945 VReg2 = MRI->createVirtualRegister(TRC);
6946 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVTi16), VReg2)
6948 .addImm(NumLPads >> 16));
6951 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPrr))
6956 BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc))
6961 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6962 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT),NewVReg3)
6963 .addJumpTableIndex(MJTI)
6966 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6969 BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg4)
6970 .addReg(NewVReg3, RegState::Kill)
6972 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
6974 BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT))
6975 .addReg(NewVReg4, RegState::Kill)
6977 .addJumpTableIndex(MJTI)
6979 } else if (Subtarget->isThumb()) {
6980 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6981 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1)
6984 .addMemOperand(FIMMOLd));
6986 if (NumLPads < 256) {
6987 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPi8))
6991 MachineConstantPool *ConstantPool = MF->getConstantPool();
6992 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
6993 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
6995 // MachineConstantPool wants an explicit alignment.
6996 unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
6998 Align = getDataLayout()->getTypeAllocSize(C->getType());
6999 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
7001 unsigned VReg1 = MRI->createVirtualRegister(TRC);
7002 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRpci))
7003 .addReg(VReg1, RegState::Define)
7004 .addConstantPoolIndex(Idx));
7005 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPr))
7010 BuildMI(DispatchBB, dl, TII->get(ARM::tBcc))
7015 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
7016 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLSLri), NewVReg2)
7017 .addReg(ARM::CPSR, RegState::Define)
7021 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
7022 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLEApcrelJT), NewVReg3)
7023 .addJumpTableIndex(MJTI)
7026 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
7027 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg4)
7028 .addReg(ARM::CPSR, RegState::Define)
7029 .addReg(NewVReg2, RegState::Kill)
7032 MachineMemOperand *JTMMOLd =
7033 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(),
7034 MachineMemOperand::MOLoad, 4, 4);
7036 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
7037 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLDRi), NewVReg5)
7038 .addReg(NewVReg4, RegState::Kill)
7040 .addMemOperand(JTMMOLd));
7042 unsigned NewVReg6 = NewVReg5;
7043 if (RelocM == Reloc::PIC_) {
7044 NewVReg6 = MRI->createVirtualRegister(TRC);
7045 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6)
7046 .addReg(ARM::CPSR, RegState::Define)
7047 .addReg(NewVReg5, RegState::Kill)
7051 BuildMI(DispContBB, dl, TII->get(ARM::tBR_JTr))
7052 .addReg(NewVReg6, RegState::Kill)
7053 .addJumpTableIndex(MJTI)
7056 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
7057 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1)
7060 .addMemOperand(FIMMOLd));
7062 if (NumLPads < 256) {
7063 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPri))
7066 } else if (Subtarget->hasV6T2Ops() && isUInt<16>(NumLPads)) {
7067 unsigned VReg1 = MRI->createVirtualRegister(TRC);
7068 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1)
7069 .addImm(NumLPads & 0xFFFF));
7071 unsigned VReg2 = VReg1;
7072 if ((NumLPads & 0xFFFF0000) != 0) {
7073 VReg2 = MRI->createVirtualRegister(TRC);
7074 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVTi16), VReg2)
7076 .addImm(NumLPads >> 16));
7079 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
7083 MachineConstantPool *ConstantPool = MF->getConstantPool();
7084 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
7085 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
7087 // MachineConstantPool wants an explicit alignment.
7088 unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
7090 Align = getDataLayout()->getTypeAllocSize(C->getType());
7091 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
7093 unsigned VReg1 = MRI->createVirtualRegister(TRC);
7094 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRcp))
7095 .addReg(VReg1, RegState::Define)
7096 .addConstantPoolIndex(Idx)
7098 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
7100 .addReg(VReg1, RegState::Kill));
7103 BuildMI(DispatchBB, dl, TII->get(ARM::Bcc))
7108 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
7110 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg3)
7112 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
7113 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
7114 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg4)
7115 .addJumpTableIndex(MJTI)
7118 MachineMemOperand *JTMMOLd =
7119 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(),
7120 MachineMemOperand::MOLoad, 4, 4);
7121 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
7123 BuildMI(DispContBB, dl, TII->get(ARM::LDRrs), NewVReg5)
7124 .addReg(NewVReg3, RegState::Kill)
7127 .addMemOperand(JTMMOLd));
7129 if (RelocM == Reloc::PIC_) {
7130 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTadd))
7131 .addReg(NewVReg5, RegState::Kill)
7133 .addJumpTableIndex(MJTI)
7136 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTr))
7137 .addReg(NewVReg5, RegState::Kill)
7138 .addJumpTableIndex(MJTI)
7143 // Add the jump table entries as successors to the MBB.
7144 SmallPtrSet<MachineBasicBlock*, 8> SeenMBBs;
7145 for (std::vector<MachineBasicBlock*>::iterator
7146 I = LPadList.begin(), E = LPadList.end(); I != E; ++I) {
7147 MachineBasicBlock *CurMBB = *I;
7148 if (SeenMBBs.insert(CurMBB))
7149 DispContBB->addSuccessor(CurMBB);
7152 // N.B. the order the invoke BBs are processed in doesn't matter here.
7153 const uint16_t *SavedRegs = RI.getCalleeSavedRegs(MF);
7154 SmallVector<MachineBasicBlock*, 64> MBBLPads;
7155 for (SmallPtrSet<MachineBasicBlock*, 64>::iterator
7156 I = InvokeBBs.begin(), E = InvokeBBs.end(); I != E; ++I) {
7157 MachineBasicBlock *BB = *I;
7159 // Remove the landing pad successor from the invoke block and replace it
7160 // with the new dispatch block.
7161 SmallVector<MachineBasicBlock*, 4> Successors(BB->succ_begin(),
7163 while (!Successors.empty()) {
7164 MachineBasicBlock *SMBB = Successors.pop_back_val();
7165 if (SMBB->isLandingPad()) {
7166 BB->removeSuccessor(SMBB);
7167 MBBLPads.push_back(SMBB);
7171 BB->addSuccessor(DispatchBB);
7173 // Find the invoke call and mark all of the callee-saved registers as
7174 // 'implicit defined' so that they're spilled. This prevents code from
7175 // moving instructions to before the EH block, where they will never be
7177 for (MachineBasicBlock::reverse_iterator
7178 II = BB->rbegin(), IE = BB->rend(); II != IE; ++II) {
7179 if (!II->isCall()) continue;
7181 DenseMap<unsigned, bool> DefRegs;
7182 for (MachineInstr::mop_iterator
7183 OI = II->operands_begin(), OE = II->operands_end();
7185 if (!OI->isReg()) continue;
7186 DefRegs[OI->getReg()] = true;
7189 MachineInstrBuilder MIB(*MF, &*II);
7191 for (unsigned i = 0; SavedRegs[i] != 0; ++i) {
7192 unsigned Reg = SavedRegs[i];
7193 if (Subtarget->isThumb2() &&
7194 !ARM::tGPRRegClass.contains(Reg) &&
7195 !ARM::hGPRRegClass.contains(Reg))
7197 if (Subtarget->isThumb1Only() && !ARM::tGPRRegClass.contains(Reg))
7199 if (!Subtarget->isThumb() && !ARM::GPRRegClass.contains(Reg))
7202 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead);
7209 // Mark all former landing pads as non-landing pads. The dispatch is the only
7211 for (SmallVectorImpl<MachineBasicBlock*>::iterator
7212 I = MBBLPads.begin(), E = MBBLPads.end(); I != E; ++I)
7213 (*I)->setIsLandingPad(false);
7215 // The instruction is gone now.
7216 MI->eraseFromParent();
7222 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
7223 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
7224 E = MBB->succ_end(); I != E; ++I)
7227 llvm_unreachable("Expecting a BB with two successors!");
7230 /// Return the load opcode for a given load size. If load size >= 8,
7231 /// neon opcode will be returned.
7232 static unsigned getLdOpcode(unsigned LdSize, bool IsThumb1, bool IsThumb2) {
7234 return LdSize == 16 ? ARM::VLD1q32wb_fixed
7235 : LdSize == 8 ? ARM::VLD1d32wb_fixed : 0;
7237 return LdSize == 4 ? ARM::tLDRi
7238 : LdSize == 2 ? ARM::tLDRHi
7239 : LdSize == 1 ? ARM::tLDRBi : 0;
7241 return LdSize == 4 ? ARM::t2LDR_POST
7242 : LdSize == 2 ? ARM::t2LDRH_POST
7243 : LdSize == 1 ? ARM::t2LDRB_POST : 0;
7244 return LdSize == 4 ? ARM::LDR_POST_IMM
7245 : LdSize == 2 ? ARM::LDRH_POST
7246 : LdSize == 1 ? ARM::LDRB_POST_IMM : 0;
7249 /// Return the store opcode for a given store size. If store size >= 8,
7250 /// neon opcode will be returned.
7251 static unsigned getStOpcode(unsigned StSize, bool IsThumb1, bool IsThumb2) {
7253 return StSize == 16 ? ARM::VST1q32wb_fixed
7254 : StSize == 8 ? ARM::VST1d32wb_fixed : 0;
7256 return StSize == 4 ? ARM::tSTRi
7257 : StSize == 2 ? ARM::tSTRHi
7258 : StSize == 1 ? ARM::tSTRBi : 0;
7260 return StSize == 4 ? ARM::t2STR_POST
7261 : StSize == 2 ? ARM::t2STRH_POST
7262 : StSize == 1 ? ARM::t2STRB_POST : 0;
7263 return StSize == 4 ? ARM::STR_POST_IMM
7264 : StSize == 2 ? ARM::STRH_POST
7265 : StSize == 1 ? ARM::STRB_POST_IMM : 0;
7268 /// Emit a post-increment load operation with given size. The instructions
7269 /// will be added to BB at Pos.
7270 static void emitPostLd(MachineBasicBlock *BB, MachineInstr *Pos,
7271 const TargetInstrInfo *TII, DebugLoc dl,
7272 unsigned LdSize, unsigned Data, unsigned AddrIn,
7273 unsigned AddrOut, bool IsThumb1, bool IsThumb2) {
7274 unsigned LdOpc = getLdOpcode(LdSize, IsThumb1, IsThumb2);
7275 assert(LdOpc != 0 && "Should have a load opcode");
7277 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7278 .addReg(AddrOut, RegState::Define).addReg(AddrIn)
7280 } else if (IsThumb1) {
7281 // load + update AddrIn
7282 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7283 .addReg(AddrIn).addImm(0));
7284 MachineInstrBuilder MIB =
7285 BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut);
7286 MIB = AddDefaultT1CC(MIB);
7287 MIB.addReg(AddrIn).addImm(LdSize);
7288 AddDefaultPred(MIB);
7289 } else if (IsThumb2) {
7290 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7291 .addReg(AddrOut, RegState::Define).addReg(AddrIn)
7294 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7295 .addReg(AddrOut, RegState::Define).addReg(AddrIn)
7296 .addReg(0).addImm(LdSize));
7300 /// Emit a post-increment store operation with given size. The instructions
7301 /// will be added to BB at Pos.
7302 static void emitPostSt(MachineBasicBlock *BB, MachineInstr *Pos,
7303 const TargetInstrInfo *TII, DebugLoc dl,
7304 unsigned StSize, unsigned Data, unsigned AddrIn,
7305 unsigned AddrOut, bool IsThumb1, bool IsThumb2) {
7306 unsigned StOpc = getStOpcode(StSize, IsThumb1, IsThumb2);
7307 assert(StOpc != 0 && "Should have a store opcode");
7309 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
7310 .addReg(AddrIn).addImm(0).addReg(Data));
7311 } else if (IsThumb1) {
7312 // store + update AddrIn
7313 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc)).addReg(Data)
7314 .addReg(AddrIn).addImm(0));
7315 MachineInstrBuilder MIB =
7316 BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut);
7317 MIB = AddDefaultT1CC(MIB);
7318 MIB.addReg(AddrIn).addImm(StSize);
7319 AddDefaultPred(MIB);
7320 } else if (IsThumb2) {
7321 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
7322 .addReg(Data).addReg(AddrIn).addImm(StSize));
7324 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
7325 .addReg(Data).addReg(AddrIn).addReg(0)
7331 ARMTargetLowering::EmitStructByval(MachineInstr *MI,
7332 MachineBasicBlock *BB) const {
7333 // This pseudo instruction has 3 operands: dst, src, size
7334 // We expand it to a loop if size > Subtarget->getMaxInlineSizeThreshold().
7335 // Otherwise, we will generate unrolled scalar copies.
7336 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7337 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7338 MachineFunction::iterator It = BB;
7341 unsigned dest = MI->getOperand(0).getReg();
7342 unsigned src = MI->getOperand(1).getReg();
7343 unsigned SizeVal = MI->getOperand(2).getImm();
7344 unsigned Align = MI->getOperand(3).getImm();
7345 DebugLoc dl = MI->getDebugLoc();
7347 MachineFunction *MF = BB->getParent();
7348 MachineRegisterInfo &MRI = MF->getRegInfo();
7349 unsigned UnitSize = 0;
7350 const TargetRegisterClass *TRC = 0;
7351 const TargetRegisterClass *VecTRC = 0;
7353 bool IsThumb1 = Subtarget->isThumb1Only();
7354 bool IsThumb2 = Subtarget->isThumb2();
7358 } else if (Align & 2) {
7361 // Check whether we can use NEON instructions.
7362 if (!MF->getFunction()->getAttributes().
7363 hasAttribute(AttributeSet::FunctionIndex,
7364 Attribute::NoImplicitFloat) &&
7365 Subtarget->hasNEON()) {
7366 if ((Align % 16 == 0) && SizeVal >= 16)
7368 else if ((Align % 8 == 0) && SizeVal >= 8)
7371 // Can't use NEON instructions.
7376 // Select the correct opcode and register class for unit size load/store
7377 bool IsNeon = UnitSize >= 8;
7378 TRC = (IsThumb1 || IsThumb2) ? (const TargetRegisterClass *)&ARM::tGPRRegClass
7379 : (const TargetRegisterClass *)&ARM::GPRRegClass;
7381 VecTRC = UnitSize == 16
7382 ? (const TargetRegisterClass *)&ARM::DPairRegClass
7384 ? (const TargetRegisterClass *)&ARM::DPRRegClass
7387 unsigned BytesLeft = SizeVal % UnitSize;
7388 unsigned LoopSize = SizeVal - BytesLeft;
7390 if (SizeVal <= Subtarget->getMaxInlineSizeThreshold()) {
7391 // Use LDR and STR to copy.
7392 // [scratch, srcOut] = LDR_POST(srcIn, UnitSize)
7393 // [destOut] = STR_POST(scratch, destIn, UnitSize)
7394 unsigned srcIn = src;
7395 unsigned destIn = dest;
7396 for (unsigned i = 0; i < LoopSize; i+=UnitSize) {
7397 unsigned srcOut = MRI.createVirtualRegister(TRC);
7398 unsigned destOut = MRI.createVirtualRegister(TRC);
7399 unsigned scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
7400 emitPostLd(BB, MI, TII, dl, UnitSize, scratch, srcIn, srcOut,
7401 IsThumb1, IsThumb2);
7402 emitPostSt(BB, MI, TII, dl, UnitSize, scratch, destIn, destOut,
7403 IsThumb1, IsThumb2);
7408 // Handle the leftover bytes with LDRB and STRB.
7409 // [scratch, srcOut] = LDRB_POST(srcIn, 1)
7410 // [destOut] = STRB_POST(scratch, destIn, 1)
7411 for (unsigned i = 0; i < BytesLeft; i++) {
7412 unsigned srcOut = MRI.createVirtualRegister(TRC);
7413 unsigned destOut = MRI.createVirtualRegister(TRC);
7414 unsigned scratch = MRI.createVirtualRegister(TRC);
7415 emitPostLd(BB, MI, TII, dl, 1, scratch, srcIn, srcOut,
7416 IsThumb1, IsThumb2);
7417 emitPostSt(BB, MI, TII, dl, 1, scratch, destIn, destOut,
7418 IsThumb1, IsThumb2);
7422 MI->eraseFromParent(); // The instruction is gone now.
7426 // Expand the pseudo op to a loop.
7429 // movw varEnd, # --> with thumb2
7431 // ldrcp varEnd, idx --> without thumb2
7432 // fallthrough --> loopMBB
7434 // PHI varPhi, varEnd, varLoop
7435 // PHI srcPhi, src, srcLoop
7436 // PHI destPhi, dst, destLoop
7437 // [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
7438 // [destLoop] = STR_POST(scratch, destPhi, UnitSize)
7439 // subs varLoop, varPhi, #UnitSize
7441 // fallthrough --> exitMBB
7443 // epilogue to handle left-over bytes
7444 // [scratch, srcOut] = LDRB_POST(srcLoop, 1)
7445 // [destOut] = STRB_POST(scratch, destLoop, 1)
7446 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
7447 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
7448 MF->insert(It, loopMBB);
7449 MF->insert(It, exitMBB);
7451 // Transfer the remainder of BB and its successor edges to exitMBB.
7452 exitMBB->splice(exitMBB->begin(), BB,
7453 llvm::next(MachineBasicBlock::iterator(MI)),
7455 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7457 // Load an immediate to varEnd.
7458 unsigned varEnd = MRI.createVirtualRegister(TRC);
7460 unsigned Vtmp = varEnd;
7461 if ((LoopSize & 0xFFFF0000) != 0)
7462 Vtmp = MRI.createVirtualRegister(TRC);
7463 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVi16), Vtmp)
7464 .addImm(LoopSize & 0xFFFF));
7466 if ((LoopSize & 0xFFFF0000) != 0)
7467 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVTi16), varEnd)
7468 .addReg(Vtmp).addImm(LoopSize >> 16));
7470 MachineConstantPool *ConstantPool = MF->getConstantPool();
7471 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
7472 const Constant *C = ConstantInt::get(Int32Ty, LoopSize);
7474 // MachineConstantPool wants an explicit alignment.
7475 unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
7477 Align = getDataLayout()->getTypeAllocSize(C->getType());
7478 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
7481 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(ARM::tLDRpci)).addReg(
7482 varEnd, RegState::Define).addConstantPoolIndex(Idx));
7484 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(ARM::LDRcp)).addReg(
7485 varEnd, RegState::Define).addConstantPoolIndex(Idx).addImm(0));
7487 BB->addSuccessor(loopMBB);
7489 // Generate the loop body:
7490 // varPhi = PHI(varLoop, varEnd)
7491 // srcPhi = PHI(srcLoop, src)
7492 // destPhi = PHI(destLoop, dst)
7493 MachineBasicBlock *entryBB = BB;
7495 unsigned varLoop = MRI.createVirtualRegister(TRC);
7496 unsigned varPhi = MRI.createVirtualRegister(TRC);
7497 unsigned srcLoop = MRI.createVirtualRegister(TRC);
7498 unsigned srcPhi = MRI.createVirtualRegister(TRC);
7499 unsigned destLoop = MRI.createVirtualRegister(TRC);
7500 unsigned destPhi = MRI.createVirtualRegister(TRC);
7502 BuildMI(*BB, BB->begin(), dl, TII->get(ARM::PHI), varPhi)
7503 .addReg(varLoop).addMBB(loopMBB)
7504 .addReg(varEnd).addMBB(entryBB);
7505 BuildMI(BB, dl, TII->get(ARM::PHI), srcPhi)
7506 .addReg(srcLoop).addMBB(loopMBB)
7507 .addReg(src).addMBB(entryBB);
7508 BuildMI(BB, dl, TII->get(ARM::PHI), destPhi)
7509 .addReg(destLoop).addMBB(loopMBB)
7510 .addReg(dest).addMBB(entryBB);
7512 // [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
7513 // [destLoop] = STR_POST(scratch, destPhi, UnitSiz)
7514 unsigned scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
7515 emitPostLd(BB, BB->end(), TII, dl, UnitSize, scratch, srcPhi, srcLoop,
7516 IsThumb1, IsThumb2);
7517 emitPostSt(BB, BB->end(), TII, dl, UnitSize, scratch, destPhi, destLoop,
7518 IsThumb1, IsThumb2);
7520 // Decrement loop variable by UnitSize.
7522 MachineInstrBuilder MIB =
7523 BuildMI(*BB, BB->end(), dl, TII->get(ARM::tSUBi8), varLoop);
7524 MIB = AddDefaultT1CC(MIB);
7525 MIB.addReg(varPhi).addImm(UnitSize);
7526 AddDefaultPred(MIB);
7528 MachineInstrBuilder MIB =
7529 BuildMI(*BB, BB->end(), dl,
7530 TII->get(IsThumb2 ? ARM::t2SUBri : ARM::SUBri), varLoop);
7531 AddDefaultCC(AddDefaultPred(MIB.addReg(varPhi).addImm(UnitSize)));
7532 MIB->getOperand(5).setReg(ARM::CPSR);
7533 MIB->getOperand(5).setIsDef(true);
7535 BuildMI(*BB, BB->end(), dl,
7536 TII->get(IsThumb1 ? ARM::tBcc : IsThumb2 ? ARM::t2Bcc : ARM::Bcc))
7537 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
7539 // loopMBB can loop back to loopMBB or fall through to exitMBB.
7540 BB->addSuccessor(loopMBB);
7541 BB->addSuccessor(exitMBB);
7543 // Add epilogue to handle BytesLeft.
7545 MachineInstr *StartOfExit = exitMBB->begin();
7547 // [scratch, srcOut] = LDRB_POST(srcLoop, 1)
7548 // [destOut] = STRB_POST(scratch, destLoop, 1)
7549 unsigned srcIn = srcLoop;
7550 unsigned destIn = destLoop;
7551 for (unsigned i = 0; i < BytesLeft; i++) {
7552 unsigned srcOut = MRI.createVirtualRegister(TRC);
7553 unsigned destOut = MRI.createVirtualRegister(TRC);
7554 unsigned scratch = MRI.createVirtualRegister(TRC);
7555 emitPostLd(BB, StartOfExit, TII, dl, 1, scratch, srcIn, srcOut,
7556 IsThumb1, IsThumb2);
7557 emitPostSt(BB, StartOfExit, TII, dl, 1, scratch, destIn, destOut,
7558 IsThumb1, IsThumb2);
7563 MI->eraseFromParent(); // The instruction is gone now.
7568 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7569 MachineBasicBlock *BB) const {
7570 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7571 DebugLoc dl = MI->getDebugLoc();
7572 bool isThumb2 = Subtarget->isThumb2();
7573 switch (MI->getOpcode()) {
7576 llvm_unreachable("Unexpected instr type to insert");
7578 // The Thumb2 pre-indexed stores have the same MI operands, they just
7579 // define them differently in the .td files from the isel patterns, so
7580 // they need pseudos.
7581 case ARM::t2STR_preidx:
7582 MI->setDesc(TII->get(ARM::t2STR_PRE));
7584 case ARM::t2STRB_preidx:
7585 MI->setDesc(TII->get(ARM::t2STRB_PRE));
7587 case ARM::t2STRH_preidx:
7588 MI->setDesc(TII->get(ARM::t2STRH_PRE));
7591 case ARM::STRi_preidx:
7592 case ARM::STRBi_preidx: {
7593 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ?
7594 ARM::STR_PRE_IMM : ARM::STRB_PRE_IMM;
7595 // Decode the offset.
7596 unsigned Offset = MI->getOperand(4).getImm();
7597 bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub;
7598 Offset = ARM_AM::getAM2Offset(Offset);
7602 MachineMemOperand *MMO = *MI->memoperands_begin();
7603 BuildMI(*BB, MI, dl, TII->get(NewOpc))
7604 .addOperand(MI->getOperand(0)) // Rn_wb
7605 .addOperand(MI->getOperand(1)) // Rt
7606 .addOperand(MI->getOperand(2)) // Rn
7607 .addImm(Offset) // offset (skip GPR==zero_reg)
7608 .addOperand(MI->getOperand(5)) // pred
7609 .addOperand(MI->getOperand(6))
7610 .addMemOperand(MMO);
7611 MI->eraseFromParent();
7614 case ARM::STRr_preidx:
7615 case ARM::STRBr_preidx:
7616 case ARM::STRH_preidx: {
7618 switch (MI->getOpcode()) {
7619 default: llvm_unreachable("unexpected opcode!");
7620 case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break;
7621 case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break;
7622 case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break;
7624 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
7625 for (unsigned i = 0; i < MI->getNumOperands(); ++i)
7626 MIB.addOperand(MI->getOperand(i));
7627 MI->eraseFromParent();
7630 case ARM::ATOMIC_LOAD_ADD_I8:
7631 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
7632 case ARM::ATOMIC_LOAD_ADD_I16:
7633 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
7634 case ARM::ATOMIC_LOAD_ADD_I32:
7635 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
7637 case ARM::ATOMIC_LOAD_AND_I8:
7638 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
7639 case ARM::ATOMIC_LOAD_AND_I16:
7640 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
7641 case ARM::ATOMIC_LOAD_AND_I32:
7642 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
7644 case ARM::ATOMIC_LOAD_OR_I8:
7645 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
7646 case ARM::ATOMIC_LOAD_OR_I16:
7647 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
7648 case ARM::ATOMIC_LOAD_OR_I32:
7649 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
7651 case ARM::ATOMIC_LOAD_XOR_I8:
7652 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
7653 case ARM::ATOMIC_LOAD_XOR_I16:
7654 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
7655 case ARM::ATOMIC_LOAD_XOR_I32:
7656 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
7658 case ARM::ATOMIC_LOAD_NAND_I8:
7659 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
7660 case ARM::ATOMIC_LOAD_NAND_I16:
7661 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
7662 case ARM::ATOMIC_LOAD_NAND_I32:
7663 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
7665 case ARM::ATOMIC_LOAD_SUB_I8:
7666 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
7667 case ARM::ATOMIC_LOAD_SUB_I16:
7668 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
7669 case ARM::ATOMIC_LOAD_SUB_I32:
7670 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
7672 case ARM::ATOMIC_LOAD_MIN_I8:
7673 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::LT);
7674 case ARM::ATOMIC_LOAD_MIN_I16:
7675 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::LT);
7676 case ARM::ATOMIC_LOAD_MIN_I32:
7677 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::LT);
7679 case ARM::ATOMIC_LOAD_MAX_I8:
7680 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::GT);
7681 case ARM::ATOMIC_LOAD_MAX_I16:
7682 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::GT);
7683 case ARM::ATOMIC_LOAD_MAX_I32:
7684 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::GT);
7686 case ARM::ATOMIC_LOAD_UMIN_I8:
7687 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::LO);
7688 case ARM::ATOMIC_LOAD_UMIN_I16:
7689 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::LO);
7690 case ARM::ATOMIC_LOAD_UMIN_I32:
7691 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::LO);
7693 case ARM::ATOMIC_LOAD_UMAX_I8:
7694 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::HI);
7695 case ARM::ATOMIC_LOAD_UMAX_I16:
7696 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::HI);
7697 case ARM::ATOMIC_LOAD_UMAX_I32:
7698 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::HI);
7700 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
7701 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
7702 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
7704 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
7705 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
7706 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
7708 case ARM::ATOMIC_LOAD_I64:
7709 return EmitAtomicLoad64(MI, BB);
7711 case ARM::ATOMIC_LOAD_ADD_I64:
7712 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr,
7713 isThumb2 ? ARM::t2ADCrr : ARM::ADCrr,
7714 /*NeedsCarry*/ true);
7715 case ARM::ATOMIC_LOAD_SUB_I64:
7716 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
7717 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
7718 /*NeedsCarry*/ true);
7719 case ARM::ATOMIC_LOAD_OR_I64:
7720 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr,
7721 isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
7722 case ARM::ATOMIC_LOAD_XOR_I64:
7723 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2EORrr : ARM::EORrr,
7724 isThumb2 ? ARM::t2EORrr : ARM::EORrr);
7725 case ARM::ATOMIC_LOAD_AND_I64:
7726 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr,
7727 isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
7728 case ARM::ATOMIC_STORE_I64:
7729 case ARM::ATOMIC_SWAP_I64:
7730 return EmitAtomicBinary64(MI, BB, 0, 0, false);
7731 case ARM::ATOMIC_CMP_SWAP_I64:
7732 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
7733 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
7734 /*NeedsCarry*/ false, /*IsCmpxchg*/true);
7735 case ARM::ATOMIC_LOAD_MIN_I64:
7736 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
7737 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
7738 /*NeedsCarry*/ true, /*IsCmpxchg*/false,
7739 /*IsMinMax*/ true, ARMCC::LT);
7740 case ARM::ATOMIC_LOAD_MAX_I64:
7741 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
7742 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
7743 /*NeedsCarry*/ true, /*IsCmpxchg*/false,
7744 /*IsMinMax*/ true, ARMCC::GE);
7745 case ARM::ATOMIC_LOAD_UMIN_I64:
7746 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
7747 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
7748 /*NeedsCarry*/ true, /*IsCmpxchg*/false,
7749 /*IsMinMax*/ true, ARMCC::LO);
7750 case ARM::ATOMIC_LOAD_UMAX_I64:
7751 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
7752 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
7753 /*NeedsCarry*/ true, /*IsCmpxchg*/false,
7754 /*IsMinMax*/ true, ARMCC::HS);
7756 case ARM::tMOVCCr_pseudo: {
7757 // To "insert" a SELECT_CC instruction, we actually have to insert the
7758 // diamond control-flow pattern. The incoming instruction knows the
7759 // destination vreg to set, the condition code register to branch on, the
7760 // true/false values to select between, and a branch opcode to use.
7761 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7762 MachineFunction::iterator It = BB;
7768 // cmpTY ccX, r1, r2
7770 // fallthrough --> copy0MBB
7771 MachineBasicBlock *thisMBB = BB;
7772 MachineFunction *F = BB->getParent();
7773 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7774 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7775 F->insert(It, copy0MBB);
7776 F->insert(It, sinkMBB);
7778 // Transfer the remainder of BB and its successor edges to sinkMBB.
7779 sinkMBB->splice(sinkMBB->begin(), BB,
7780 llvm::next(MachineBasicBlock::iterator(MI)),
7782 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7784 BB->addSuccessor(copy0MBB);
7785 BB->addSuccessor(sinkMBB);
7787 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
7788 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
7791 // %FalseValue = ...
7792 // # fallthrough to sinkMBB
7795 // Update machine-CFG edges
7796 BB->addSuccessor(sinkMBB);
7799 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7802 BuildMI(*BB, BB->begin(), dl,
7803 TII->get(ARM::PHI), MI->getOperand(0).getReg())
7804 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
7805 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7807 MI->eraseFromParent(); // The pseudo instruction is gone now.
7812 case ARM::BCCZi64: {
7813 // If there is an unconditional branch to the other successor, remove it.
7814 BB->erase(llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
7816 // Compare both parts that make up the double comparison separately for
7818 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
7820 unsigned LHS1 = MI->getOperand(1).getReg();
7821 unsigned LHS2 = MI->getOperand(2).getReg();
7823 AddDefaultPred(BuildMI(BB, dl,
7824 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7825 .addReg(LHS1).addImm(0));
7826 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7827 .addReg(LHS2).addImm(0)
7828 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
7830 unsigned RHS1 = MI->getOperand(3).getReg();
7831 unsigned RHS2 = MI->getOperand(4).getReg();
7832 AddDefaultPred(BuildMI(BB, dl,
7833 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
7834 .addReg(LHS1).addReg(RHS1));
7835 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
7836 .addReg(LHS2).addReg(RHS2)
7837 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
7840 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
7841 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
7842 if (MI->getOperand(0).getImm() == ARMCC::NE)
7843 std::swap(destMBB, exitMBB);
7845 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
7846 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
7848 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2B)).addMBB(exitMBB));
7850 BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB);
7852 MI->eraseFromParent(); // The pseudo instruction is gone now.
7856 case ARM::Int_eh_sjlj_setjmp:
7857 case ARM::Int_eh_sjlj_setjmp_nofp:
7858 case ARM::tInt_eh_sjlj_setjmp:
7859 case ARM::t2Int_eh_sjlj_setjmp:
7860 case ARM::t2Int_eh_sjlj_setjmp_nofp:
7861 EmitSjLjDispatchBlock(MI, BB);
7866 // To insert an ABS instruction, we have to insert the
7867 // diamond control-flow pattern. The incoming instruction knows the
7868 // source vreg to test against 0, the destination vreg to set,
7869 // the condition code register to branch on, the
7870 // true/false values to select between, and a branch opcode to use.
7875 // BCC (branch to SinkBB if V0 >= 0)
7876 // RSBBB: V3 = RSBri V2, 0 (compute ABS if V2 < 0)
7877 // SinkBB: V1 = PHI(V2, V3)
7878 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7879 MachineFunction::iterator BBI = BB;
7881 MachineFunction *Fn = BB->getParent();
7882 MachineBasicBlock *RSBBB = Fn->CreateMachineBasicBlock(LLVM_BB);
7883 MachineBasicBlock *SinkBB = Fn->CreateMachineBasicBlock(LLVM_BB);
7884 Fn->insert(BBI, RSBBB);
7885 Fn->insert(BBI, SinkBB);
7887 unsigned int ABSSrcReg = MI->getOperand(1).getReg();
7888 unsigned int ABSDstReg = MI->getOperand(0).getReg();
7889 bool isThumb2 = Subtarget->isThumb2();
7890 MachineRegisterInfo &MRI = Fn->getRegInfo();
7891 // In Thumb mode S must not be specified if source register is the SP or
7892 // PC and if destination register is the SP, so restrict register class
7893 unsigned NewRsbDstReg = MRI.createVirtualRegister(isThumb2 ?
7894 (const TargetRegisterClass*)&ARM::rGPRRegClass :
7895 (const TargetRegisterClass*)&ARM::GPRRegClass);
7897 // Transfer the remainder of BB and its successor edges to sinkMBB.
7898 SinkBB->splice(SinkBB->begin(), BB,
7899 llvm::next(MachineBasicBlock::iterator(MI)),
7901 SinkBB->transferSuccessorsAndUpdatePHIs(BB);
7903 BB->addSuccessor(RSBBB);
7904 BB->addSuccessor(SinkBB);
7906 // fall through to SinkMBB
7907 RSBBB->addSuccessor(SinkBB);
7909 // insert a cmp at the end of BB
7910 AddDefaultPred(BuildMI(BB, dl,
7911 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7912 .addReg(ABSSrcReg).addImm(0));
7914 // insert a bcc with opposite CC to ARMCC::MI at the end of BB
7916 TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)).addMBB(SinkBB)
7917 .addImm(ARMCC::getOppositeCondition(ARMCC::MI)).addReg(ARM::CPSR);
7919 // insert rsbri in RSBBB
7920 // Note: BCC and rsbri will be converted into predicated rsbmi
7921 // by if-conversion pass
7922 BuildMI(*RSBBB, RSBBB->begin(), dl,
7923 TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg)
7924 .addReg(ABSSrcReg, RegState::Kill)
7925 .addImm(0).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
7927 // insert PHI in SinkBB,
7928 // reuse ABSDstReg to not change uses of ABS instruction
7929 BuildMI(*SinkBB, SinkBB->begin(), dl,
7930 TII->get(ARM::PHI), ABSDstReg)
7931 .addReg(NewRsbDstReg).addMBB(RSBBB)
7932 .addReg(ABSSrcReg).addMBB(BB);
7934 // remove ABS instruction
7935 MI->eraseFromParent();
7937 // return last added BB
7940 case ARM::COPY_STRUCT_BYVAL_I32:
7942 return EmitStructByval(MI, BB);
7946 void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
7947 SDNode *Node) const {
7948 if (!MI->hasPostISelHook()) {
7949 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
7950 "Pseudo flag-setting opcodes must be marked with 'hasPostISelHook'");
7954 const MCInstrDesc *MCID = &MI->getDesc();
7955 // Adjust potentially 's' setting instructions after isel, i.e. ADC, SBC, RSB,
7956 // RSC. Coming out of isel, they have an implicit CPSR def, but the optional
7957 // operand is still set to noreg. If needed, set the optional operand's
7958 // register to CPSR, and remove the redundant implicit def.
7960 // e.g. ADCS (..., CPSR<imp-def>) -> ADC (... opt:CPSR<def>).
7962 // Rename pseudo opcodes.
7963 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode());
7965 const ARMBaseInstrInfo *TII =
7966 static_cast<const ARMBaseInstrInfo*>(getTargetMachine().getInstrInfo());
7967 MCID = &TII->get(NewOpc);
7969 assert(MCID->getNumOperands() == MI->getDesc().getNumOperands() + 1 &&
7970 "converted opcode should be the same except for cc_out");
7974 // Add the optional cc_out operand
7975 MI->addOperand(MachineOperand::CreateReg(0, /*isDef=*/true));
7977 unsigned ccOutIdx = MCID->getNumOperands() - 1;
7979 // Any ARM instruction that sets the 's' bit should specify an optional
7980 // "cc_out" operand in the last operand position.
7981 if (!MI->hasOptionalDef() || !MCID->OpInfo[ccOutIdx].isOptionalDef()) {
7982 assert(!NewOpc && "Optional cc_out operand required");
7985 // Look for an implicit def of CPSR added by MachineInstr ctor. Remove it
7986 // since we already have an optional CPSR def.
7987 bool definesCPSR = false;
7988 bool deadCPSR = false;
7989 for (unsigned i = MCID->getNumOperands(), e = MI->getNumOperands();
7991 const MachineOperand &MO = MI->getOperand(i);
7992 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) {
7996 MI->RemoveOperand(i);
8001 assert(!NewOpc && "Optional cc_out operand required");
8004 assert(deadCPSR == !Node->hasAnyUseOfValue(1) && "inconsistent dead flag");
8006 assert(!MI->getOperand(ccOutIdx).getReg() &&
8007 "expect uninitialized optional cc_out operand");
8011 // If this instruction was defined with an optional CPSR def and its dag node
8012 // had a live implicit CPSR def, then activate the optional CPSR def.
8013 MachineOperand &MO = MI->getOperand(ccOutIdx);
8014 MO.setReg(ARM::CPSR);
8018 //===----------------------------------------------------------------------===//
8019 // ARM Optimization Hooks
8020 //===----------------------------------------------------------------------===//
8022 // Helper function that checks if N is a null or all ones constant.
8023 static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) {
8024 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
8027 return AllOnes ? C->isAllOnesValue() : C->isNullValue();
8030 // Return true if N is conditionally 0 or all ones.
8031 // Detects these expressions where cc is an i1 value:
8033 // (select cc 0, y) [AllOnes=0]
8034 // (select cc y, 0) [AllOnes=0]
8035 // (zext cc) [AllOnes=0]
8036 // (sext cc) [AllOnes=0/1]
8037 // (select cc -1, y) [AllOnes=1]
8038 // (select cc y, -1) [AllOnes=1]
8040 // Invert is set when N is the null/all ones constant when CC is false.
8041 // OtherOp is set to the alternative value of N.
8042 static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes,
8043 SDValue &CC, bool &Invert,
8045 SelectionDAG &DAG) {
8046 switch (N->getOpcode()) {
8047 default: return false;
8049 CC = N->getOperand(0);
8050 SDValue N1 = N->getOperand(1);
8051 SDValue N2 = N->getOperand(2);
8052 if (isZeroOrAllOnes(N1, AllOnes)) {
8057 if (isZeroOrAllOnes(N2, AllOnes)) {
8064 case ISD::ZERO_EXTEND:
8065 // (zext cc) can never be the all ones value.
8069 case ISD::SIGN_EXTEND: {
8070 EVT VT = N->getValueType(0);
8071 CC = N->getOperand(0);
8072 if (CC.getValueType() != MVT::i1)
8076 // When looking for an AllOnes constant, N is an sext, and the 'other'
8078 OtherOp = DAG.getConstant(0, VT);
8079 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8080 // When looking for a 0 constant, N can be zext or sext.
8081 OtherOp = DAG.getConstant(1, VT);
8083 OtherOp = DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT);
8089 // Combine a constant select operand into its use:
8091 // (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
8092 // (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
8093 // (and (select cc, -1, c), x) -> (select cc, x, (and, x, c)) [AllOnes=1]
8094 // (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
8095 // (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
8097 // The transform is rejected if the select doesn't have a constant operand that
8098 // is null, or all ones when AllOnes is set.
8100 // Also recognize sext/zext from i1:
8102 // (add (zext cc), x) -> (select cc (add x, 1), x)
8103 // (add (sext cc), x) -> (select cc (add x, -1), x)
8105 // These transformations eventually create predicated instructions.
8107 // @param N The node to transform.
8108 // @param Slct The N operand that is a select.
8109 // @param OtherOp The other N operand (x above).
8110 // @param DCI Context.
8111 // @param AllOnes Require the select constant to be all ones instead of null.
8112 // @returns The new node, or SDValue() on failure.
8114 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
8115 TargetLowering::DAGCombinerInfo &DCI,
8116 bool AllOnes = false) {
8117 SelectionDAG &DAG = DCI.DAG;
8118 EVT VT = N->getValueType(0);
8119 SDValue NonConstantVal;
8122 if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps,
8123 NonConstantVal, DAG))
8126 // Slct is now know to be the desired identity constant when CC is true.
8127 SDValue TrueVal = OtherOp;
8128 SDValue FalseVal = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
8129 OtherOp, NonConstantVal);
8130 // Unless SwapSelectOps says CC should be false.
8132 std::swap(TrueVal, FalseVal);
8134 return DAG.getNode(ISD::SELECT, SDLoc(N), VT,
8135 CCOp, TrueVal, FalseVal);
8138 // Attempt combineSelectAndUse on each operand of a commutative operator N.
8140 SDValue combineSelectAndUseCommutative(SDNode *N, bool AllOnes,
8141 TargetLowering::DAGCombinerInfo &DCI) {
8142 SDValue N0 = N->getOperand(0);
8143 SDValue N1 = N->getOperand(1);
8144 if (N0.getNode()->hasOneUse()) {
8145 SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes);
8146 if (Result.getNode())
8149 if (N1.getNode()->hasOneUse()) {
8150 SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes);
8151 if (Result.getNode())
8157 // AddCombineToVPADDL- For pair-wise add on neon, use the vpaddl instruction
8158 // (only after legalization).
8159 static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
8160 TargetLowering::DAGCombinerInfo &DCI,
8161 const ARMSubtarget *Subtarget) {
8163 // Only perform optimization if after legalize, and if NEON is available. We
8164 // also expected both operands to be BUILD_VECTORs.
8165 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON()
8166 || N0.getOpcode() != ISD::BUILD_VECTOR
8167 || N1.getOpcode() != ISD::BUILD_VECTOR)
8170 // Check output type since VPADDL operand elements can only be 8, 16, or 32.
8171 EVT VT = N->getValueType(0);
8172 if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64)
8175 // Check that the vector operands are of the right form.
8176 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR
8177 // operands, where N is the size of the formed vector.
8178 // Each EXTRACT_VECTOR should have the same input vector and odd or even
8179 // index such that we have a pair wise add pattern.
8181 // Grab the vector that all EXTRACT_VECTOR nodes should be referencing.
8182 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
8184 SDValue Vec = N0->getOperand(0)->getOperand(0);
8185 SDNode *V = Vec.getNode();
8186 unsigned nextIndex = 0;
8188 // For each operands to the ADD which are BUILD_VECTORs,
8189 // check to see if each of their operands are an EXTRACT_VECTOR with
8190 // the same vector and appropriate index.
8191 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) {
8192 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT
8193 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
8195 SDValue ExtVec0 = N0->getOperand(i);
8196 SDValue ExtVec1 = N1->getOperand(i);
8198 // First operand is the vector, verify its the same.
8199 if (V != ExtVec0->getOperand(0).getNode() ||
8200 V != ExtVec1->getOperand(0).getNode())
8203 // Second is the constant, verify its correct.
8204 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(ExtVec0->getOperand(1));
8205 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(ExtVec1->getOperand(1));
8207 // For the constant, we want to see all the even or all the odd.
8208 if (!C0 || !C1 || C0->getZExtValue() != nextIndex
8209 || C1->getZExtValue() != nextIndex+1)
8218 // Create VPADDL node.
8219 SelectionDAG &DAG = DCI.DAG;
8220 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8222 // Build operand list.
8223 SmallVector<SDValue, 8> Ops;
8224 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddls,
8225 TLI.getPointerTy()));
8227 // Input is the vector.
8230 // Get widened type and narrowed type.
8232 unsigned numElem = VT.getVectorNumElements();
8233 switch (VT.getVectorElementType().getSimpleVT().SimpleTy) {
8234 case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break;
8235 case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break;
8236 case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break;
8238 llvm_unreachable("Invalid vector element type for padd optimization.");
8241 SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N),
8242 widenType, &Ops[0], Ops.size());
8243 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, tmp);
8246 static SDValue findMUL_LOHI(SDValue V) {
8247 if (V->getOpcode() == ISD::UMUL_LOHI ||
8248 V->getOpcode() == ISD::SMUL_LOHI)
8253 static SDValue AddCombineTo64bitMLAL(SDNode *AddcNode,
8254 TargetLowering::DAGCombinerInfo &DCI,
8255 const ARMSubtarget *Subtarget) {
8257 if (Subtarget->isThumb1Only()) return SDValue();
8259 // Only perform the checks after legalize when the pattern is available.
8260 if (DCI.isBeforeLegalize()) return SDValue();
8262 // Look for multiply add opportunities.
8263 // The pattern is a ISD::UMUL_LOHI followed by two add nodes, where
8264 // each add nodes consumes a value from ISD::UMUL_LOHI and there is
8265 // a glue link from the first add to the second add.
8266 // If we find this pattern, we can replace the U/SMUL_LOHI, ADDC, and ADDE by
8267 // a S/UMLAL instruction.
8270 // \ / \ [no multiline comment]
8276 assert(AddcNode->getOpcode() == ISD::ADDC && "Expect an ADDC");
8277 SDValue AddcOp0 = AddcNode->getOperand(0);
8278 SDValue AddcOp1 = AddcNode->getOperand(1);
8280 // Check if the two operands are from the same mul_lohi node.
8281 if (AddcOp0.getNode() == AddcOp1.getNode())
8284 assert(AddcNode->getNumValues() == 2 &&
8285 AddcNode->getValueType(0) == MVT::i32 &&
8286 "Expect ADDC with two result values. First: i32");
8288 // Check that we have a glued ADDC node.
8289 if (AddcNode->getValueType(1) != MVT::Glue)
8292 // Check that the ADDC adds the low result of the S/UMUL_LOHI.
8293 if (AddcOp0->getOpcode() != ISD::UMUL_LOHI &&
8294 AddcOp0->getOpcode() != ISD::SMUL_LOHI &&
8295 AddcOp1->getOpcode() != ISD::UMUL_LOHI &&
8296 AddcOp1->getOpcode() != ISD::SMUL_LOHI)
8299 // Look for the glued ADDE.
8300 SDNode* AddeNode = AddcNode->getGluedUser();
8301 if (AddeNode == NULL)
8304 // Make sure it is really an ADDE.
8305 if (AddeNode->getOpcode() != ISD::ADDE)
8308 assert(AddeNode->getNumOperands() == 3 &&
8309 AddeNode->getOperand(2).getValueType() == MVT::Glue &&
8310 "ADDE node has the wrong inputs");
8312 // Check for the triangle shape.
8313 SDValue AddeOp0 = AddeNode->getOperand(0);
8314 SDValue AddeOp1 = AddeNode->getOperand(1);
8316 // Make sure that the ADDE operands are not coming from the same node.
8317 if (AddeOp0.getNode() == AddeOp1.getNode())
8320 // Find the MUL_LOHI node walking up ADDE's operands.
8321 bool IsLeftOperandMUL = false;
8322 SDValue MULOp = findMUL_LOHI(AddeOp0);
8323 if (MULOp == SDValue())
8324 MULOp = findMUL_LOHI(AddeOp1);
8326 IsLeftOperandMUL = true;
8327 if (MULOp == SDValue())
8330 // Figure out the right opcode.
8331 unsigned Opc = MULOp->getOpcode();
8332 unsigned FinalOpc = (Opc == ISD::SMUL_LOHI) ? ARMISD::SMLAL : ARMISD::UMLAL;
8334 // Figure out the high and low input values to the MLAL node.
8335 SDValue* HiMul = &MULOp;
8336 SDValue* HiAdd = NULL;
8337 SDValue* LoMul = NULL;
8338 SDValue* LowAdd = NULL;
8340 if (IsLeftOperandMUL)
8346 if (AddcOp0->getOpcode() == Opc) {
8350 if (AddcOp1->getOpcode() == Opc) {
8358 if (LoMul->getNode() != HiMul->getNode())
8361 // Create the merged node.
8362 SelectionDAG &DAG = DCI.DAG;
8364 // Build operand list.
8365 SmallVector<SDValue, 8> Ops;
8366 Ops.push_back(LoMul->getOperand(0));
8367 Ops.push_back(LoMul->getOperand(1));
8368 Ops.push_back(*LowAdd);
8369 Ops.push_back(*HiAdd);
8371 SDValue MLALNode = DAG.getNode(FinalOpc, SDLoc(AddcNode),
8372 DAG.getVTList(MVT::i32, MVT::i32),
8373 &Ops[0], Ops.size());
8375 // Replace the ADDs' nodes uses by the MLA node's values.
8376 SDValue HiMLALResult(MLALNode.getNode(), 1);
8377 DAG.ReplaceAllUsesOfValueWith(SDValue(AddeNode, 0), HiMLALResult);
8379 SDValue LoMLALResult(MLALNode.getNode(), 0);
8380 DAG.ReplaceAllUsesOfValueWith(SDValue(AddcNode, 0), LoMLALResult);
8382 // Return original node to notify the driver to stop replacing.
8383 SDValue resNode(AddcNode, 0);
8387 /// PerformADDCCombine - Target-specific dag combine transform from
8388 /// ISD::ADDC, ISD::ADDE, and ISD::MUL_LOHI to MLAL.
8389 static SDValue PerformADDCCombine(SDNode *N,
8390 TargetLowering::DAGCombinerInfo &DCI,
8391 const ARMSubtarget *Subtarget) {
8393 return AddCombineTo64bitMLAL(N, DCI, Subtarget);
8397 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
8398 /// operands N0 and N1. This is a helper for PerformADDCombine that is
8399 /// called with the default operands, and if that fails, with commuted
8401 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
8402 TargetLowering::DAGCombinerInfo &DCI,
8403 const ARMSubtarget *Subtarget){
8405 // Attempt to create vpaddl for this add.
8406 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget);
8407 if (Result.getNode())
8410 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
8411 if (N0.getNode()->hasOneUse()) {
8412 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
8413 if (Result.getNode()) return Result;
8418 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
8420 static SDValue PerformADDCombine(SDNode *N,
8421 TargetLowering::DAGCombinerInfo &DCI,
8422 const ARMSubtarget *Subtarget) {
8423 SDValue N0 = N->getOperand(0);
8424 SDValue N1 = N->getOperand(1);
8426 // First try with the default operand order.
8427 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget);
8428 if (Result.getNode())
8431 // If that didn't work, try again with the operands commuted.
8432 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget);
8435 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
8437 static SDValue PerformSUBCombine(SDNode *N,
8438 TargetLowering::DAGCombinerInfo &DCI) {
8439 SDValue N0 = N->getOperand(0);
8440 SDValue N1 = N->getOperand(1);
8442 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
8443 if (N1.getNode()->hasOneUse()) {
8444 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
8445 if (Result.getNode()) return Result;
8451 /// PerformVMULCombine
8452 /// Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the
8453 /// special multiplier accumulator forwarding.
8459 // However, for (A + B) * (A + B),
8466 static SDValue PerformVMULCombine(SDNode *N,
8467 TargetLowering::DAGCombinerInfo &DCI,
8468 const ARMSubtarget *Subtarget) {
8469 if (!Subtarget->hasVMLxForwarding())
8472 SelectionDAG &DAG = DCI.DAG;
8473 SDValue N0 = N->getOperand(0);
8474 SDValue N1 = N->getOperand(1);
8475 unsigned Opcode = N0.getOpcode();
8476 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
8477 Opcode != ISD::FADD && Opcode != ISD::FSUB) {
8478 Opcode = N1.getOpcode();
8479 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
8480 Opcode != ISD::FADD && Opcode != ISD::FSUB)
8488 EVT VT = N->getValueType(0);
8490 SDValue N00 = N0->getOperand(0);
8491 SDValue N01 = N0->getOperand(1);
8492 return DAG.getNode(Opcode, DL, VT,
8493 DAG.getNode(ISD::MUL, DL, VT, N00, N1),
8494 DAG.getNode(ISD::MUL, DL, VT, N01, N1));
8497 static SDValue PerformMULCombine(SDNode *N,
8498 TargetLowering::DAGCombinerInfo &DCI,
8499 const ARMSubtarget *Subtarget) {
8500 SelectionDAG &DAG = DCI.DAG;
8502 if (Subtarget->isThumb1Only())
8505 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8508 EVT VT = N->getValueType(0);
8509 if (VT.is64BitVector() || VT.is128BitVector())
8510 return PerformVMULCombine(N, DCI, Subtarget);
8514 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
8518 int64_t MulAmt = C->getSExtValue();
8519 unsigned ShiftAmt = countTrailingZeros<uint64_t>(MulAmt);
8521 ShiftAmt = ShiftAmt & (32 - 1);
8522 SDValue V = N->getOperand(0);
8526 MulAmt >>= ShiftAmt;
8529 if (isPowerOf2_32(MulAmt - 1)) {
8530 // (mul x, 2^N + 1) => (add (shl x, N), x)
8531 Res = DAG.getNode(ISD::ADD, DL, VT,
8533 DAG.getNode(ISD::SHL, DL, VT,
8535 DAG.getConstant(Log2_32(MulAmt - 1),
8537 } else if (isPowerOf2_32(MulAmt + 1)) {
8538 // (mul x, 2^N - 1) => (sub (shl x, N), x)
8539 Res = DAG.getNode(ISD::SUB, DL, VT,
8540 DAG.getNode(ISD::SHL, DL, VT,
8542 DAG.getConstant(Log2_32(MulAmt + 1),
8548 uint64_t MulAmtAbs = -MulAmt;
8549 if (isPowerOf2_32(MulAmtAbs + 1)) {
8550 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
8551 Res = DAG.getNode(ISD::SUB, DL, VT,
8553 DAG.getNode(ISD::SHL, DL, VT,
8555 DAG.getConstant(Log2_32(MulAmtAbs + 1),
8557 } else if (isPowerOf2_32(MulAmtAbs - 1)) {
8558 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
8559 Res = DAG.getNode(ISD::ADD, DL, VT,
8561 DAG.getNode(ISD::SHL, DL, VT,
8563 DAG.getConstant(Log2_32(MulAmtAbs-1),
8565 Res = DAG.getNode(ISD::SUB, DL, VT,
8566 DAG.getConstant(0, MVT::i32),Res);
8573 Res = DAG.getNode(ISD::SHL, DL, VT,
8574 Res, DAG.getConstant(ShiftAmt, MVT::i32));
8576 // Do not add new nodes to DAG combiner worklist.
8577 DCI.CombineTo(N, Res, false);
8581 static SDValue PerformANDCombine(SDNode *N,
8582 TargetLowering::DAGCombinerInfo &DCI,
8583 const ARMSubtarget *Subtarget) {
8585 // Attempt to use immediate-form VBIC
8586 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
8588 EVT VT = N->getValueType(0);
8589 SelectionDAG &DAG = DCI.DAG;
8591 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8594 APInt SplatBits, SplatUndef;
8595 unsigned SplatBitSize;
8598 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
8599 if (SplatBitSize <= 64) {
8601 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
8602 SplatUndef.getZExtValue(), SplatBitSize,
8603 DAG, VbicVT, VT.is128BitVector(),
8605 if (Val.getNode()) {
8607 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
8608 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
8609 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
8614 if (!Subtarget->isThumb1Only()) {
8615 // fold (and (select cc, -1, c), x) -> (select cc, x, (and, x, c))
8616 SDValue Result = combineSelectAndUseCommutative(N, true, DCI);
8617 if (Result.getNode())
8624 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
8625 static SDValue PerformORCombine(SDNode *N,
8626 TargetLowering::DAGCombinerInfo &DCI,
8627 const ARMSubtarget *Subtarget) {
8628 // Attempt to use immediate-form VORR
8629 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
8631 EVT VT = N->getValueType(0);
8632 SelectionDAG &DAG = DCI.DAG;
8634 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8637 APInt SplatBits, SplatUndef;
8638 unsigned SplatBitSize;
8640 if (BVN && Subtarget->hasNEON() &&
8641 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
8642 if (SplatBitSize <= 64) {
8644 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
8645 SplatUndef.getZExtValue(), SplatBitSize,
8646 DAG, VorrVT, VT.is128BitVector(),
8648 if (Val.getNode()) {
8650 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
8651 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
8652 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
8657 if (!Subtarget->isThumb1Only()) {
8658 // fold (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
8659 SDValue Result = combineSelectAndUseCommutative(N, false, DCI);
8660 if (Result.getNode())
8664 // The code below optimizes (or (and X, Y), Z).
8665 // The AND operand needs to have a single user to make these optimizations
8667 SDValue N0 = N->getOperand(0);
8668 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse())
8670 SDValue N1 = N->getOperand(1);
8672 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant.
8673 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
8674 DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
8676 unsigned SplatBitSize;
8679 APInt SplatBits0, SplatBits1;
8680 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
8681 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
8682 // Ensure that the second operand of both ands are constants
8683 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize,
8684 HasAnyUndefs) && !HasAnyUndefs) {
8685 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize,
8686 HasAnyUndefs) && !HasAnyUndefs) {
8687 // Ensure that the bit width of the constants are the same and that
8688 // the splat arguments are logical inverses as per the pattern we
8689 // are trying to simplify.
8690 if (SplatBits0.getBitWidth() == SplatBits1.getBitWidth() &&
8691 SplatBits0 == ~SplatBits1) {
8692 // Canonicalize the vector type to make instruction selection
8694 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
8695 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT,
8699 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
8705 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
8708 // BFI is only available on V6T2+
8709 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
8713 // 1) or (and A, mask), val => ARMbfi A, val, mask
8714 // iff (val & mask) == val
8716 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
8717 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
8718 // && mask == ~mask2
8719 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
8720 // && ~mask == mask2
8721 // (i.e., copy a bitfield value into another bitfield of the same width)
8726 SDValue N00 = N0.getOperand(0);
8728 // The value and the mask need to be constants so we can verify this is
8729 // actually a bitfield set. If the mask is 0xffff, we can do better
8730 // via a movt instruction, so don't use BFI in that case.
8731 SDValue MaskOp = N0.getOperand(1);
8732 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
8735 unsigned Mask = MaskC->getZExtValue();
8739 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
8740 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
8742 unsigned Val = N1C->getZExtValue();
8743 if ((Val & ~Mask) != Val)
8746 if (ARM::isBitFieldInvertedMask(Mask)) {
8747 Val >>= countTrailingZeros(~Mask);
8749 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
8750 DAG.getConstant(Val, MVT::i32),
8751 DAG.getConstant(Mask, MVT::i32));
8753 // Do not add new nodes to DAG combiner worklist.
8754 DCI.CombineTo(N, Res, false);
8757 } else if (N1.getOpcode() == ISD::AND) {
8758 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
8759 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
8762 unsigned Mask2 = N11C->getZExtValue();
8764 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern
8766 if (ARM::isBitFieldInvertedMask(Mask) &&
8768 // The pack halfword instruction works better for masks that fit it,
8769 // so use that when it's available.
8770 if (Subtarget->hasT2ExtractPack() &&
8771 (Mask == 0xffff || Mask == 0xffff0000))
8774 unsigned amt = countTrailingZeros(Mask2);
8775 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
8776 DAG.getConstant(amt, MVT::i32));
8777 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
8778 DAG.getConstant(Mask, MVT::i32));
8779 // Do not add new nodes to DAG combiner worklist.
8780 DCI.CombineTo(N, Res, false);
8782 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
8784 // The pack halfword instruction works better for masks that fit it,
8785 // so use that when it's available.
8786 if (Subtarget->hasT2ExtractPack() &&
8787 (Mask2 == 0xffff || Mask2 == 0xffff0000))
8790 unsigned lsb = countTrailingZeros(Mask);
8791 Res = DAG.getNode(ISD::SRL, DL, VT, N00,
8792 DAG.getConstant(lsb, MVT::i32));
8793 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
8794 DAG.getConstant(Mask2, MVT::i32));
8795 // Do not add new nodes to DAG combiner worklist.
8796 DCI.CombineTo(N, Res, false);
8801 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
8802 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
8803 ARM::isBitFieldInvertedMask(~Mask)) {
8804 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
8805 // where lsb(mask) == #shamt and masked bits of B are known zero.
8806 SDValue ShAmt = N00.getOperand(1);
8807 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
8808 unsigned LSB = countTrailingZeros(Mask);
8812 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
8813 DAG.getConstant(~Mask, MVT::i32));
8815 // Do not add new nodes to DAG combiner worklist.
8816 DCI.CombineTo(N, Res, false);
8822 static SDValue PerformXORCombine(SDNode *N,
8823 TargetLowering::DAGCombinerInfo &DCI,
8824 const ARMSubtarget *Subtarget) {
8825 EVT VT = N->getValueType(0);
8826 SelectionDAG &DAG = DCI.DAG;
8828 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8831 if (!Subtarget->isThumb1Only()) {
8832 // fold (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
8833 SDValue Result = combineSelectAndUseCommutative(N, false, DCI);
8834 if (Result.getNode())
8841 /// PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff
8842 /// the bits being cleared by the AND are not demanded by the BFI.
8843 static SDValue PerformBFICombine(SDNode *N,
8844 TargetLowering::DAGCombinerInfo &DCI) {
8845 SDValue N1 = N->getOperand(1);
8846 if (N1.getOpcode() == ISD::AND) {
8847 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
8850 unsigned InvMask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
8851 unsigned LSB = countTrailingZeros(~InvMask);
8852 unsigned Width = (32 - countLeadingZeros(~InvMask)) - LSB;
8853 unsigned Mask = (1 << Width)-1;
8854 unsigned Mask2 = N11C->getZExtValue();
8855 if ((Mask & (~Mask2)) == 0)
8856 return DCI.DAG.getNode(ARMISD::BFI, SDLoc(N), N->getValueType(0),
8857 N->getOperand(0), N1.getOperand(0),
8863 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
8864 /// ARMISD::VMOVRRD.
8865 static SDValue PerformVMOVRRDCombine(SDNode *N,
8866 TargetLowering::DAGCombinerInfo &DCI) {
8867 // vmovrrd(vmovdrr x, y) -> x,y
8868 SDValue InDouble = N->getOperand(0);
8869 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
8870 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
8872 // vmovrrd(load f64) -> (load i32), (load i32)
8873 SDNode *InNode = InDouble.getNode();
8874 if (ISD::isNormalLoad(InNode) && InNode->hasOneUse() &&
8875 InNode->getValueType(0) == MVT::f64 &&
8876 InNode->getOperand(1).getOpcode() == ISD::FrameIndex &&
8877 !cast<LoadSDNode>(InNode)->isVolatile()) {
8878 // TODO: Should this be done for non-FrameIndex operands?
8879 LoadSDNode *LD = cast<LoadSDNode>(InNode);
8881 SelectionDAG &DAG = DCI.DAG;
8883 SDValue BasePtr = LD->getBasePtr();
8884 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr,
8885 LD->getPointerInfo(), LD->isVolatile(),
8886 LD->isNonTemporal(), LD->isInvariant(),
8887 LD->getAlignment());
8889 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
8890 DAG.getConstant(4, MVT::i32));
8891 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr,
8892 LD->getPointerInfo(), LD->isVolatile(),
8893 LD->isNonTemporal(), LD->isInvariant(),
8894 std::min(4U, LD->getAlignment() / 2));
8896 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1));
8897 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2);
8898 DCI.RemoveFromWorklist(LD);
8906 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
8907 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
8908 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
8909 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
8910 SDValue Op0 = N->getOperand(0);
8911 SDValue Op1 = N->getOperand(1);
8912 if (Op0.getOpcode() == ISD::BITCAST)
8913 Op0 = Op0.getOperand(0);
8914 if (Op1.getOpcode() == ISD::BITCAST)
8915 Op1 = Op1.getOperand(0);
8916 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
8917 Op0.getNode() == Op1.getNode() &&
8918 Op0.getResNo() == 0 && Op1.getResNo() == 1)
8919 return DAG.getNode(ISD::BITCAST, SDLoc(N),
8920 N->getValueType(0), Op0.getOperand(0));
8924 /// PerformSTORECombine - Target-specific dag combine xforms for
8926 static SDValue PerformSTORECombine(SDNode *N,
8927 TargetLowering::DAGCombinerInfo &DCI) {
8928 StoreSDNode *St = cast<StoreSDNode>(N);
8929 if (St->isVolatile())
8932 // Optimize trunc store (of multiple scalars) to shuffle and store. First,
8933 // pack all of the elements in one place. Next, store to memory in fewer
8935 SDValue StVal = St->getValue();
8936 EVT VT = StVal.getValueType();
8937 if (St->isTruncatingStore() && VT.isVector()) {
8938 SelectionDAG &DAG = DCI.DAG;
8939 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8940 EVT StVT = St->getMemoryVT();
8941 unsigned NumElems = VT.getVectorNumElements();
8942 assert(StVT != VT && "Cannot truncate to the same type");
8943 unsigned FromEltSz = VT.getVectorElementType().getSizeInBits();
8944 unsigned ToEltSz = StVT.getVectorElementType().getSizeInBits();
8946 // From, To sizes and ElemCount must be pow of two
8947 if (!isPowerOf2_32(NumElems * FromEltSz * ToEltSz)) return SDValue();
8949 // We are going to use the original vector elt for storing.
8950 // Accumulated smaller vector elements must be a multiple of the store size.
8951 if (0 != (NumElems * FromEltSz) % ToEltSz) return SDValue();
8953 unsigned SizeRatio = FromEltSz / ToEltSz;
8954 assert(SizeRatio * NumElems * ToEltSz == VT.getSizeInBits());
8956 // Create a type on which we perform the shuffle.
8957 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), StVT.getScalarType(),
8958 NumElems*SizeRatio);
8959 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
8962 SDValue WideVec = DAG.getNode(ISD::BITCAST, DL, WideVecVT, StVal);
8963 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
8964 for (unsigned i = 0; i < NumElems; ++i) ShuffleVec[i] = i * SizeRatio;
8966 // Can't shuffle using an illegal type.
8967 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
8969 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, DL, WideVec,
8970 DAG.getUNDEF(WideVec.getValueType()),
8972 // At this point all of the data is stored at the bottom of the
8973 // register. We now need to save it to mem.
8975 // Find the largest store unit
8976 MVT StoreType = MVT::i8;
8977 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
8978 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
8979 MVT Tp = (MVT::SimpleValueType)tp;
8980 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToEltSz)
8983 // Didn't find a legal store type.
8984 if (!TLI.isTypeLegal(StoreType))
8987 // Bitcast the original vector into a vector of store-size units
8988 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
8989 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
8990 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
8991 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, DL, StoreVecVT, Shuff);
8992 SmallVector<SDValue, 8> Chains;
8993 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
8994 TLI.getPointerTy());
8995 SDValue BasePtr = St->getBasePtr();
8997 // Perform one or more big stores into memory.
8998 unsigned E = (ToEltSz*NumElems)/StoreType.getSizeInBits();
8999 for (unsigned I = 0; I < E; I++) {
9000 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
9001 StoreType, ShuffWide,
9002 DAG.getIntPtrConstant(I));
9003 SDValue Ch = DAG.getStore(St->getChain(), DL, SubVec, BasePtr,
9004 St->getPointerInfo(), St->isVolatile(),
9005 St->isNonTemporal(), St->getAlignment());
9006 BasePtr = DAG.getNode(ISD::ADD, DL, BasePtr.getValueType(), BasePtr,
9008 Chains.push_back(Ch);
9010 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &Chains[0],
9014 if (!ISD::isNormalStore(St))
9017 // Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and
9018 // ARM stores of arguments in the same cache line.
9019 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
9020 StVal.getNode()->hasOneUse()) {
9021 SelectionDAG &DAG = DCI.DAG;
9023 SDValue BasePtr = St->getBasePtr();
9024 SDValue NewST1 = DAG.getStore(St->getChain(), DL,
9025 StVal.getNode()->getOperand(0), BasePtr,
9026 St->getPointerInfo(), St->isVolatile(),
9027 St->isNonTemporal(), St->getAlignment());
9029 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
9030 DAG.getConstant(4, MVT::i32));
9031 return DAG.getStore(NewST1.getValue(0), DL, StVal.getNode()->getOperand(1),
9032 OffsetPtr, St->getPointerInfo(), St->isVolatile(),
9033 St->isNonTemporal(),
9034 std::min(4U, St->getAlignment() / 2));
9037 if (StVal.getValueType() != MVT::i64 ||
9038 StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9041 // Bitcast an i64 store extracted from a vector to f64.
9042 // Otherwise, the i64 value will be legalized to a pair of i32 values.
9043 SelectionDAG &DAG = DCI.DAG;
9045 SDValue IntVec = StVal.getOperand(0);
9046 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
9047 IntVec.getValueType().getVectorNumElements());
9048 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec);
9049 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
9050 Vec, StVal.getOperand(1));
9052 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
9053 // Make the DAGCombiner fold the bitcasts.
9054 DCI.AddToWorklist(Vec.getNode());
9055 DCI.AddToWorklist(ExtElt.getNode());
9056 DCI.AddToWorklist(V.getNode());
9057 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(),
9058 St->getPointerInfo(), St->isVolatile(),
9059 St->isNonTemporal(), St->getAlignment(),
9063 /// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node
9064 /// are normal, non-volatile loads. If so, it is profitable to bitcast an
9065 /// i64 vector to have f64 elements, since the value can then be loaded
9066 /// directly into a VFP register.
9067 static bool hasNormalLoadOperand(SDNode *N) {
9068 unsigned NumElts = N->getValueType(0).getVectorNumElements();
9069 for (unsigned i = 0; i < NumElts; ++i) {
9070 SDNode *Elt = N->getOperand(i).getNode();
9071 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile())
9077 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
9078 /// ISD::BUILD_VECTOR.
9079 static SDValue PerformBUILD_VECTORCombine(SDNode *N,
9080 TargetLowering::DAGCombinerInfo &DCI){
9081 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
9082 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
9083 // into a pair of GPRs, which is fine when the value is used as a scalar,
9084 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
9085 SelectionDAG &DAG = DCI.DAG;
9086 if (N->getNumOperands() == 2) {
9087 SDValue RV = PerformVMOVDRRCombine(N, DAG);
9092 // Load i64 elements as f64 values so that type legalization does not split
9093 // them up into i32 values.
9094 EVT VT = N->getValueType(0);
9095 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))
9098 SmallVector<SDValue, 8> Ops;
9099 unsigned NumElts = VT.getVectorNumElements();
9100 for (unsigned i = 0; i < NumElts; ++i) {
9101 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i));
9103 // Make the DAGCombiner fold the bitcast.
9104 DCI.AddToWorklist(V.getNode());
9106 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts);
9107 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops.data(), NumElts);
9108 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
9111 /// \brief Target-specific dag combine xforms for ARMISD::BUILD_VECTOR.
9113 PerformARMBUILD_VECTORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
9114 // ARMISD::BUILD_VECTOR is introduced when legalizing ISD::BUILD_VECTOR.
9115 // At that time, we may have inserted bitcasts from integer to float.
9116 // If these bitcasts have survived DAGCombine, change the lowering of this
9117 // BUILD_VECTOR in something more vector friendly, i.e., that does not
9118 // force to use floating point types.
9120 // Make sure we can change the type of the vector.
9121 // This is possible iff:
9122 // 1. The vector is only used in a bitcast to a integer type. I.e.,
9123 // 1.1. Vector is used only once.
9124 // 1.2. Use is a bit convert to an integer type.
9125 // 2. The size of its operands are 32-bits (64-bits are not legal).
9126 EVT VT = N->getValueType(0);
9127 EVT EltVT = VT.getVectorElementType();
9129 // Check 1.1. and 2.
9130 if (EltVT.getSizeInBits() != 32 || !N->hasOneUse())
9133 // By construction, the input type must be float.
9134 assert(EltVT == MVT::f32 && "Unexpected type!");
9137 SDNode *Use = *N->use_begin();
9138 if (Use->getOpcode() != ISD::BITCAST ||
9139 Use->getValueType(0).isFloatingPoint())
9142 // Check profitability.
9143 // Model is, if more than half of the relevant operands are bitcast from
9144 // i32, turn the build_vector into a sequence of insert_vector_elt.
9145 // Relevant operands are everything that is not statically
9146 // (i.e., at compile time) bitcasted.
9147 unsigned NumOfBitCastedElts = 0;
9148 unsigned NumElts = VT.getVectorNumElements();
9149 unsigned NumOfRelevantElts = NumElts;
9150 for (unsigned Idx = 0; Idx < NumElts; ++Idx) {
9151 SDValue Elt = N->getOperand(Idx);
9152 if (Elt->getOpcode() == ISD::BITCAST) {
9153 // Assume only bit cast to i32 will go away.
9154 if (Elt->getOperand(0).getValueType() == MVT::i32)
9155 ++NumOfBitCastedElts;
9156 } else if (Elt.getOpcode() == ISD::UNDEF || isa<ConstantSDNode>(Elt))
9157 // Constants are statically casted, thus do not count them as
9158 // relevant operands.
9159 --NumOfRelevantElts;
9162 // Check if more than half of the elements require a non-free bitcast.
9163 if (NumOfBitCastedElts <= NumOfRelevantElts / 2)
9166 SelectionDAG &DAG = DCI.DAG;
9167 // Create the new vector type.
9168 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
9169 // Check if the type is legal.
9170 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9171 if (!TLI.isTypeLegal(VecVT))
9175 // ARMISD::BUILD_VECTOR E1, E2, ..., EN.
9176 // => BITCAST INSERT_VECTOR_ELT
9177 // (INSERT_VECTOR_ELT (...), (BITCAST EN-1), N-1),
9179 SDValue Vec = DAG.getUNDEF(VecVT);
9181 for (unsigned Idx = 0 ; Idx < NumElts; ++Idx) {
9182 SDValue V = N->getOperand(Idx);
9183 if (V.getOpcode() == ISD::UNDEF)
9185 if (V.getOpcode() == ISD::BITCAST &&
9186 V->getOperand(0).getValueType() == MVT::i32)
9187 // Fold obvious case.
9188 V = V.getOperand(0);
9190 V = DAG.getNode(ISD::BITCAST, SDLoc(V), MVT::i32, V);
9191 // Make the DAGCombiner fold the bitcasts.
9192 DCI.AddToWorklist(V.getNode());
9194 SDValue LaneIdx = DAG.getConstant(Idx, MVT::i32);
9195 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecVT, Vec, V, LaneIdx);
9197 Vec = DAG.getNode(ISD::BITCAST, dl, VT, Vec);
9198 // Make the DAGCombiner fold the bitcasts.
9199 DCI.AddToWorklist(Vec.getNode());
9203 /// PerformInsertEltCombine - Target-specific dag combine xforms for
9204 /// ISD::INSERT_VECTOR_ELT.
9205 static SDValue PerformInsertEltCombine(SDNode *N,
9206 TargetLowering::DAGCombinerInfo &DCI) {
9207 // Bitcast an i64 load inserted into a vector to f64.
9208 // Otherwise, the i64 value will be legalized to a pair of i32 values.
9209 EVT VT = N->getValueType(0);
9210 SDNode *Elt = N->getOperand(1).getNode();
9211 if (VT.getVectorElementType() != MVT::i64 ||
9212 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile())
9215 SelectionDAG &DAG = DCI.DAG;
9217 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
9218 VT.getVectorNumElements());
9219 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0));
9220 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1));
9221 // Make the DAGCombiner fold the bitcasts.
9222 DCI.AddToWorklist(Vec.getNode());
9223 DCI.AddToWorklist(V.getNode());
9224 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT,
9225 Vec, V, N->getOperand(2));
9226 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt);
9229 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
9230 /// ISD::VECTOR_SHUFFLE.
9231 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
9232 // The LLVM shufflevector instruction does not require the shuffle mask
9233 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
9234 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
9235 // operands do not match the mask length, they are extended by concatenating
9236 // them with undef vectors. That is probably the right thing for other
9237 // targets, but for NEON it is better to concatenate two double-register
9238 // size vector operands into a single quad-register size vector. Do that
9239 // transformation here:
9240 // shuffle(concat(v1, undef), concat(v2, undef)) ->
9241 // shuffle(concat(v1, v2), undef)
9242 SDValue Op0 = N->getOperand(0);
9243 SDValue Op1 = N->getOperand(1);
9244 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
9245 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
9246 Op0.getNumOperands() != 2 ||
9247 Op1.getNumOperands() != 2)
9249 SDValue Concat0Op1 = Op0.getOperand(1);
9250 SDValue Concat1Op1 = Op1.getOperand(1);
9251 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
9252 Concat1Op1.getOpcode() != ISD::UNDEF)
9254 // Skip the transformation if any of the types are illegal.
9255 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9256 EVT VT = N->getValueType(0);
9257 if (!TLI.isTypeLegal(VT) ||
9258 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
9259 !TLI.isTypeLegal(Concat1Op1.getValueType()))
9262 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,
9263 Op0.getOperand(0), Op1.getOperand(0));
9264 // Translate the shuffle mask.
9265 SmallVector<int, 16> NewMask;
9266 unsigned NumElts = VT.getVectorNumElements();
9267 unsigned HalfElts = NumElts/2;
9268 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
9269 for (unsigned n = 0; n < NumElts; ++n) {
9270 int MaskElt = SVN->getMaskElt(n);
9272 if (MaskElt < (int)HalfElts)
9274 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
9275 NewElt = HalfElts + MaskElt - NumElts;
9276 NewMask.push_back(NewElt);
9278 return DAG.getVectorShuffle(VT, SDLoc(N), NewConcat,
9279 DAG.getUNDEF(VT), NewMask.data());
9282 /// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP and
9283 /// NEON load/store intrinsics to merge base address updates.
9284 static SDValue CombineBaseUpdate(SDNode *N,
9285 TargetLowering::DAGCombinerInfo &DCI) {
9286 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
9289 SelectionDAG &DAG = DCI.DAG;
9290 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
9291 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
9292 unsigned AddrOpIdx = (isIntrinsic ? 2 : 1);
9293 SDValue Addr = N->getOperand(AddrOpIdx);
9295 // Search for a use of the address operand that is an increment.
9296 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
9297 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
9299 if (User->getOpcode() != ISD::ADD ||
9300 UI.getUse().getResNo() != Addr.getResNo())
9303 // Check that the add is independent of the load/store. Otherwise, folding
9304 // it would create a cycle.
9305 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
9308 // Find the new opcode for the updating load/store.
9310 bool isLaneOp = false;
9311 unsigned NewOpc = 0;
9312 unsigned NumVecs = 0;
9314 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
9316 default: llvm_unreachable("unexpected intrinsic for Neon base update");
9317 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
9319 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
9321 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
9323 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
9325 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
9326 NumVecs = 2; isLaneOp = true; break;
9327 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
9328 NumVecs = 3; isLaneOp = true; break;
9329 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
9330 NumVecs = 4; isLaneOp = true; break;
9331 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD;
9332 NumVecs = 1; isLoad = false; break;
9333 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD;
9334 NumVecs = 2; isLoad = false; break;
9335 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD;
9336 NumVecs = 3; isLoad = false; break;
9337 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD;
9338 NumVecs = 4; isLoad = false; break;
9339 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
9340 NumVecs = 2; isLoad = false; isLaneOp = true; break;
9341 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
9342 NumVecs = 3; isLoad = false; isLaneOp = true; break;
9343 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
9344 NumVecs = 4; isLoad = false; isLaneOp = true; break;
9348 switch (N->getOpcode()) {
9349 default: llvm_unreachable("unexpected opcode for Neon base update");
9350 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
9351 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
9352 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
9356 // Find the size of memory referenced by the load/store.
9359 VecTy = N->getValueType(0);
9361 VecTy = N->getOperand(AddrOpIdx+1).getValueType();
9362 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
9364 NumBytes /= VecTy.getVectorNumElements();
9366 // If the increment is a constant, it must match the memory ref size.
9367 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
9368 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
9369 uint64_t IncVal = CInc->getZExtValue();
9370 if (IncVal != NumBytes)
9372 } else if (NumBytes >= 3 * 16) {
9373 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two
9374 // separate instructions that make it harder to use a non-constant update.
9378 // Create the new updating load/store node.
9380 unsigned NumResultVecs = (isLoad ? NumVecs : 0);
9382 for (n = 0; n < NumResultVecs; ++n)
9384 Tys[n++] = MVT::i32;
9385 Tys[n] = MVT::Other;
9386 SDVTList SDTys = DAG.getVTList(Tys, NumResultVecs+2);
9387 SmallVector<SDValue, 8> Ops;
9388 Ops.push_back(N->getOperand(0)); // incoming chain
9389 Ops.push_back(N->getOperand(AddrOpIdx));
9391 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) {
9392 Ops.push_back(N->getOperand(i));
9394 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
9395 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys,
9396 Ops.data(), Ops.size(),
9397 MemInt->getMemoryVT(),
9398 MemInt->getMemOperand());
9401 std::vector<SDValue> NewResults;
9402 for (unsigned i = 0; i < NumResultVecs; ++i) {
9403 NewResults.push_back(SDValue(UpdN.getNode(), i));
9405 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain
9406 DCI.CombineTo(N, NewResults);
9407 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
9414 /// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a
9415 /// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
9416 /// are also VDUPLANEs. If so, combine them to a vldN-dup operation and
9418 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
9419 SelectionDAG &DAG = DCI.DAG;
9420 EVT VT = N->getValueType(0);
9421 // vldN-dup instructions only support 64-bit vectors for N > 1.
9422 if (!VT.is64BitVector())
9425 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
9426 SDNode *VLD = N->getOperand(0).getNode();
9427 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
9429 unsigned NumVecs = 0;
9430 unsigned NewOpc = 0;
9431 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
9432 if (IntNo == Intrinsic::arm_neon_vld2lane) {
9434 NewOpc = ARMISD::VLD2DUP;
9435 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
9437 NewOpc = ARMISD::VLD3DUP;
9438 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
9440 NewOpc = ARMISD::VLD4DUP;
9445 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
9446 // numbers match the load.
9447 unsigned VLDLaneNo =
9448 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue();
9449 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
9451 // Ignore uses of the chain result.
9452 if (UI.getUse().getResNo() == NumVecs)
9455 if (User->getOpcode() != ARMISD::VDUPLANE ||
9456 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
9460 // Create the vldN-dup node.
9463 for (n = 0; n < NumVecs; ++n)
9465 Tys[n] = MVT::Other;
9466 SDVTList SDTys = DAG.getVTList(Tys, NumVecs+1);
9467 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
9468 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
9469 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, SDLoc(VLD), SDTys,
9470 Ops, 2, VLDMemInt->getMemoryVT(),
9471 VLDMemInt->getMemOperand());
9474 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
9476 unsigned ResNo = UI.getUse().getResNo();
9477 // Ignore uses of the chain result.
9478 if (ResNo == NumVecs)
9481 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
9484 // Now the vldN-lane intrinsic is dead except for its chain result.
9485 // Update uses of the chain.
9486 std::vector<SDValue> VLDDupResults;
9487 for (unsigned n = 0; n < NumVecs; ++n)
9488 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
9489 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
9490 DCI.CombineTo(VLD, VLDDupResults);
9495 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
9496 /// ARMISD::VDUPLANE.
9497 static SDValue PerformVDUPLANECombine(SDNode *N,
9498 TargetLowering::DAGCombinerInfo &DCI) {
9499 SDValue Op = N->getOperand(0);
9501 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
9502 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
9503 if (CombineVLDDUP(N, DCI))
9504 return SDValue(N, 0);
9506 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
9507 // redundant. Ignore bit_converts for now; element sizes are checked below.
9508 while (Op.getOpcode() == ISD::BITCAST)
9509 Op = Op.getOperand(0);
9510 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
9513 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
9514 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
9515 // The canonical VMOV for a zero vector uses a 32-bit element size.
9516 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9518 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
9520 EVT VT = N->getValueType(0);
9521 if (EltSize > VT.getVectorElementType().getSizeInBits())
9524 return DCI.DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
9527 // isConstVecPow2 - Return true if each vector element is a power of 2, all
9528 // elements are the same constant, C, and Log2(C) ranges from 1 to 32.
9529 static bool isConstVecPow2(SDValue ConstVec, bool isSigned, uint64_t &C)
9533 for (unsigned I = 0, E = ConstVec.getValueType().getVectorNumElements();
9535 ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(ConstVec.getOperand(I));
9540 APFloat APF = C->getValueAPF();
9541 if (APF.convertToInteger(&cN, 64, isSigned, APFloat::rmTowardZero, &isExact)
9542 != APFloat::opOK || !isExact)
9545 c0 = (I == 0) ? cN : c0;
9546 if (!isPowerOf2_64(cN) || c0 != cN || Log2_64(c0) < 1 || Log2_64(c0) > 32)
9553 /// PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD)
9554 /// can replace combinations of VMUL and VCVT (floating-point to integer)
9555 /// when the VMUL has a constant operand that is a power of 2.
9557 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
9558 /// vmul.f32 d16, d17, d16
9559 /// vcvt.s32.f32 d16, d16
9561 /// vcvt.s32.f32 d16, d16, #3
9562 static SDValue PerformVCVTCombine(SDNode *N,
9563 TargetLowering::DAGCombinerInfo &DCI,
9564 const ARMSubtarget *Subtarget) {
9565 SelectionDAG &DAG = DCI.DAG;
9566 SDValue Op = N->getOperand(0);
9568 if (!Subtarget->hasNEON() || !Op.getValueType().isVector() ||
9569 Op.getOpcode() != ISD::FMUL)
9573 SDValue N0 = Op->getOperand(0);
9574 SDValue ConstVec = Op->getOperand(1);
9575 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT;
9577 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
9578 !isConstVecPow2(ConstVec, isSigned, C))
9581 MVT FloatTy = Op.getSimpleValueType().getVectorElementType();
9582 MVT IntTy = N->getSimpleValueType(0).getVectorElementType();
9583 if (FloatTy.getSizeInBits() != 32 || IntTy.getSizeInBits() > 32) {
9584 // These instructions only exist converting from f32 to i32. We can handle
9585 // smaller integers by generating an extra truncate, but larger ones would
9590 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs :
9591 Intrinsic::arm_neon_vcvtfp2fxu;
9592 unsigned NumLanes = Op.getValueType().getVectorNumElements();
9593 SDValue FixConv = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N),
9594 NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,
9595 DAG.getConstant(IntrinsicOpcode, MVT::i32), N0,
9596 DAG.getConstant(Log2_64(C), MVT::i32));
9598 if (IntTy.getSizeInBits() < FloatTy.getSizeInBits())
9599 FixConv = DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), FixConv);
9604 /// PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD)
9605 /// can replace combinations of VCVT (integer to floating-point) and VDIV
9606 /// when the VDIV has a constant operand that is a power of 2.
9608 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
9609 /// vcvt.f32.s32 d16, d16
9610 /// vdiv.f32 d16, d17, d16
9612 /// vcvt.f32.s32 d16, d16, #3
9613 static SDValue PerformVDIVCombine(SDNode *N,
9614 TargetLowering::DAGCombinerInfo &DCI,
9615 const ARMSubtarget *Subtarget) {
9616 SelectionDAG &DAG = DCI.DAG;
9617 SDValue Op = N->getOperand(0);
9618 unsigned OpOpcode = Op.getNode()->getOpcode();
9620 if (!Subtarget->hasNEON() || !N->getValueType(0).isVector() ||
9621 (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP))
9625 SDValue ConstVec = N->getOperand(1);
9626 bool isSigned = OpOpcode == ISD::SINT_TO_FP;
9628 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
9629 !isConstVecPow2(ConstVec, isSigned, C))
9632 MVT FloatTy = N->getSimpleValueType(0).getVectorElementType();
9633 MVT IntTy = Op.getOperand(0).getSimpleValueType().getVectorElementType();
9634 if (FloatTy.getSizeInBits() != 32 || IntTy.getSizeInBits() > 32) {
9635 // These instructions only exist converting from i32 to f32. We can handle
9636 // smaller integers by generating an extra extend, but larger ones would
9641 SDValue ConvInput = Op.getOperand(0);
9642 unsigned NumLanes = Op.getValueType().getVectorNumElements();
9643 if (IntTy.getSizeInBits() < FloatTy.getSizeInBits())
9644 ConvInput = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
9645 SDLoc(N), NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,
9648 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp :
9649 Intrinsic::arm_neon_vcvtfxu2fp;
9650 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N),
9652 DAG.getConstant(IntrinsicOpcode, MVT::i32),
9653 ConvInput, DAG.getConstant(Log2_64(C), MVT::i32));
9656 /// Getvshiftimm - Check if this is a valid build_vector for the immediate
9657 /// operand of a vector shift operation, where all the elements of the
9658 /// build_vector must have the same constant integer value.
9659 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
9660 // Ignore bit_converts.
9661 while (Op.getOpcode() == ISD::BITCAST)
9662 Op = Op.getOperand(0);
9663 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
9664 APInt SplatBits, SplatUndef;
9665 unsigned SplatBitSize;
9667 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
9668 HasAnyUndefs, ElementBits) ||
9669 SplatBitSize > ElementBits)
9671 Cnt = SplatBits.getSExtValue();
9675 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
9676 /// operand of a vector shift left operation. That value must be in the range:
9677 /// 0 <= Value < ElementBits for a left shift; or
9678 /// 0 <= Value <= ElementBits for a long left shift.
9679 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
9680 assert(VT.isVector() && "vector shift count is not a vector type");
9681 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
9682 if (! getVShiftImm(Op, ElementBits, Cnt))
9684 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
9687 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
9688 /// operand of a vector shift right operation. For a shift opcode, the value
9689 /// is positive, but for an intrinsic the value count must be negative. The
9690 /// absolute value must be in the range:
9691 /// 1 <= |Value| <= ElementBits for a right shift; or
9692 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
9693 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
9695 assert(VT.isVector() && "vector shift count is not a vector type");
9696 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
9697 if (! getVShiftImm(Op, ElementBits, Cnt))
9701 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
9704 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
9705 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
9706 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
9709 // Don't do anything for most intrinsics.
9712 // Vector shifts: check for immediate versions and lower them.
9713 // Note: This is done during DAG combining instead of DAG legalizing because
9714 // the build_vectors for 64-bit vector element shift counts are generally
9715 // not legal, and it is hard to see their values after they get legalized to
9716 // loads from a constant pool.
9717 case Intrinsic::arm_neon_vshifts:
9718 case Intrinsic::arm_neon_vshiftu:
9719 case Intrinsic::arm_neon_vshiftls:
9720 case Intrinsic::arm_neon_vshiftlu:
9721 case Intrinsic::arm_neon_vshiftn:
9722 case Intrinsic::arm_neon_vrshifts:
9723 case Intrinsic::arm_neon_vrshiftu:
9724 case Intrinsic::arm_neon_vrshiftn:
9725 case Intrinsic::arm_neon_vqshifts:
9726 case Intrinsic::arm_neon_vqshiftu:
9727 case Intrinsic::arm_neon_vqshiftsu:
9728 case Intrinsic::arm_neon_vqshiftns:
9729 case Intrinsic::arm_neon_vqshiftnu:
9730 case Intrinsic::arm_neon_vqshiftnsu:
9731 case Intrinsic::arm_neon_vqrshiftns:
9732 case Intrinsic::arm_neon_vqrshiftnu:
9733 case Intrinsic::arm_neon_vqrshiftnsu: {
9734 EVT VT = N->getOperand(1).getValueType();
9736 unsigned VShiftOpc = 0;
9739 case Intrinsic::arm_neon_vshifts:
9740 case Intrinsic::arm_neon_vshiftu:
9741 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
9742 VShiftOpc = ARMISD::VSHL;
9745 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
9746 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
9747 ARMISD::VSHRs : ARMISD::VSHRu);
9752 case Intrinsic::arm_neon_vshiftls:
9753 case Intrinsic::arm_neon_vshiftlu:
9754 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
9756 llvm_unreachable("invalid shift count for vshll intrinsic");
9758 case Intrinsic::arm_neon_vrshifts:
9759 case Intrinsic::arm_neon_vrshiftu:
9760 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
9764 case Intrinsic::arm_neon_vqshifts:
9765 case Intrinsic::arm_neon_vqshiftu:
9766 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
9770 case Intrinsic::arm_neon_vqshiftsu:
9771 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
9773 llvm_unreachable("invalid shift count for vqshlu intrinsic");
9775 case Intrinsic::arm_neon_vshiftn:
9776 case Intrinsic::arm_neon_vrshiftn:
9777 case Intrinsic::arm_neon_vqshiftns:
9778 case Intrinsic::arm_neon_vqshiftnu:
9779 case Intrinsic::arm_neon_vqshiftnsu:
9780 case Intrinsic::arm_neon_vqrshiftns:
9781 case Intrinsic::arm_neon_vqrshiftnu:
9782 case Intrinsic::arm_neon_vqrshiftnsu:
9783 // Narrowing shifts require an immediate right shift.
9784 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
9786 llvm_unreachable("invalid shift count for narrowing vector shift "
9790 llvm_unreachable("unhandled vector shift");
9794 case Intrinsic::arm_neon_vshifts:
9795 case Intrinsic::arm_neon_vshiftu:
9796 // Opcode already set above.
9798 case Intrinsic::arm_neon_vshiftls:
9799 case Intrinsic::arm_neon_vshiftlu:
9800 if (Cnt == VT.getVectorElementType().getSizeInBits())
9801 VShiftOpc = ARMISD::VSHLLi;
9803 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
9804 ARMISD::VSHLLs : ARMISD::VSHLLu);
9806 case Intrinsic::arm_neon_vshiftn:
9807 VShiftOpc = ARMISD::VSHRN; break;
9808 case Intrinsic::arm_neon_vrshifts:
9809 VShiftOpc = ARMISD::VRSHRs; break;
9810 case Intrinsic::arm_neon_vrshiftu:
9811 VShiftOpc = ARMISD::VRSHRu; break;
9812 case Intrinsic::arm_neon_vrshiftn:
9813 VShiftOpc = ARMISD::VRSHRN; break;
9814 case Intrinsic::arm_neon_vqshifts:
9815 VShiftOpc = ARMISD::VQSHLs; break;
9816 case Intrinsic::arm_neon_vqshiftu:
9817 VShiftOpc = ARMISD::VQSHLu; break;
9818 case Intrinsic::arm_neon_vqshiftsu:
9819 VShiftOpc = ARMISD::VQSHLsu; break;
9820 case Intrinsic::arm_neon_vqshiftns:
9821 VShiftOpc = ARMISD::VQSHRNs; break;
9822 case Intrinsic::arm_neon_vqshiftnu:
9823 VShiftOpc = ARMISD::VQSHRNu; break;
9824 case Intrinsic::arm_neon_vqshiftnsu:
9825 VShiftOpc = ARMISD::VQSHRNsu; break;
9826 case Intrinsic::arm_neon_vqrshiftns:
9827 VShiftOpc = ARMISD::VQRSHRNs; break;
9828 case Intrinsic::arm_neon_vqrshiftnu:
9829 VShiftOpc = ARMISD::VQRSHRNu; break;
9830 case Intrinsic::arm_neon_vqrshiftnsu:
9831 VShiftOpc = ARMISD::VQRSHRNsu; break;
9834 return DAG.getNode(VShiftOpc, SDLoc(N), N->getValueType(0),
9835 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
9838 case Intrinsic::arm_neon_vshiftins: {
9839 EVT VT = N->getOperand(1).getValueType();
9841 unsigned VShiftOpc = 0;
9843 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
9844 VShiftOpc = ARMISD::VSLI;
9845 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
9846 VShiftOpc = ARMISD::VSRI;
9848 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
9851 return DAG.getNode(VShiftOpc, SDLoc(N), N->getValueType(0),
9852 N->getOperand(1), N->getOperand(2),
9853 DAG.getConstant(Cnt, MVT::i32));
9856 case Intrinsic::arm_neon_vqrshifts:
9857 case Intrinsic::arm_neon_vqrshiftu:
9858 // No immediate versions of these to check for.
9865 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
9866 /// lowers them. As with the vector shift intrinsics, this is done during DAG
9867 /// combining instead of DAG legalizing because the build_vectors for 64-bit
9868 /// vector element shift counts are generally not legal, and it is hard to see
9869 /// their values after they get legalized to loads from a constant pool.
9870 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
9871 const ARMSubtarget *ST) {
9872 EVT VT = N->getValueType(0);
9873 if (N->getOpcode() == ISD::SRL && VT == MVT::i32 && ST->hasV6Ops()) {
9874 // Canonicalize (srl (bswap x), 16) to (rotr (bswap x), 16) if the high
9875 // 16-bits of x is zero. This optimizes rev + lsr 16 to rev16.
9876 SDValue N1 = N->getOperand(1);
9877 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
9878 SDValue N0 = N->getOperand(0);
9879 if (C->getZExtValue() == 16 && N0.getOpcode() == ISD::BSWAP &&
9880 DAG.MaskedValueIsZero(N0.getOperand(0),
9881 APInt::getHighBitsSet(32, 16)))
9882 return DAG.getNode(ISD::ROTR, SDLoc(N), VT, N0, N1);
9886 // Nothing to be done for scalar shifts.
9887 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9888 if (!VT.isVector() || !TLI.isTypeLegal(VT))
9891 assert(ST->hasNEON() && "unexpected vector shift");
9894 switch (N->getOpcode()) {
9895 default: llvm_unreachable("unexpected shift opcode");
9898 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
9899 return DAG.getNode(ARMISD::VSHL, SDLoc(N), VT, N->getOperand(0),
9900 DAG.getConstant(Cnt, MVT::i32));
9905 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
9906 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
9907 ARMISD::VSHRs : ARMISD::VSHRu);
9908 return DAG.getNode(VShiftOpc, SDLoc(N), VT, N->getOperand(0),
9909 DAG.getConstant(Cnt, MVT::i32));
9915 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
9916 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
9917 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
9918 const ARMSubtarget *ST) {
9919 SDValue N0 = N->getOperand(0);
9921 // Check for sign- and zero-extensions of vector extract operations of 8-
9922 // and 16-bit vector elements. NEON supports these directly. They are
9923 // handled during DAG combining because type legalization will promote them
9924 // to 32-bit types and it is messy to recognize the operations after that.
9925 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
9926 SDValue Vec = N0.getOperand(0);
9927 SDValue Lane = N0.getOperand(1);
9928 EVT VT = N->getValueType(0);
9929 EVT EltVT = N0.getValueType();
9930 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9932 if (VT == MVT::i32 &&
9933 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
9934 TLI.isTypeLegal(Vec.getValueType()) &&
9935 isa<ConstantSDNode>(Lane)) {
9938 switch (N->getOpcode()) {
9939 default: llvm_unreachable("unexpected opcode");
9940 case ISD::SIGN_EXTEND:
9941 Opc = ARMISD::VGETLANEs;
9943 case ISD::ZERO_EXTEND:
9944 case ISD::ANY_EXTEND:
9945 Opc = ARMISD::VGETLANEu;
9948 return DAG.getNode(Opc, SDLoc(N), VT, Vec, Lane);
9955 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
9956 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
9957 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
9958 const ARMSubtarget *ST) {
9959 // If the target supports NEON, try to use vmax/vmin instructions for f32
9960 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
9961 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
9962 // a NaN; only do the transformation when it matches that behavior.
9964 // For now only do this when using NEON for FP operations; if using VFP, it
9965 // is not obvious that the benefit outweighs the cost of switching to the
9967 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
9968 N->getValueType(0) != MVT::f32)
9971 SDValue CondLHS = N->getOperand(0);
9972 SDValue CondRHS = N->getOperand(1);
9973 SDValue LHS = N->getOperand(2);
9974 SDValue RHS = N->getOperand(3);
9975 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
9977 unsigned Opcode = 0;
9979 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
9980 IsReversed = false; // x CC y ? x : y
9981 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
9982 IsReversed = true ; // x CC y ? y : x
9996 // If LHS is NaN, an ordered comparison will be false and the result will
9997 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
9998 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
9999 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
10000 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
10002 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
10003 // will return -0, so vmin can only be used for unsafe math or if one of
10004 // the operands is known to be nonzero.
10005 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
10006 !DAG.getTarget().Options.UnsafeFPMath &&
10007 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
10009 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
10018 // If LHS is NaN, an ordered comparison will be false and the result will
10019 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
10020 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
10021 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
10022 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
10024 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
10025 // will return +0, so vmax can only be used for unsafe math or if one of
10026 // the operands is known to be nonzero.
10027 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
10028 !DAG.getTarget().Options.UnsafeFPMath &&
10029 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
10031 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
10037 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), LHS, RHS);
10040 /// PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.
10042 ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
10043 SDValue Cmp = N->getOperand(4);
10044 if (Cmp.getOpcode() != ARMISD::CMPZ)
10045 // Only looking at EQ and NE cases.
10048 EVT VT = N->getValueType(0);
10050 SDValue LHS = Cmp.getOperand(0);
10051 SDValue RHS = Cmp.getOperand(1);
10052 SDValue FalseVal = N->getOperand(0);
10053 SDValue TrueVal = N->getOperand(1);
10054 SDValue ARMcc = N->getOperand(2);
10055 ARMCC::CondCodes CC =
10056 (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue();
10074 /// FIXME: Turn this into a target neutral optimization?
10076 if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) {
10077 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc,
10078 N->getOperand(3), Cmp);
10079 } else if (CC == ARMCC::EQ && TrueVal == RHS) {
10081 SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl);
10082 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc,
10083 N->getOperand(3), NewCmp);
10086 if (Res.getNode()) {
10087 APInt KnownZero, KnownOne;
10088 DAG.ComputeMaskedBits(SDValue(N,0), KnownZero, KnownOne);
10089 // Capture demanded bits information that would be otherwise lost.
10090 if (KnownZero == 0xfffffffe)
10091 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
10092 DAG.getValueType(MVT::i1));
10093 else if (KnownZero == 0xffffff00)
10094 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
10095 DAG.getValueType(MVT::i8));
10096 else if (KnownZero == 0xffff0000)
10097 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
10098 DAG.getValueType(MVT::i16));
10104 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
10105 DAGCombinerInfo &DCI) const {
10106 switch (N->getOpcode()) {
10108 case ISD::ADDC: return PerformADDCCombine(N, DCI, Subtarget);
10109 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget);
10110 case ISD::SUB: return PerformSUBCombine(N, DCI);
10111 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
10112 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
10113 case ISD::XOR: return PerformXORCombine(N, DCI, Subtarget);
10114 case ISD::AND: return PerformANDCombine(N, DCI, Subtarget);
10115 case ARMISD::BFI: return PerformBFICombine(N, DCI);
10116 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
10117 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
10118 case ISD::STORE: return PerformSTORECombine(N, DCI);
10119 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI);
10120 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
10121 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
10122 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
10123 case ISD::FP_TO_SINT:
10124 case ISD::FP_TO_UINT: return PerformVCVTCombine(N, DCI, Subtarget);
10125 case ISD::FDIV: return PerformVDIVCombine(N, DCI, Subtarget);
10126 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
10129 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
10130 case ISD::SIGN_EXTEND:
10131 case ISD::ZERO_EXTEND:
10132 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
10133 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
10134 case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG);
10135 case ARMISD::VLD2DUP:
10136 case ARMISD::VLD3DUP:
10137 case ARMISD::VLD4DUP:
10138 return CombineBaseUpdate(N, DCI);
10139 case ARMISD::BUILD_VECTOR:
10140 return PerformARMBUILD_VECTORCombine(N, DCI);
10141 case ISD::INTRINSIC_VOID:
10142 case ISD::INTRINSIC_W_CHAIN:
10143 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
10144 case Intrinsic::arm_neon_vld1:
10145 case Intrinsic::arm_neon_vld2:
10146 case Intrinsic::arm_neon_vld3:
10147 case Intrinsic::arm_neon_vld4:
10148 case Intrinsic::arm_neon_vld2lane:
10149 case Intrinsic::arm_neon_vld3lane:
10150 case Intrinsic::arm_neon_vld4lane:
10151 case Intrinsic::arm_neon_vst1:
10152 case Intrinsic::arm_neon_vst2:
10153 case Intrinsic::arm_neon_vst3:
10154 case Intrinsic::arm_neon_vst4:
10155 case Intrinsic::arm_neon_vst2lane:
10156 case Intrinsic::arm_neon_vst3lane:
10157 case Intrinsic::arm_neon_vst4lane:
10158 return CombineBaseUpdate(N, DCI);
10166 bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc,
10168 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);
10171 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
10172 // The AllowsUnaliged flag models the SCTLR.A setting in ARM cpus
10173 bool AllowsUnaligned = Subtarget->allowsUnalignedMem();
10175 switch (VT.getSimpleVT().SimpleTy) {
10181 // Unaligned access can use (for example) LRDB, LRDH, LDR
10182 if (AllowsUnaligned) {
10184 *Fast = Subtarget->hasV7Ops();
10191 // For any little-endian targets with neon, we can support unaligned ld/st
10192 // of D and Q (e.g. {D0,D1}) registers by using vld1.i8/vst1.i8.
10193 // A big-endian target may also explictly support unaligned accesses
10194 if (Subtarget->hasNEON() && (AllowsUnaligned || isLittleEndian())) {
10204 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
10205 unsigned AlignCheck) {
10206 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
10207 (DstAlign == 0 || DstAlign % AlignCheck == 0));
10210 EVT ARMTargetLowering::getOptimalMemOpType(uint64_t Size,
10211 unsigned DstAlign, unsigned SrcAlign,
10212 bool IsMemset, bool ZeroMemset,
10214 MachineFunction &MF) const {
10215 const Function *F = MF.getFunction();
10217 // See if we can use NEON instructions for this...
10218 if ((!IsMemset || ZeroMemset) &&
10219 Subtarget->hasNEON() &&
10220 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
10221 Attribute::NoImplicitFloat)) {
10224 (memOpAlign(SrcAlign, DstAlign, 16) ||
10225 (allowsUnalignedMemoryAccesses(MVT::v2f64, &Fast) && Fast))) {
10227 } else if (Size >= 8 &&
10228 (memOpAlign(SrcAlign, DstAlign, 8) ||
10229 (allowsUnalignedMemoryAccesses(MVT::f64, &Fast) && Fast))) {
10234 // Lowering to i32/i16 if the size permits.
10237 else if (Size >= 2)
10240 // Let the target-independent logic figure it out.
10244 bool ARMTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
10245 if (Val.getOpcode() != ISD::LOAD)
10248 EVT VT1 = Val.getValueType();
10249 if (!VT1.isSimple() || !VT1.isInteger() ||
10250 !VT2.isSimple() || !VT2.isInteger())
10253 switch (VT1.getSimpleVT().SimpleTy) {
10258 // 8-bit and 16-bit loads implicitly zero-extend to 32-bits.
10265 bool ARMTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
10266 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
10269 if (!isTypeLegal(EVT::getEVT(Ty1)))
10272 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
10274 // Assuming the caller doesn't have a zeroext or signext return parameter,
10275 // truncation all the way down to i1 is valid.
10280 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
10284 unsigned Scale = 1;
10285 switch (VT.getSimpleVT().SimpleTy) {
10286 default: return false;
10301 if ((V & (Scale - 1)) != 0)
10304 return V == (V & ((1LL << 5) - 1));
10307 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
10308 const ARMSubtarget *Subtarget) {
10309 bool isNeg = false;
10315 switch (VT.getSimpleVT().SimpleTy) {
10316 default: return false;
10321 // + imm12 or - imm8
10323 return V == (V & ((1LL << 8) - 1));
10324 return V == (V & ((1LL << 12) - 1));
10327 // Same as ARM mode. FIXME: NEON?
10328 if (!Subtarget->hasVFP2())
10333 return V == (V & ((1LL << 8) - 1));
10337 /// isLegalAddressImmediate - Return true if the integer value can be used
10338 /// as the offset of the target addressing mode for load / store of the
10340 static bool isLegalAddressImmediate(int64_t V, EVT VT,
10341 const ARMSubtarget *Subtarget) {
10345 if (!VT.isSimple())
10348 if (Subtarget->isThumb1Only())
10349 return isLegalT1AddressImmediate(V, VT);
10350 else if (Subtarget->isThumb2())
10351 return isLegalT2AddressImmediate(V, VT, Subtarget);
10356 switch (VT.getSimpleVT().SimpleTy) {
10357 default: return false;
10362 return V == (V & ((1LL << 12) - 1));
10365 return V == (V & ((1LL << 8) - 1));
10368 if (!Subtarget->hasVFP2()) // FIXME: NEON?
10373 return V == (V & ((1LL << 8) - 1));
10377 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
10379 int Scale = AM.Scale;
10383 switch (VT.getSimpleVT().SimpleTy) {
10384 default: return false;
10392 Scale = Scale & ~1;
10393 return Scale == 2 || Scale == 4 || Scale == 8;
10396 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
10400 // Note, we allow "void" uses (basically, uses that aren't loads or
10401 // stores), because arm allows folding a scale into many arithmetic
10402 // operations. This should be made more precise and revisited later.
10404 // Allow r << imm, but the imm has to be a multiple of two.
10405 if (Scale & 1) return false;
10406 return isPowerOf2_32(Scale);
10410 /// isLegalAddressingMode - Return true if the addressing mode represented
10411 /// by AM is legal for this target, for a load/store of the specified type.
10412 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
10414 EVT VT = getValueType(Ty, true);
10415 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
10418 // Can never fold addr of global into load/store.
10422 switch (AM.Scale) {
10423 case 0: // no scale reg, must be "r+i" or "r", or "i".
10426 if (Subtarget->isThumb1Only())
10430 // ARM doesn't support any R+R*scale+imm addr modes.
10434 if (!VT.isSimple())
10437 if (Subtarget->isThumb2())
10438 return isLegalT2ScaledAddressingMode(AM, VT);
10440 int Scale = AM.Scale;
10441 switch (VT.getSimpleVT().SimpleTy) {
10442 default: return false;
10446 if (Scale < 0) Scale = -Scale;
10450 return isPowerOf2_32(Scale & ~1);
10454 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
10459 // Note, we allow "void" uses (basically, uses that aren't loads or
10460 // stores), because arm allows folding a scale into many arithmetic
10461 // operations. This should be made more precise and revisited later.
10463 // Allow r << imm, but the imm has to be a multiple of two.
10464 if (Scale & 1) return false;
10465 return isPowerOf2_32(Scale);
10471 /// isLegalICmpImmediate - Return true if the specified immediate is legal
10472 /// icmp immediate, that is the target has icmp instructions which can compare
10473 /// a register against the immediate without having to materialize the
10474 /// immediate into a register.
10475 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
10476 // Thumb2 and ARM modes can use cmn for negative immediates.
10477 if (!Subtarget->isThumb())
10478 return ARM_AM::getSOImmVal(llvm::abs64(Imm)) != -1;
10479 if (Subtarget->isThumb2())
10480 return ARM_AM::getT2SOImmVal(llvm::abs64(Imm)) != -1;
10481 // Thumb1 doesn't have cmn, and only 8-bit immediates.
10482 return Imm >= 0 && Imm <= 255;
10485 /// isLegalAddImmediate - Return true if the specified immediate is a legal add
10486 /// *or sub* immediate, that is the target has add or sub instructions which can
10487 /// add a register with the immediate without having to materialize the
10488 /// immediate into a register.
10489 bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const {
10490 // Same encoding for add/sub, just flip the sign.
10491 int64_t AbsImm = llvm::abs64(Imm);
10492 if (!Subtarget->isThumb())
10493 return ARM_AM::getSOImmVal(AbsImm) != -1;
10494 if (Subtarget->isThumb2())
10495 return ARM_AM::getT2SOImmVal(AbsImm) != -1;
10496 // Thumb1 only has 8-bit unsigned immediate.
10497 return AbsImm >= 0 && AbsImm <= 255;
10500 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
10501 bool isSEXTLoad, SDValue &Base,
10502 SDValue &Offset, bool &isInc,
10503 SelectionDAG &DAG) {
10504 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
10507 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
10508 // AddressingMode 3
10509 Base = Ptr->getOperand(0);
10510 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
10511 int RHSC = (int)RHS->getZExtValue();
10512 if (RHSC < 0 && RHSC > -256) {
10513 assert(Ptr->getOpcode() == ISD::ADD);
10515 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
10519 isInc = (Ptr->getOpcode() == ISD::ADD);
10520 Offset = Ptr->getOperand(1);
10522 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
10523 // AddressingMode 2
10524 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
10525 int RHSC = (int)RHS->getZExtValue();
10526 if (RHSC < 0 && RHSC > -0x1000) {
10527 assert(Ptr->getOpcode() == ISD::ADD);
10529 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
10530 Base = Ptr->getOperand(0);
10535 if (Ptr->getOpcode() == ISD::ADD) {
10537 ARM_AM::ShiftOpc ShOpcVal=
10538 ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode());
10539 if (ShOpcVal != ARM_AM::no_shift) {
10540 Base = Ptr->getOperand(1);
10541 Offset = Ptr->getOperand(0);
10543 Base = Ptr->getOperand(0);
10544 Offset = Ptr->getOperand(1);
10549 isInc = (Ptr->getOpcode() == ISD::ADD);
10550 Base = Ptr->getOperand(0);
10551 Offset = Ptr->getOperand(1);
10555 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
10559 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
10560 bool isSEXTLoad, SDValue &Base,
10561 SDValue &Offset, bool &isInc,
10562 SelectionDAG &DAG) {
10563 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
10566 Base = Ptr->getOperand(0);
10567 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
10568 int RHSC = (int)RHS->getZExtValue();
10569 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
10570 assert(Ptr->getOpcode() == ISD::ADD);
10572 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
10574 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
10575 isInc = Ptr->getOpcode() == ISD::ADD;
10576 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
10584 /// getPreIndexedAddressParts - returns true by value, base pointer and
10585 /// offset pointer and addressing mode by reference if the node's address
10586 /// can be legally represented as pre-indexed load / store address.
10588 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
10590 ISD::MemIndexedMode &AM,
10591 SelectionDAG &DAG) const {
10592 if (Subtarget->isThumb1Only())
10597 bool isSEXTLoad = false;
10598 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
10599 Ptr = LD->getBasePtr();
10600 VT = LD->getMemoryVT();
10601 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
10602 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
10603 Ptr = ST->getBasePtr();
10604 VT = ST->getMemoryVT();
10609 bool isLegal = false;
10610 if (Subtarget->isThumb2())
10611 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
10612 Offset, isInc, DAG);
10614 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
10615 Offset, isInc, DAG);
10619 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
10623 /// getPostIndexedAddressParts - returns true by value, base pointer and
10624 /// offset pointer and addressing mode by reference if this node can be
10625 /// combined with a load / store to form a post-indexed load / store.
10626 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
10629 ISD::MemIndexedMode &AM,
10630 SelectionDAG &DAG) const {
10631 if (Subtarget->isThumb1Only())
10636 bool isSEXTLoad = false;
10637 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
10638 VT = LD->getMemoryVT();
10639 Ptr = LD->getBasePtr();
10640 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
10641 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
10642 VT = ST->getMemoryVT();
10643 Ptr = ST->getBasePtr();
10648 bool isLegal = false;
10649 if (Subtarget->isThumb2())
10650 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
10653 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
10659 // Swap base ptr and offset to catch more post-index load / store when
10660 // it's legal. In Thumb2 mode, offset must be an immediate.
10661 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
10662 !Subtarget->isThumb2())
10663 std::swap(Base, Offset);
10665 // Post-indexed load / store update the base pointer.
10670 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
10674 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
10677 const SelectionDAG &DAG,
10678 unsigned Depth) const {
10679 unsigned BitWidth = KnownOne.getBitWidth();
10680 KnownZero = KnownOne = APInt(BitWidth, 0);
10681 switch (Op.getOpcode()) {
10687 // These nodes' second result is a boolean
10688 if (Op.getResNo() == 0)
10690 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
10692 case ARMISD::CMOV: {
10693 // Bits are known zero/one if known on the LHS and RHS.
10694 DAG.ComputeMaskedBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
10695 if (KnownZero == 0 && KnownOne == 0) return;
10697 APInt KnownZeroRHS, KnownOneRHS;
10698 DAG.ComputeMaskedBits(Op.getOperand(1), KnownZeroRHS, KnownOneRHS, Depth+1);
10699 KnownZero &= KnownZeroRHS;
10700 KnownOne &= KnownOneRHS;
10706 //===----------------------------------------------------------------------===//
10707 // ARM Inline Assembly Support
10708 //===----------------------------------------------------------------------===//
10710 bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
10711 // Looking for "rev" which is V6+.
10712 if (!Subtarget->hasV6Ops())
10715 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
10716 std::string AsmStr = IA->getAsmString();
10717 SmallVector<StringRef, 4> AsmPieces;
10718 SplitString(AsmStr, AsmPieces, ";\n");
10720 switch (AsmPieces.size()) {
10721 default: return false;
10723 AsmStr = AsmPieces[0];
10725 SplitString(AsmStr, AsmPieces, " \t,");
10728 if (AsmPieces.size() == 3 &&
10729 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" &&
10730 IA->getConstraintString().compare(0, 4, "=l,l") == 0) {
10731 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
10732 if (Ty && Ty->getBitWidth() == 32)
10733 return IntrinsicLowering::LowerToByteSwap(CI);
10741 /// getConstraintType - Given a constraint letter, return the type of
10742 /// constraint it is for this target.
10743 ARMTargetLowering::ConstraintType
10744 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
10745 if (Constraint.size() == 1) {
10746 switch (Constraint[0]) {
10748 case 'l': return C_RegisterClass;
10749 case 'w': return C_RegisterClass;
10750 case 'h': return C_RegisterClass;
10751 case 'x': return C_RegisterClass;
10752 case 't': return C_RegisterClass;
10753 case 'j': return C_Other; // Constant for movw.
10754 // An address with a single base register. Due to the way we
10755 // currently handle addresses it is the same as an 'r' memory constraint.
10756 case 'Q': return C_Memory;
10758 } else if (Constraint.size() == 2) {
10759 switch (Constraint[0]) {
10761 // All 'U+' constraints are addresses.
10762 case 'U': return C_Memory;
10765 return TargetLowering::getConstraintType(Constraint);
10768 /// Examine constraint type and operand type and determine a weight value.
10769 /// This object must already have been set up with the operand type
10770 /// and the current alternative constraint selected.
10771 TargetLowering::ConstraintWeight
10772 ARMTargetLowering::getSingleConstraintMatchWeight(
10773 AsmOperandInfo &info, const char *constraint) const {
10774 ConstraintWeight weight = CW_Invalid;
10775 Value *CallOperandVal = info.CallOperandVal;
10776 // If we don't have a value, we can't do a match,
10777 // but allow it at the lowest weight.
10778 if (CallOperandVal == NULL)
10780 Type *type = CallOperandVal->getType();
10781 // Look at the constraint type.
10782 switch (*constraint) {
10784 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
10787 if (type->isIntegerTy()) {
10788 if (Subtarget->isThumb())
10789 weight = CW_SpecificReg;
10791 weight = CW_Register;
10795 if (type->isFloatingPointTy())
10796 weight = CW_Register;
10802 typedef std::pair<unsigned, const TargetRegisterClass*> RCPair;
10804 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
10806 if (Constraint.size() == 1) {
10807 // GCC ARM Constraint Letters
10808 switch (Constraint[0]) {
10809 case 'l': // Low regs or general regs.
10810 if (Subtarget->isThumb())
10811 return RCPair(0U, &ARM::tGPRRegClass);
10812 return RCPair(0U, &ARM::GPRRegClass);
10813 case 'h': // High regs or no regs.
10814 if (Subtarget->isThumb())
10815 return RCPair(0U, &ARM::hGPRRegClass);
10818 return RCPair(0U, &ARM::GPRRegClass);
10820 if (VT == MVT::Other)
10822 if (VT == MVT::f32)
10823 return RCPair(0U, &ARM::SPRRegClass);
10824 if (VT.getSizeInBits() == 64)
10825 return RCPair(0U, &ARM::DPRRegClass);
10826 if (VT.getSizeInBits() == 128)
10827 return RCPair(0U, &ARM::QPRRegClass);
10830 if (VT == MVT::Other)
10832 if (VT == MVT::f32)
10833 return RCPair(0U, &ARM::SPR_8RegClass);
10834 if (VT.getSizeInBits() == 64)
10835 return RCPair(0U, &ARM::DPR_8RegClass);
10836 if (VT.getSizeInBits() == 128)
10837 return RCPair(0U, &ARM::QPR_8RegClass);
10840 if (VT == MVT::f32)
10841 return RCPair(0U, &ARM::SPRRegClass);
10845 if (StringRef("{cc}").equals_lower(Constraint))
10846 return std::make_pair(unsigned(ARM::CPSR), &ARM::CCRRegClass);
10848 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
10851 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
10852 /// vector. If it is invalid, don't add anything to Ops.
10853 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
10854 std::string &Constraint,
10855 std::vector<SDValue>&Ops,
10856 SelectionDAG &DAG) const {
10857 SDValue Result(0, 0);
10859 // Currently only support length 1 constraints.
10860 if (Constraint.length() != 1) return;
10862 char ConstraintLetter = Constraint[0];
10863 switch (ConstraintLetter) {
10866 case 'I': case 'J': case 'K': case 'L':
10867 case 'M': case 'N': case 'O':
10868 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
10872 int64_t CVal64 = C->getSExtValue();
10873 int CVal = (int) CVal64;
10874 // None of these constraints allow values larger than 32 bits. Check
10875 // that the value fits in an int.
10876 if (CVal != CVal64)
10879 switch (ConstraintLetter) {
10881 // Constant suitable for movw, must be between 0 and
10883 if (Subtarget->hasV6T2Ops())
10884 if (CVal >= 0 && CVal <= 65535)
10888 if (Subtarget->isThumb1Only()) {
10889 // This must be a constant between 0 and 255, for ADD
10891 if (CVal >= 0 && CVal <= 255)
10893 } else if (Subtarget->isThumb2()) {
10894 // A constant that can be used as an immediate value in a
10895 // data-processing instruction.
10896 if (ARM_AM::getT2SOImmVal(CVal) != -1)
10899 // A constant that can be used as an immediate value in a
10900 // data-processing instruction.
10901 if (ARM_AM::getSOImmVal(CVal) != -1)
10907 if (Subtarget->isThumb()) { // FIXME thumb2
10908 // This must be a constant between -255 and -1, for negated ADD
10909 // immediates. This can be used in GCC with an "n" modifier that
10910 // prints the negated value, for use with SUB instructions. It is
10911 // not useful otherwise but is implemented for compatibility.
10912 if (CVal >= -255 && CVal <= -1)
10915 // This must be a constant between -4095 and 4095. It is not clear
10916 // what this constraint is intended for. Implemented for
10917 // compatibility with GCC.
10918 if (CVal >= -4095 && CVal <= 4095)
10924 if (Subtarget->isThumb1Only()) {
10925 // A 32-bit value where only one byte has a nonzero value. Exclude
10926 // zero to match GCC. This constraint is used by GCC internally for
10927 // constants that can be loaded with a move/shift combination.
10928 // It is not useful otherwise but is implemented for compatibility.
10929 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
10931 } else if (Subtarget->isThumb2()) {
10932 // A constant whose bitwise inverse can be used as an immediate
10933 // value in a data-processing instruction. This can be used in GCC
10934 // with a "B" modifier that prints the inverted value, for use with
10935 // BIC and MVN instructions. It is not useful otherwise but is
10936 // implemented for compatibility.
10937 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
10940 // A constant whose bitwise inverse can be used as an immediate
10941 // value in a data-processing instruction. This can be used in GCC
10942 // with a "B" modifier that prints the inverted value, for use with
10943 // BIC and MVN instructions. It is not useful otherwise but is
10944 // implemented for compatibility.
10945 if (ARM_AM::getSOImmVal(~CVal) != -1)
10951 if (Subtarget->isThumb1Only()) {
10952 // This must be a constant between -7 and 7,
10953 // for 3-operand ADD/SUB immediate instructions.
10954 if (CVal >= -7 && CVal < 7)
10956 } else if (Subtarget->isThumb2()) {
10957 // A constant whose negation can be used as an immediate value in a
10958 // data-processing instruction. This can be used in GCC with an "n"
10959 // modifier that prints the negated value, for use with SUB
10960 // instructions. It is not useful otherwise but is implemented for
10962 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
10965 // A constant whose negation can be used as an immediate value in a
10966 // data-processing instruction. This can be used in GCC with an "n"
10967 // modifier that prints the negated value, for use with SUB
10968 // instructions. It is not useful otherwise but is implemented for
10970 if (ARM_AM::getSOImmVal(-CVal) != -1)
10976 if (Subtarget->isThumb()) { // FIXME thumb2
10977 // This must be a multiple of 4 between 0 and 1020, for
10978 // ADD sp + immediate.
10979 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
10982 // A power of two or a constant between 0 and 32. This is used in
10983 // GCC for the shift amount on shifted register operands, but it is
10984 // useful in general for any shift amounts.
10985 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
10991 if (Subtarget->isThumb()) { // FIXME thumb2
10992 // This must be a constant between 0 and 31, for shift amounts.
10993 if (CVal >= 0 && CVal <= 31)
10999 if (Subtarget->isThumb()) { // FIXME thumb2
11000 // This must be a multiple of 4 between -508 and 508, for
11001 // ADD/SUB sp = sp + immediate.
11002 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
11007 Result = DAG.getTargetConstant(CVal, Op.getValueType());
11011 if (Result.getNode()) {
11012 Ops.push_back(Result);
11015 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
11018 SDValue ARMTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
11019 assert(Subtarget->isTargetAEABI() && "Register-based DivRem lowering only");
11020 unsigned Opcode = Op->getOpcode();
11021 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
11022 "Invalid opcode for Div/Rem lowering");
11023 bool isSigned = (Opcode == ISD::SDIVREM);
11024 EVT VT = Op->getValueType(0);
11025 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
11028 switch (VT.getSimpleVT().SimpleTy) {
11029 default: llvm_unreachable("Unexpected request for libcall!");
11030 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
11031 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
11032 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
11033 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
11036 SDValue InChain = DAG.getEntryNode();
11038 TargetLowering::ArgListTy Args;
11039 TargetLowering::ArgListEntry Entry;
11040 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
11041 EVT ArgVT = Op->getOperand(i).getValueType();
11042 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
11043 Entry.Node = Op->getOperand(i);
11045 Entry.isSExt = isSigned;
11046 Entry.isZExt = !isSigned;
11047 Args.push_back(Entry);
11050 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
11053 Type *RetTy = (Type*)StructType::get(Ty, Ty, NULL);
11057 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, true,
11058 0, getLibcallCallingConv(LC), /*isTailCall=*/false,
11059 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
11060 Callee, Args, DAG, dl);
11061 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
11063 return CallInfo.first;
11067 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
11068 // The ARM target isn't yet aware of offsets.
11072 bool ARM::isBitFieldInvertedMask(unsigned v) {
11073 if (v == 0xffffffff)
11076 // there can be 1's on either or both "outsides", all the "inside"
11077 // bits must be 0's
11078 unsigned TO = CountTrailingOnes_32(v);
11079 unsigned LO = CountLeadingOnes_32(v);
11080 v = (v >> TO) << TO;
11081 v = (v << LO) >> LO;
11085 /// isFPImmLegal - Returns true if the target can instruction select the
11086 /// specified FP immediate natively. If false, the legalizer will
11087 /// materialize the FP immediate as a load from a constant pool.
11088 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
11089 if (!Subtarget->hasVFP3())
11091 if (VT == MVT::f32)
11092 return ARM_AM::getFP32Imm(Imm) != -1;
11093 if (VT == MVT::f64)
11094 return ARM_AM::getFP64Imm(Imm) != -1;
11098 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
11099 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
11100 /// specified in the intrinsic calls.
11101 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
11103 unsigned Intrinsic) const {
11104 switch (Intrinsic) {
11105 case Intrinsic::arm_neon_vld1:
11106 case Intrinsic::arm_neon_vld2:
11107 case Intrinsic::arm_neon_vld3:
11108 case Intrinsic::arm_neon_vld4:
11109 case Intrinsic::arm_neon_vld2lane:
11110 case Intrinsic::arm_neon_vld3lane:
11111 case Intrinsic::arm_neon_vld4lane: {
11112 Info.opc = ISD::INTRINSIC_W_CHAIN;
11113 // Conservatively set memVT to the entire set of vectors loaded.
11114 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
11115 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
11116 Info.ptrVal = I.getArgOperand(0);
11118 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
11119 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
11120 Info.vol = false; // volatile loads with NEON intrinsics not supported
11121 Info.readMem = true;
11122 Info.writeMem = false;
11125 case Intrinsic::arm_neon_vst1:
11126 case Intrinsic::arm_neon_vst2:
11127 case Intrinsic::arm_neon_vst3:
11128 case Intrinsic::arm_neon_vst4:
11129 case Intrinsic::arm_neon_vst2lane:
11130 case Intrinsic::arm_neon_vst3lane:
11131 case Intrinsic::arm_neon_vst4lane: {
11132 Info.opc = ISD::INTRINSIC_VOID;
11133 // Conservatively set memVT to the entire set of vectors stored.
11134 unsigned NumElts = 0;
11135 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
11136 Type *ArgTy = I.getArgOperand(ArgI)->getType();
11137 if (!ArgTy->isVectorTy())
11139 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
11141 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
11142 Info.ptrVal = I.getArgOperand(0);
11144 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
11145 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
11146 Info.vol = false; // volatile stores with NEON intrinsics not supported
11147 Info.readMem = false;
11148 Info.writeMem = true;
11151 case Intrinsic::arm_ldrex: {
11152 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
11153 Info.opc = ISD::INTRINSIC_W_CHAIN;
11154 Info.memVT = MVT::getVT(PtrTy->getElementType());
11155 Info.ptrVal = I.getArgOperand(0);
11157 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
11159 Info.readMem = true;
11160 Info.writeMem = false;
11163 case Intrinsic::arm_strex: {
11164 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
11165 Info.opc = ISD::INTRINSIC_W_CHAIN;
11166 Info.memVT = MVT::getVT(PtrTy->getElementType());
11167 Info.ptrVal = I.getArgOperand(1);
11169 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
11171 Info.readMem = false;
11172 Info.writeMem = true;
11175 case Intrinsic::arm_strexd: {
11176 Info.opc = ISD::INTRINSIC_W_CHAIN;
11177 Info.memVT = MVT::i64;
11178 Info.ptrVal = I.getArgOperand(2);
11182 Info.readMem = false;
11183 Info.writeMem = true;
11186 case Intrinsic::arm_ldrexd: {
11187 Info.opc = ISD::INTRINSIC_W_CHAIN;
11188 Info.memVT = MVT::i64;
11189 Info.ptrVal = I.getArgOperand(0);
11193 Info.readMem = true;
11194 Info.writeMem = false;