1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMISelLowering.h"
18 #include "ARMTargetMachine.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/SelectionDAGISel.h"
30 #include "llvm/Target/TargetLowering.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Support/Compiler.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
39 //===--------------------------------------------------------------------===//
40 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
41 /// instructions for SelectionDAG operations.
44 class ARMDAGToDAGISel : public SelectionDAGISel {
45 ARMBaseTargetMachine &TM;
47 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
48 /// make the right decision when generating code for different targets.
49 const ARMSubtarget *Subtarget;
52 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
53 CodeGenOpt::Level OptLevel)
54 : SelectionDAGISel(tm, OptLevel), TM(tm),
55 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
58 virtual const char *getPassName() const {
59 return "ARM Instruction Selection";
62 /// getI32Imm - Return a target constant with the specified value, of type i32.
63 inline SDValue getI32Imm(unsigned Imm) {
64 return CurDAG->getTargetConstant(Imm, MVT::i32);
67 SDNode *Select(SDValue Op);
68 virtual void InstructionSelect();
69 bool SelectShifterOperandReg(SDValue Op, SDValue N, SDValue &A,
70 SDValue &B, SDValue &C);
71 bool SelectAddrMode2(SDValue Op, SDValue N, SDValue &Base,
72 SDValue &Offset, SDValue &Opc);
73 bool SelectAddrMode2Offset(SDValue Op, SDValue N,
74 SDValue &Offset, SDValue &Opc);
75 bool SelectAddrMode3(SDValue Op, SDValue N, SDValue &Base,
76 SDValue &Offset, SDValue &Opc);
77 bool SelectAddrMode3Offset(SDValue Op, SDValue N,
78 SDValue &Offset, SDValue &Opc);
79 bool SelectAddrMode4(SDValue Op, SDValue N, SDValue &Addr,
81 bool SelectAddrMode5(SDValue Op, SDValue N, SDValue &Base,
83 bool SelectAddrMode6(SDValue Op, SDValue N, SDValue &Addr, SDValue &Update,
86 bool SelectAddrModePC(SDValue Op, SDValue N, SDValue &Offset,
89 bool SelectThumbAddrModeRR(SDValue Op, SDValue N, SDValue &Base,
91 bool SelectThumbAddrModeRI5(SDValue Op, SDValue N, unsigned Scale,
92 SDValue &Base, SDValue &OffImm,
94 bool SelectThumbAddrModeS1(SDValue Op, SDValue N, SDValue &Base,
95 SDValue &OffImm, SDValue &Offset);
96 bool SelectThumbAddrModeS2(SDValue Op, SDValue N, SDValue &Base,
97 SDValue &OffImm, SDValue &Offset);
98 bool SelectThumbAddrModeS4(SDValue Op, SDValue N, SDValue &Base,
99 SDValue &OffImm, SDValue &Offset);
100 bool SelectThumbAddrModeSP(SDValue Op, SDValue N, SDValue &Base,
103 bool SelectT2ShifterOperandReg(SDValue Op, SDValue N,
104 SDValue &BaseReg, SDValue &Opc);
105 bool SelectT2AddrModeImm12(SDValue Op, SDValue N, SDValue &Base,
107 bool SelectT2AddrModeImm8(SDValue Op, SDValue N, SDValue &Base,
109 bool SelectT2AddrModeImm8Offset(SDValue Op, SDValue N,
111 bool SelectT2AddrModeImm8s4(SDValue Op, SDValue N, SDValue &Base,
113 bool SelectT2AddrModeSoReg(SDValue Op, SDValue N, SDValue &Base,
114 SDValue &OffReg, SDValue &ShImm);
116 // Include the pieces autogenerated from the target description.
117 #include "ARMGenDAGISel.inc"
120 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
122 SDNode *SelectARMIndexedLoad(SDValue Op);
123 SDNode *SelectT2IndexedLoad(SDValue Op);
125 /// SelectDYN_ALLOC - Select dynamic alloc for Thumb.
126 SDNode *SelectDYN_ALLOC(SDValue Op);
128 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
129 /// inline asm expressions.
130 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
132 std::vector<SDValue> &OutOps);
136 void ARMDAGToDAGISel::InstructionSelect() {
140 CurDAG->RemoveDeadNodes();
143 bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue Op,
148 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
150 // Don't match base register only case. That is matched to a separate
151 // lower complexity pattern with explicit register operand.
152 if (ShOpcVal == ARM_AM::no_shift) return false;
154 BaseReg = N.getOperand(0);
155 unsigned ShImmVal = 0;
156 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
157 ShReg = CurDAG->getRegister(0, MVT::i32);
158 ShImmVal = RHS->getZExtValue() & 31;
160 ShReg = N.getOperand(1);
162 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
167 bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N,
168 SDValue &Base, SDValue &Offset,
170 if (N.getOpcode() == ISD::MUL) {
171 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
172 // X * [3,5,9] -> X + X * [2,4,8] etc.
173 int RHSC = (int)RHS->getZExtValue();
176 ARM_AM::AddrOpc AddSub = ARM_AM::add;
178 AddSub = ARM_AM::sub;
181 if (isPowerOf2_32(RHSC)) {
182 unsigned ShAmt = Log2_32(RHSC);
183 Base = Offset = N.getOperand(0);
184 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
193 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
195 if (N.getOpcode() == ISD::FrameIndex) {
196 int FI = cast<FrameIndexSDNode>(N)->getIndex();
197 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
198 } else if (N.getOpcode() == ARMISD::Wrapper) {
199 Base = N.getOperand(0);
201 Offset = CurDAG->getRegister(0, MVT::i32);
202 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
208 // Match simple R +/- imm12 operands.
209 if (N.getOpcode() == ISD::ADD)
210 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
211 int RHSC = (int)RHS->getZExtValue();
212 if ((RHSC >= 0 && RHSC < 0x1000) ||
213 (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
214 Base = N.getOperand(0);
215 if (Base.getOpcode() == ISD::FrameIndex) {
216 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
217 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
219 Offset = CurDAG->getRegister(0, MVT::i32);
221 ARM_AM::AddrOpc AddSub = ARM_AM::add;
223 AddSub = ARM_AM::sub;
226 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
233 // Otherwise this is R +/- [possibly shifted] R
234 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
235 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
238 Base = N.getOperand(0);
239 Offset = N.getOperand(1);
241 if (ShOpcVal != ARM_AM::no_shift) {
242 // Check to see if the RHS of the shift is a constant, if not, we can't fold
244 if (ConstantSDNode *Sh =
245 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
246 ShAmt = Sh->getZExtValue();
247 Offset = N.getOperand(1).getOperand(0);
249 ShOpcVal = ARM_AM::no_shift;
253 // Try matching (R shl C) + (R).
254 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
255 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
256 if (ShOpcVal != ARM_AM::no_shift) {
257 // Check to see if the RHS of the shift is a constant, if not, we can't
259 if (ConstantSDNode *Sh =
260 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
261 ShAmt = Sh->getZExtValue();
262 Offset = N.getOperand(0).getOperand(0);
263 Base = N.getOperand(1);
265 ShOpcVal = ARM_AM::no_shift;
270 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
275 bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDValue Op, SDValue N,
276 SDValue &Offset, SDValue &Opc) {
277 unsigned Opcode = Op.getOpcode();
278 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
279 ? cast<LoadSDNode>(Op)->getAddressingMode()
280 : cast<StoreSDNode>(Op)->getAddressingMode();
281 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
282 ? ARM_AM::add : ARM_AM::sub;
283 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
284 int Val = (int)C->getZExtValue();
285 if (Val >= 0 && Val < 0x1000) { // 12 bits.
286 Offset = CurDAG->getRegister(0, MVT::i32);
287 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
295 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
297 if (ShOpcVal != ARM_AM::no_shift) {
298 // Check to see if the RHS of the shift is a constant, if not, we can't fold
300 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
301 ShAmt = Sh->getZExtValue();
302 Offset = N.getOperand(0);
304 ShOpcVal = ARM_AM::no_shift;
308 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
314 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue Op, SDValue N,
315 SDValue &Base, SDValue &Offset,
317 if (N.getOpcode() == ISD::SUB) {
318 // X - C is canonicalize to X + -C, no need to handle it here.
319 Base = N.getOperand(0);
320 Offset = N.getOperand(1);
321 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
325 if (N.getOpcode() != ISD::ADD) {
327 if (N.getOpcode() == ISD::FrameIndex) {
328 int FI = cast<FrameIndexSDNode>(N)->getIndex();
329 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
331 Offset = CurDAG->getRegister(0, MVT::i32);
332 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
336 // If the RHS is +/- imm8, fold into addr mode.
337 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
338 int RHSC = (int)RHS->getZExtValue();
339 if ((RHSC >= 0 && RHSC < 256) ||
340 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
341 Base = N.getOperand(0);
342 if (Base.getOpcode() == ISD::FrameIndex) {
343 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
344 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
346 Offset = CurDAG->getRegister(0, MVT::i32);
348 ARM_AM::AddrOpc AddSub = ARM_AM::add;
350 AddSub = ARM_AM::sub;
353 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
358 Base = N.getOperand(0);
359 Offset = N.getOperand(1);
360 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
364 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDValue Op, SDValue N,
365 SDValue &Offset, SDValue &Opc) {
366 unsigned Opcode = Op.getOpcode();
367 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
368 ? cast<LoadSDNode>(Op)->getAddressingMode()
369 : cast<StoreSDNode>(Op)->getAddressingMode();
370 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
371 ? ARM_AM::add : ARM_AM::sub;
372 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
373 int Val = (int)C->getZExtValue();
374 if (Val >= 0 && Val < 256) {
375 Offset = CurDAG->getRegister(0, MVT::i32);
376 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
382 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
386 bool ARMDAGToDAGISel::SelectAddrMode4(SDValue Op, SDValue N,
387 SDValue &Addr, SDValue &Mode) {
389 Mode = CurDAG->getTargetConstant(0, MVT::i32);
393 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue Op, SDValue N,
394 SDValue &Base, SDValue &Offset) {
395 if (N.getOpcode() != ISD::ADD) {
397 if (N.getOpcode() == ISD::FrameIndex) {
398 int FI = cast<FrameIndexSDNode>(N)->getIndex();
399 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
400 } else if (N.getOpcode() == ARMISD::Wrapper) {
401 Base = N.getOperand(0);
403 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
408 // If the RHS is +/- imm8, fold into addr mode.
409 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
410 int RHSC = (int)RHS->getZExtValue();
411 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
413 if ((RHSC >= 0 && RHSC < 256) ||
414 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
415 Base = N.getOperand(0);
416 if (Base.getOpcode() == ISD::FrameIndex) {
417 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
418 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
421 ARM_AM::AddrOpc AddSub = ARM_AM::add;
423 AddSub = ARM_AM::sub;
426 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
434 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
439 bool ARMDAGToDAGISel::SelectAddrMode6(SDValue Op, SDValue N,
440 SDValue &Addr, SDValue &Update,
443 // The optional writeback is handled in ARMLoadStoreOpt.
444 Update = CurDAG->getRegister(0, MVT::i32);
445 Opc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(false), MVT::i32);
449 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue Op, SDValue N,
450 SDValue &Offset, SDValue &Label) {
451 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
452 Offset = N.getOperand(0);
453 SDValue N1 = N.getOperand(1);
454 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
461 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue Op, SDValue N,
462 SDValue &Base, SDValue &Offset){
463 // FIXME dl should come from the parent load or store, not the address
464 DebugLoc dl = Op.getDebugLoc();
465 if (N.getOpcode() != ISD::ADD) {
466 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
467 if (!NC || NC->getZExtValue() != 0)
474 Base = N.getOperand(0);
475 Offset = N.getOperand(1);
480 ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue Op, SDValue N,
481 unsigned Scale, SDValue &Base,
482 SDValue &OffImm, SDValue &Offset) {
484 SDValue TmpBase, TmpOffImm;
485 if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
486 return false; // We want to select tLDRspi / tSTRspi instead.
487 if (N.getOpcode() == ARMISD::Wrapper &&
488 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
489 return false; // We want to select tLDRpci instead.
492 if (N.getOpcode() != ISD::ADD) {
493 Base = (N.getOpcode() == ARMISD::Wrapper) ? N.getOperand(0) : N;
494 Offset = CurDAG->getRegister(0, MVT::i32);
495 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
499 // Thumb does not have [sp, r] address mode.
500 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
501 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
502 if ((LHSR && LHSR->getReg() == ARM::SP) ||
503 (RHSR && RHSR->getReg() == ARM::SP)) {
505 Offset = CurDAG->getRegister(0, MVT::i32);
506 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
510 // If the RHS is + imm5 * scale, fold into addr mode.
511 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
512 int RHSC = (int)RHS->getZExtValue();
513 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied.
515 if (RHSC >= 0 && RHSC < 32) {
516 Base = N.getOperand(0);
517 Offset = CurDAG->getRegister(0, MVT::i32);
518 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
524 Base = N.getOperand(0);
525 Offset = N.getOperand(1);
526 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
530 bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue Op, SDValue N,
531 SDValue &Base, SDValue &OffImm,
533 return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
536 bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue Op, SDValue N,
537 SDValue &Base, SDValue &OffImm,
539 return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
542 bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue Op, SDValue N,
543 SDValue &Base, SDValue &OffImm,
545 return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
548 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N,
549 SDValue &Base, SDValue &OffImm) {
550 if (N.getOpcode() == ISD::FrameIndex) {
551 int FI = cast<FrameIndexSDNode>(N)->getIndex();
552 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
553 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
557 if (N.getOpcode() != ISD::ADD)
560 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
561 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
562 (LHSR && LHSR->getReg() == ARM::SP)) {
563 // If the RHS is + imm8 * scale, fold into addr mode.
564 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
565 int RHSC = (int)RHS->getZExtValue();
566 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied.
568 if (RHSC >= 0 && RHSC < 256) {
569 Base = N.getOperand(0);
570 if (Base.getOpcode() == ISD::FrameIndex) {
571 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
572 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
574 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
584 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue Op, SDValue N,
587 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
589 // Don't match base register only case. That is matched to a separate
590 // lower complexity pattern with explicit register operand.
591 if (ShOpcVal == ARM_AM::no_shift) return false;
593 BaseReg = N.getOperand(0);
594 unsigned ShImmVal = 0;
595 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
596 ShImmVal = RHS->getZExtValue() & 31;
597 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
604 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue Op, SDValue N,
605 SDValue &Base, SDValue &OffImm) {
606 // Match simple R + imm12 operands.
609 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
610 if (N.getOpcode() == ISD::FrameIndex) {
611 // Match frame index...
612 int FI = cast<FrameIndexSDNode>(N)->getIndex();
613 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
614 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
616 } else if (N.getOpcode() == ARMISD::Wrapper) {
617 Base = N.getOperand(0);
618 if (Base.getOpcode() == ISD::TargetConstantPool)
619 return false; // We want to select t2LDRpci instead.
622 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
626 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
627 if (SelectT2AddrModeImm8(Op, N, Base, OffImm))
628 // Let t2LDRi8 handle (R - imm8).
631 int RHSC = (int)RHS->getZExtValue();
632 if (N.getOpcode() == ISD::SUB)
635 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
636 Base = N.getOperand(0);
637 if (Base.getOpcode() == ISD::FrameIndex) {
638 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
639 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
641 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
648 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
652 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue Op, SDValue N,
653 SDValue &Base, SDValue &OffImm) {
654 // Match simple R - imm8 operands.
655 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::SUB) {
656 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
657 int RHSC = (int)RHS->getSExtValue();
658 if (N.getOpcode() == ISD::SUB)
661 if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
662 Base = N.getOperand(0);
663 if (Base.getOpcode() == ISD::FrameIndex) {
664 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
665 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
667 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
676 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDValue Op, SDValue N,
678 unsigned Opcode = Op.getOpcode();
679 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
680 ? cast<LoadSDNode>(Op)->getAddressingMode()
681 : cast<StoreSDNode>(Op)->getAddressingMode();
682 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N)) {
683 int RHSC = (int)RHS->getZExtValue();
684 if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
685 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
686 ? CurDAG->getTargetConstant(RHSC, MVT::i32)
687 : CurDAG->getTargetConstant(-RHSC, MVT::i32);
695 bool ARMDAGToDAGISel::SelectT2AddrModeImm8s4(SDValue Op, SDValue N,
696 SDValue &Base, SDValue &OffImm) {
697 if (N.getOpcode() == ISD::ADD) {
698 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
699 int RHSC = (int)RHS->getZExtValue();
700 if (((RHSC & 0x3) == 0) &&
701 ((RHSC >= 0 && RHSC < 0x400) || (RHSC < 0 && RHSC > -0x400))) { // 8 bits.
702 Base = N.getOperand(0);
703 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
707 } else if (N.getOpcode() == ISD::SUB) {
708 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
709 int RHSC = (int)RHS->getZExtValue();
710 if (((RHSC & 0x3) == 0) && (RHSC >= 0 && RHSC < 0x400)) { // 8 bits.
711 Base = N.getOperand(0);
712 OffImm = CurDAG->getTargetConstant(-RHSC, MVT::i32);
721 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue Op, SDValue N,
723 SDValue &OffReg, SDValue &ShImm) {
724 // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
725 if (N.getOpcode() != ISD::ADD)
728 // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
729 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
730 int RHSC = (int)RHS->getZExtValue();
731 if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
733 else if (RHSC < 0 && RHSC >= -255) // 8 bits
737 // Look for (R + R) or (R + (R << [1,2,3])).
739 Base = N.getOperand(0);
740 OffReg = N.getOperand(1);
742 // Swap if it is ((R << c) + R).
743 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg);
744 if (ShOpcVal != ARM_AM::lsl) {
745 ShOpcVal = ARM_AM::getShiftOpcForNode(Base);
746 if (ShOpcVal == ARM_AM::lsl)
747 std::swap(Base, OffReg);
750 if (ShOpcVal == ARM_AM::lsl) {
751 // Check to see if the RHS of the shift is a constant, if not, we can't fold
753 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
754 ShAmt = Sh->getZExtValue();
757 ShOpcVal = ARM_AM::no_shift;
759 OffReg = OffReg.getOperand(0);
761 ShOpcVal = ARM_AM::no_shift;
765 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
770 //===--------------------------------------------------------------------===//
772 /// getAL - Returns a ARMCC::AL immediate node.
773 static inline SDValue getAL(SelectionDAG *CurDAG) {
774 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
777 SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDValue Op) {
778 LoadSDNode *LD = cast<LoadSDNode>(Op);
779 ISD::MemIndexedMode AM = LD->getAddressingMode();
780 if (AM == ISD::UNINDEXED)
783 EVT LoadedVT = LD->getMemoryVT();
784 SDValue Offset, AMOpc;
785 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
788 if (LoadedVT == MVT::i32 &&
789 SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
790 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
792 } else if (LoadedVT == MVT::i16 &&
793 SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
795 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
796 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
797 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
798 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
799 if (LD->getExtensionType() == ISD::SEXTLOAD) {
800 if (SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
802 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
805 if (SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
807 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
813 SDValue Chain = LD->getChain();
814 SDValue Base = LD->getBasePtr();
815 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
816 CurDAG->getRegister(0, MVT::i32), Chain };
817 return CurDAG->getMachineNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
824 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDValue Op) {
825 LoadSDNode *LD = cast<LoadSDNode>(Op);
826 ISD::MemIndexedMode AM = LD->getAddressingMode();
827 if (AM == ISD::UNINDEXED)
830 EVT LoadedVT = LD->getMemoryVT();
831 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
833 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
836 if (SelectT2AddrModeImm8Offset(Op, LD->getOffset(), Offset)) {
837 switch (LoadedVT.getSimpleVT().SimpleTy) {
839 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
843 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
845 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
850 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
852 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
861 SDValue Chain = LD->getChain();
862 SDValue Base = LD->getBasePtr();
863 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
864 CurDAG->getRegister(0, MVT::i32), Chain };
865 return CurDAG->getMachineNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
872 SDNode *ARMDAGToDAGISel::SelectDYN_ALLOC(SDValue Op) {
873 SDNode *N = Op.getNode();
874 DebugLoc dl = N->getDebugLoc();
875 EVT VT = Op.getValueType();
876 SDValue Chain = Op.getOperand(0);
877 SDValue Size = Op.getOperand(1);
878 SDValue Align = Op.getOperand(2);
879 SDValue SP = CurDAG->getRegister(ARM::SP, MVT::i32);
880 int32_t AlignVal = cast<ConstantSDNode>(Align)->getSExtValue();
882 // We need to align the stack. Use Thumb1 tAND which is the only thumb
883 // instruction that can read and write SP. This matches to a pseudo
884 // instruction that has a chain to ensure the result is written back to
885 // the stack pointer.
886 SP = SDValue(CurDAG->getMachineNode(ARM::tANDsp, dl, VT, SP, Align), 0);
888 bool isC = isa<ConstantSDNode>(Size);
889 uint32_t C = isC ? cast<ConstantSDNode>(Size)->getZExtValue() : ~0UL;
890 // Handle the most common case for both Thumb1 and Thumb2:
891 // tSUBspi - immediate is between 0 ... 508 inclusive.
892 if (C <= 508 && ((C & 3) == 0))
893 // FIXME: tSUBspi encode scale 4 implicitly.
894 return CurDAG->SelectNodeTo(N, ARM::tSUBspi_, VT, MVT::Other, SP,
895 CurDAG->getTargetConstant(C/4, MVT::i32),
898 if (Subtarget->isThumb1Only()) {
899 // Use tADDspr since Thumb1 does not have a sub r, sp, r. ARMISelLowering
900 // should have negated the size operand already. FIXME: We can't insert
901 // new target independent node at this stage so we are forced to negate
902 // it earlier. Is there a better solution?
903 return CurDAG->SelectNodeTo(N, ARM::tADDspr_, VT, MVT::Other, SP, Size,
905 } else if (Subtarget->isThumb2()) {
906 if (isC && Predicate_t2_so_imm(Size.getNode())) {
908 SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, MVT::i32), Chain };
909 return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi_, VT, MVT::Other, Ops, 3);
910 } else if (isC && Predicate_imm0_4095(Size.getNode())) {
912 SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, MVT::i32), Chain };
913 return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi12_, VT, MVT::Other, Ops, 3);
916 SDValue Ops[] = { SP, Size,
917 getI32Imm(ARM_AM::getSORegOpc(ARM_AM::lsl,0)), Chain };
918 return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPs_, VT, MVT::Other, Ops, 4);
922 // FIXME: Add ADD / SUB sp instructions for ARM.
926 SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
927 SDNode *N = Op.getNode();
928 DebugLoc dl = N->getDebugLoc();
930 if (N->isMachineOpcode())
931 return NULL; // Already selected.
933 switch (N->getOpcode()) {
935 case ISD::Constant: {
936 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
938 if (Subtarget->hasThumb2())
939 // Thumb2-aware targets have the MOVT instruction, so all immediates can
940 // be done with MOV + MOVT, at worst.
943 if (Subtarget->isThumb()) {
944 UseCP = (Val > 255 && // MOV
945 ~Val > 255 && // MOV + MVN
946 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
948 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
949 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
950 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
955 CurDAG->getTargetConstantPool(ConstantInt::get(
956 Type::getInt32Ty(*CurDAG->getContext()), Val),
960 if (Subtarget->isThumb1Only()) {
961 SDValue Pred = CurDAG->getTargetConstant(0xEULL, MVT::i32);
962 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
963 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
964 ResNode = CurDAG->getMachineNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
969 CurDAG->getRegister(0, MVT::i32),
970 CurDAG->getTargetConstant(0, MVT::i32),
972 CurDAG->getRegister(0, MVT::i32),
973 CurDAG->getEntryNode()
975 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
978 ReplaceUses(Op, SDValue(ResNode, 0));
982 // Other cases are autogenerated.
985 case ISD::FrameIndex: {
986 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
987 int FI = cast<FrameIndexSDNode>(N)->getIndex();
988 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
989 if (Subtarget->isThumb1Only()) {
990 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
991 CurDAG->getTargetConstant(0, MVT::i32));
993 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
994 ARM::t2ADDri : ARM::ADDri);
995 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
996 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
997 CurDAG->getRegister(0, MVT::i32) };
998 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1001 case ARMISD::DYN_ALLOC:
1002 return SelectDYN_ALLOC(Op);
1004 if (Subtarget->isThumb1Only())
1006 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1007 unsigned RHSV = C->getZExtValue();
1009 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
1010 unsigned ShImm = Log2_32(RHSV-1);
1013 SDValue V = Op.getOperand(0);
1014 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
1015 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
1016 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1017 if (Subtarget->isThumb()) {
1018 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1019 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
1021 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1022 return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
1025 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
1026 unsigned ShImm = Log2_32(RHSV+1);
1029 SDValue V = Op.getOperand(0);
1030 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
1031 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
1032 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1033 if (Subtarget->isThumb()) {
1034 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0 };
1035 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 5);
1037 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1038 return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
1044 return CurDAG->getMachineNode(ARM::FMRRD, dl, MVT::i32, MVT::i32,
1045 Op.getOperand(0), getAL(CurDAG),
1046 CurDAG->getRegister(0, MVT::i32));
1047 case ISD::UMUL_LOHI: {
1048 if (Subtarget->isThumb1Only())
1050 if (Subtarget->isThumb()) {
1051 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1052 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1053 CurDAG->getRegister(0, MVT::i32) };
1054 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops,4);
1056 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1057 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1058 CurDAG->getRegister(0, MVT::i32) };
1059 return CurDAG->getMachineNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
1062 case ISD::SMUL_LOHI: {
1063 if (Subtarget->isThumb1Only())
1065 if (Subtarget->isThumb()) {
1066 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1067 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
1068 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops,4);
1070 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1071 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1072 CurDAG->getRegister(0, MVT::i32) };
1073 return CurDAG->getMachineNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
1077 SDNode *ResNode = 0;
1078 if (Subtarget->isThumb() && Subtarget->hasThumb2())
1079 ResNode = SelectT2IndexedLoad(Op);
1081 ResNode = SelectARMIndexedLoad(Op);
1084 // Other cases are autogenerated.
1087 case ARMISD::BRCOND: {
1088 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1089 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1090 // Pattern complexity = 6 cost = 1 size = 0
1092 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1093 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
1094 // Pattern complexity = 6 cost = 1 size = 0
1096 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1097 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1098 // Pattern complexity = 6 cost = 1 size = 0
1100 unsigned Opc = Subtarget->isThumb() ?
1101 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
1102 SDValue Chain = Op.getOperand(0);
1103 SDValue N1 = Op.getOperand(1);
1104 SDValue N2 = Op.getOperand(2);
1105 SDValue N3 = Op.getOperand(3);
1106 SDValue InFlag = Op.getOperand(4);
1107 assert(N1.getOpcode() == ISD::BasicBlock);
1108 assert(N2.getOpcode() == ISD::Constant);
1109 assert(N3.getOpcode() == ISD::Register);
1111 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1112 cast<ConstantSDNode>(N2)->getZExtValue()),
1114 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
1115 SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
1117 Chain = SDValue(ResNode, 0);
1118 if (Op.getNode()->getNumValues() == 2) {
1119 InFlag = SDValue(ResNode, 1);
1120 ReplaceUses(SDValue(Op.getNode(), 1), InFlag);
1122 ReplaceUses(SDValue(Op.getNode(), 0), SDValue(Chain.getNode(), Chain.getResNo()));
1125 case ARMISD::CMOV: {
1126 EVT VT = Op.getValueType();
1127 SDValue N0 = Op.getOperand(0);
1128 SDValue N1 = Op.getOperand(1);
1129 SDValue N2 = Op.getOperand(2);
1130 SDValue N3 = Op.getOperand(3);
1131 SDValue InFlag = Op.getOperand(4);
1132 assert(N2.getOpcode() == ISD::Constant);
1133 assert(N3.getOpcode() == ISD::Register);
1135 if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
1136 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1137 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1138 // Pattern complexity = 18 cost = 1 size = 0
1142 if (Subtarget->isThumb()) {
1143 if (SelectT2ShifterOperandReg(Op, N1, CPTmp0, CPTmp1)) {
1144 unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
1145 unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
1148 case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
1149 case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
1150 case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
1151 case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
1153 llvm_unreachable("Unknown so_reg opcode!");
1157 CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
1158 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1159 cast<ConstantSDNode>(N2)->getZExtValue()),
1161 SDValue Ops[] = { N0, CPTmp0, SOShImm, Tmp2, N3, InFlag };
1162 return CurDAG->SelectNodeTo(Op.getNode(), Opc, MVT::i32,Ops, 6);
1165 if (SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) {
1166 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1167 cast<ConstantSDNode>(N2)->getZExtValue()),
1169 SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
1170 return CurDAG->SelectNodeTo(Op.getNode(),
1171 ARM::MOVCCs, MVT::i32, Ops, 7);
1175 // Pattern: (ARMcmov:i32 GPR:i32:$false,
1176 // (imm:i32)<<P:Predicate_so_imm>>:$true,
1178 // Emits: (MOVCCi:i32 GPR:i32:$false,
1179 // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
1180 // Pattern complexity = 10 cost = 1 size = 0
1181 if (N3.getOpcode() == ISD::Constant) {
1182 if (Subtarget->isThumb()) {
1183 if (Predicate_t2_so_imm(N3.getNode())) {
1184 SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
1185 cast<ConstantSDNode>(N1)->getZExtValue()),
1187 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1188 cast<ConstantSDNode>(N2)->getZExtValue()),
1190 SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
1191 return CurDAG->SelectNodeTo(Op.getNode(),
1192 ARM::t2MOVCCi, MVT::i32, Ops, 5);
1195 if (Predicate_so_imm(N3.getNode())) {
1196 SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
1197 cast<ConstantSDNode>(N1)->getZExtValue()),
1199 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1200 cast<ConstantSDNode>(N2)->getZExtValue()),
1202 SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
1203 return CurDAG->SelectNodeTo(Op.getNode(),
1204 ARM::MOVCCi, MVT::i32, Ops, 5);
1210 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1211 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1212 // Pattern complexity = 6 cost = 1 size = 0
1214 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1215 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1216 // Pattern complexity = 6 cost = 11 size = 0
1218 // Also FCPYScc and FCPYDcc.
1219 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1220 cast<ConstantSDNode>(N2)->getZExtValue()),
1222 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
1224 switch (VT.getSimpleVT().SimpleTy) {
1225 default: assert(false && "Illegal conditional move type!");
1228 Opc = Subtarget->isThumb()
1229 ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
1239 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
1241 case ARMISD::CNEG: {
1242 EVT VT = Op.getValueType();
1243 SDValue N0 = Op.getOperand(0);
1244 SDValue N1 = Op.getOperand(1);
1245 SDValue N2 = Op.getOperand(2);
1246 SDValue N3 = Op.getOperand(3);
1247 SDValue InFlag = Op.getOperand(4);
1248 assert(N2.getOpcode() == ISD::Constant);
1249 assert(N3.getOpcode() == ISD::Register);
1251 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1252 cast<ConstantSDNode>(N2)->getZExtValue()),
1254 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
1256 switch (VT.getSimpleVT().SimpleTy) {
1257 default: assert(false && "Illegal conditional move type!");
1266 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
1269 case ARMISD::VZIP: {
1271 EVT VT = N->getValueType(0);
1272 switch (VT.getSimpleVT().SimpleTy) {
1273 default: return NULL;
1274 case MVT::v8i8: Opc = ARM::VZIPd8; break;
1275 case MVT::v4i16: Opc = ARM::VZIPd16; break;
1277 case MVT::v2i32: Opc = ARM::VZIPd32; break;
1278 case MVT::v16i8: Opc = ARM::VZIPq8; break;
1279 case MVT::v8i16: Opc = ARM::VZIPq16; break;
1281 case MVT::v4i32: Opc = ARM::VZIPq32; break;
1283 return CurDAG->getMachineNode(Opc, dl, VT, VT,
1284 N->getOperand(0), N->getOperand(1));
1286 case ARMISD::VUZP: {
1288 EVT VT = N->getValueType(0);
1289 switch (VT.getSimpleVT().SimpleTy) {
1290 default: return NULL;
1291 case MVT::v8i8: Opc = ARM::VUZPd8; break;
1292 case MVT::v4i16: Opc = ARM::VUZPd16; break;
1294 case MVT::v2i32: Opc = ARM::VUZPd32; break;
1295 case MVT::v16i8: Opc = ARM::VUZPq8; break;
1296 case MVT::v8i16: Opc = ARM::VUZPq16; break;
1298 case MVT::v4i32: Opc = ARM::VUZPq32; break;
1300 return CurDAG->getMachineNode(Opc, dl, VT, VT,
1301 N->getOperand(0), N->getOperand(1));
1303 case ARMISD::VTRN: {
1305 EVT VT = N->getValueType(0);
1306 switch (VT.getSimpleVT().SimpleTy) {
1307 default: return NULL;
1308 case MVT::v8i8: Opc = ARM::VTRNd8; break;
1309 case MVT::v4i16: Opc = ARM::VTRNd16; break;
1311 case MVT::v2i32: Opc = ARM::VTRNd32; break;
1312 case MVT::v16i8: Opc = ARM::VTRNq8; break;
1313 case MVT::v8i16: Opc = ARM::VTRNq16; break;
1315 case MVT::v4i32: Opc = ARM::VTRNq32; break;
1317 return CurDAG->getMachineNode(Opc, dl, VT, VT,
1318 N->getOperand(0), N->getOperand(1));
1321 case ISD::INTRINSIC_VOID:
1322 case ISD::INTRINSIC_W_CHAIN: {
1323 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
1324 EVT VT = N->getValueType(0);
1331 case Intrinsic::arm_neon_vld2: {
1332 SDValue MemAddr, MemUpdate, MemOpc;
1333 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1335 switch (VT.getSimpleVT().SimpleTy) {
1336 default: llvm_unreachable("unhandled vld2 type");
1337 case MVT::v8i8: Opc = ARM::VLD2d8; break;
1338 case MVT::v4i16: Opc = ARM::VLD2d16; break;
1340 case MVT::v2i32: Opc = ARM::VLD2d32; break;
1342 SDValue Chain = N->getOperand(0);
1343 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
1344 return CurDAG->getMachineNode(Opc, dl, VT, VT, MVT::Other, Ops, 4);
1347 case Intrinsic::arm_neon_vld3: {
1348 SDValue MemAddr, MemUpdate, MemOpc;
1349 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1351 switch (VT.getSimpleVT().SimpleTy) {
1352 default: llvm_unreachable("unhandled vld3 type");
1353 case MVT::v8i8: Opc = ARM::VLD3d8; break;
1354 case MVT::v4i16: Opc = ARM::VLD3d16; break;
1356 case MVT::v2i32: Opc = ARM::VLD3d32; break;
1358 SDValue Chain = N->getOperand(0);
1359 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
1360 return CurDAG->getMachineNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 4);
1363 case Intrinsic::arm_neon_vld4: {
1364 SDValue MemAddr, MemUpdate, MemOpc;
1365 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1367 switch (VT.getSimpleVT().SimpleTy) {
1368 default: llvm_unreachable("unhandled vld4 type");
1369 case MVT::v8i8: Opc = ARM::VLD4d8; break;
1370 case MVT::v4i16: Opc = ARM::VLD4d16; break;
1372 case MVT::v2i32: Opc = ARM::VLD4d32; break;
1374 SDValue Chain = N->getOperand(0);
1375 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
1376 std::vector<EVT> ResTys(4, VT);
1377 ResTys.push_back(MVT::Other);
1378 return CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 4);
1381 case Intrinsic::arm_neon_vld2lane: {
1382 SDValue MemAddr, MemUpdate, MemOpc;
1383 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1385 switch (VT.getSimpleVT().SimpleTy) {
1386 default: llvm_unreachable("unhandled vld2lane type");
1387 case MVT::v8i8: Opc = ARM::VLD2LNd8; break;
1388 case MVT::v4i16: Opc = ARM::VLD2LNd16; break;
1390 case MVT::v2i32: Opc = ARM::VLD2LNd32; break;
1392 SDValue Chain = N->getOperand(0);
1393 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1394 N->getOperand(3), N->getOperand(4),
1395 N->getOperand(5), Chain };
1396 return CurDAG->getMachineNode(Opc, dl, VT, VT, MVT::Other, Ops, 7);
1399 case Intrinsic::arm_neon_vld3lane: {
1400 SDValue MemAddr, MemUpdate, MemOpc;
1401 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1403 switch (VT.getSimpleVT().SimpleTy) {
1404 default: llvm_unreachable("unhandled vld3lane type");
1405 case MVT::v8i8: Opc = ARM::VLD3LNd8; break;
1406 case MVT::v4i16: Opc = ARM::VLD3LNd16; break;
1408 case MVT::v2i32: Opc = ARM::VLD3LNd32; break;
1410 SDValue Chain = N->getOperand(0);
1411 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1412 N->getOperand(3), N->getOperand(4),
1413 N->getOperand(5), N->getOperand(6), Chain };
1414 return CurDAG->getMachineNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 8);
1417 case Intrinsic::arm_neon_vld4lane: {
1418 SDValue MemAddr, MemUpdate, MemOpc;
1419 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1421 switch (VT.getSimpleVT().SimpleTy) {
1422 default: llvm_unreachable("unhandled vld4lane type");
1423 case MVT::v8i8: Opc = ARM::VLD4LNd8; break;
1424 case MVT::v4i16: Opc = ARM::VLD4LNd16; break;
1426 case MVT::v2i32: Opc = ARM::VLD4LNd32; break;
1428 SDValue Chain = N->getOperand(0);
1429 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1430 N->getOperand(3), N->getOperand(4),
1431 N->getOperand(5), N->getOperand(6),
1432 N->getOperand(7), Chain };
1433 std::vector<EVT> ResTys(4, VT);
1434 ResTys.push_back(MVT::Other);
1435 return CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 9);
1438 case Intrinsic::arm_neon_vst2: {
1439 SDValue MemAddr, MemUpdate, MemOpc;
1440 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1442 switch (N->getOperand(3).getValueType().getSimpleVT().SimpleTy) {
1443 default: llvm_unreachable("unhandled vst2 type");
1444 case MVT::v8i8: Opc = ARM::VST2d8; break;
1445 case MVT::v4i16: Opc = ARM::VST2d16; break;
1447 case MVT::v2i32: Opc = ARM::VST2d32; break;
1449 SDValue Chain = N->getOperand(0);
1450 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1451 N->getOperand(3), N->getOperand(4), Chain };
1452 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 6);
1455 case Intrinsic::arm_neon_vst3: {
1456 SDValue MemAddr, MemUpdate, MemOpc;
1457 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1459 switch (N->getOperand(3).getValueType().getSimpleVT().SimpleTy) {
1460 default: llvm_unreachable("unhandled vst3 type");
1461 case MVT::v8i8: Opc = ARM::VST3d8; break;
1462 case MVT::v4i16: Opc = ARM::VST3d16; break;
1464 case MVT::v2i32: Opc = ARM::VST3d32; break;
1466 SDValue Chain = N->getOperand(0);
1467 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1468 N->getOperand(3), N->getOperand(4),
1469 N->getOperand(5), Chain };
1470 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 7);
1473 case Intrinsic::arm_neon_vst4: {
1474 SDValue MemAddr, MemUpdate, MemOpc;
1475 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1477 switch (N->getOperand(3).getValueType().getSimpleVT().SimpleTy) {
1478 default: llvm_unreachable("unhandled vst4 type");
1479 case MVT::v8i8: Opc = ARM::VST4d8; break;
1480 case MVT::v4i16: Opc = ARM::VST4d16; break;
1482 case MVT::v2i32: Opc = ARM::VST4d32; break;
1484 SDValue Chain = N->getOperand(0);
1485 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1486 N->getOperand(3), N->getOperand(4),
1487 N->getOperand(5), N->getOperand(6), Chain };
1488 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 8);
1491 case Intrinsic::arm_neon_vst2lane: {
1492 SDValue MemAddr, MemUpdate, MemOpc;
1493 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1495 switch (N->getOperand(3).getValueType().getSimpleVT().SimpleTy) {
1496 default: llvm_unreachable("unhandled vst2lane type");
1497 case MVT::v8i8: Opc = ARM::VST2LNd8; break;
1498 case MVT::v4i16: Opc = ARM::VST2LNd16; break;
1500 case MVT::v2i32: Opc = ARM::VST2LNd32; break;
1502 SDValue Chain = N->getOperand(0);
1503 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1504 N->getOperand(3), N->getOperand(4),
1505 N->getOperand(5), Chain };
1506 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 7);
1509 case Intrinsic::arm_neon_vst3lane: {
1510 SDValue MemAddr, MemUpdate, MemOpc;
1511 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1513 switch (N->getOperand(3).getValueType().getSimpleVT().SimpleTy) {
1514 default: llvm_unreachable("unhandled vst3lane type");
1515 case MVT::v8i8: Opc = ARM::VST3LNd8; break;
1516 case MVT::v4i16: Opc = ARM::VST3LNd16; break;
1518 case MVT::v2i32: Opc = ARM::VST3LNd32; break;
1520 SDValue Chain = N->getOperand(0);
1521 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1522 N->getOperand(3), N->getOperand(4),
1523 N->getOperand(5), N->getOperand(6), Chain };
1524 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 8);
1527 case Intrinsic::arm_neon_vst4lane: {
1528 SDValue MemAddr, MemUpdate, MemOpc;
1529 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1531 switch (N->getOperand(3).getValueType().getSimpleVT().SimpleTy) {
1532 default: llvm_unreachable("unhandled vst4lane type");
1533 case MVT::v8i8: Opc = ARM::VST4LNd8; break;
1534 case MVT::v4i16: Opc = ARM::VST4LNd16; break;
1536 case MVT::v2i32: Opc = ARM::VST4LNd32; break;
1538 SDValue Chain = N->getOperand(0);
1539 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1540 N->getOperand(3), N->getOperand(4),
1541 N->getOperand(5), N->getOperand(6),
1542 N->getOperand(7), Chain };
1543 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 9);
1549 return SelectCode(Op);
1552 bool ARMDAGToDAGISel::
1553 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
1554 std::vector<SDValue> &OutOps) {
1555 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
1557 SDValue Base, Offset, Opc;
1558 if (!SelectAddrMode2(Op, Op, Base, Offset, Opc))
1561 OutOps.push_back(Base);
1562 OutOps.push_back(Offset);
1563 OutOps.push_back(Opc);
1567 /// createARMISelDag - This pass converts a legalized DAG into a
1568 /// ARM-specific DAG, ready for instruction scheduling.
1570 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
1571 CodeGenOpt::Level OptLevel) {
1572 return new ARMDAGToDAGISel(TM, OptLevel);