1 //===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a pass that expands pseudo instructions into target
11 // instructions to allow proper scheduling, if-conversion, and other late
12 // optimizations. This pass should be run after register allocation but before
13 // the post-regalloc scheduling pass.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "arm-pseudo"
19 #include "ARMBaseInstrInfo.h"
20 #include "ARMBaseRegisterInfo.h"
21 #include "ARMConstantPoolValue.h"
22 #include "ARMMachineFunctionInfo.h"
23 #include "MCTargetDesc/ARMAddressingModes.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove!
30 #include "llvm/Target/TargetFrameLowering.h"
31 #include "llvm/Target/TargetRegisterInfo.h"
35 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
36 cl::desc("Verify machine code after expanding ARM pseudos"));
39 class ARMExpandPseudo : public MachineFunctionPass {
42 ARMExpandPseudo() : MachineFunctionPass(ID) {}
44 const ARMBaseInstrInfo *TII;
45 const TargetRegisterInfo *TRI;
46 const ARMSubtarget *STI;
49 virtual bool runOnMachineFunction(MachineFunction &Fn);
51 virtual const char *getPassName() const {
52 return "ARM pseudo instruction expansion pass";
56 void TransferImpOps(MachineInstr &OldMI,
57 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
58 bool ExpandMI(MachineBasicBlock &MBB,
59 MachineBasicBlock::iterator MBBI);
60 bool ExpandMBB(MachineBasicBlock &MBB);
61 void ExpandVLD(MachineBasicBlock::iterator &MBBI);
62 void ExpandVST(MachineBasicBlock::iterator &MBBI);
63 void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
64 void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
65 unsigned Opc, bool IsExt);
66 void ExpandMOV32BitImm(MachineBasicBlock &MBB,
67 MachineBasicBlock::iterator &MBBI);
69 char ARMExpandPseudo::ID = 0;
72 /// TransferImpOps - Transfer implicit operands on the pseudo instruction to
73 /// the instructions created from the expansion.
74 void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI,
75 MachineInstrBuilder &UseMI,
76 MachineInstrBuilder &DefMI) {
77 const MCInstrDesc &Desc = OldMI.getDesc();
78 for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands();
80 const MachineOperand &MO = OldMI.getOperand(i);
81 assert(MO.isReg() && MO.getReg());
90 // Constants for register spacing in NEON load/store instructions.
91 // For quad-register load-lane and store-lane pseudo instructors, the
92 // spacing is initially assumed to be EvenDblSpc, and that is changed to
93 // OddDblSpc depending on the lane number operand.
100 // Entries for NEON load/store information table. The table is sorted by
101 // PseudoOpc for fast binary-search lookups.
102 struct NEONLdStTableEntry {
107 bool hasWritebackOperand;
108 uint8_t RegSpacing; // One of type NEONRegSpacing
109 uint8_t NumRegs; // D registers loaded or stored
110 uint8_t RegElts; // elements per D register; used for lane ops
111 // FIXME: Temporary flag to denote whether the real instruction takes
112 // a single register (like the encoding) or all of the registers in
113 // the list (like the asm syntax and the isel DAG). When all definitions
114 // are converted to take only the single encoded register, this will
116 bool copyAllListRegs;
118 // Comparison methods for binary search of the table.
119 bool operator<(const NEONLdStTableEntry &TE) const {
120 return PseudoOpc < TE.PseudoOpc;
122 friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) {
123 return TE.PseudoOpc < PseudoOpc;
125 friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc,
126 const NEONLdStTableEntry &TE) {
127 return PseudoOpc < TE.PseudoOpc;
132 static const NEONLdStTableEntry NEONLdStTable[] = {
133 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
134 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
135 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
136 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
137 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
138 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true},
140 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false},
141 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false},
143 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true},
144 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true},
145 { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, false, SingleSpc, 2, 2 ,true},
146 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true, SingleSpc, 2, 2 ,true},
147 { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, false, SingleSpc, 2, 8 ,true},
148 { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, true, SingleSpc, 2, 8 ,true},
149 { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, false, EvenDblSpc, 2, 4 ,true},
150 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, true, EvenDblSpc, 2, 4 ,true},
151 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, false, EvenDblSpc, 2, 2 ,true},
152 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, true, EvenDblSpc, 2, 2 ,true},
154 { ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, false, SingleSpc, 4, 4 ,false},
155 { ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed, true, true, false, SingleSpc, 4, 4 ,false},
156 { ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register, true, true, true, SingleSpc, 4, 4 ,false},
157 { ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, false, SingleSpc, 4, 2 ,false},
158 { ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed, true, true, false, SingleSpc, 4, 2 ,false},
159 { ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register, true, true, true, SingleSpc, 4, 2 ,false},
160 { ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, false, SingleSpc, 4, 8 ,false},
161 { ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed, true, true, false, SingleSpc, 4, 8 ,false},
162 { ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register, true, true, true, SingleSpc, 4, 8 ,false},
164 { ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, false, SingleSpc, 3, 4,true},
165 { ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, true, SingleSpc, 3, 4,true},
166 { ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, false, SingleSpc, 3, 2,true},
167 { ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, true, SingleSpc, 3, 2,true},
168 { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, false, SingleSpc, 3, 8,true},
169 { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, true, SingleSpc, 3, 8,true},
171 { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, false, SingleSpc, 3, 4 ,true},
172 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
173 { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, false, SingleSpc, 3, 2 ,true},
174 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
175 { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, false, SingleSpc, 3, 8 ,true},
176 { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
177 { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, false, EvenDblSpc, 3, 4 ,true},
178 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
179 { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, false, EvenDblSpc, 3, 2 ,true},
180 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
182 { ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, false, SingleSpc, 3, 4 ,true},
183 { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
184 { ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, false, SingleSpc, 3, 2 ,true},
185 { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
186 { ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, false, SingleSpc, 3, 8 ,true},
187 { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
189 { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
190 { ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, false, OddDblSpc, 3, 4 ,true},
191 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, true, OddDblSpc, 3, 4 ,true},
192 { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
193 { ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, false, OddDblSpc, 3, 2 ,true},
194 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, true, OddDblSpc, 3, 2 ,true},
195 { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, true, EvenDblSpc, 3, 8 ,true},
196 { ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, false, OddDblSpc, 3, 8 ,true},
197 { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, true, OddDblSpc, 3, 8 ,true},
199 { ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, false, SingleSpc, 4, 4,true},
200 { ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, true, SingleSpc, 4, 4,true},
201 { ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, false, SingleSpc, 4, 2,true},
202 { ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, true, SingleSpc, 4, 2,true},
203 { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, false, SingleSpc, 4, 8,true},
204 { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, true, SingleSpc, 4, 8,true},
206 { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, false, SingleSpc, 4, 4 ,true},
207 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
208 { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, false, SingleSpc, 4, 2 ,true},
209 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
210 { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, false, SingleSpc, 4, 8 ,true},
211 { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
212 { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, false, EvenDblSpc, 4, 4 ,true},
213 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
214 { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, false, EvenDblSpc, 4, 2 ,true},
215 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
217 { ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, false, SingleSpc, 4, 4 ,true},
218 { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
219 { ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, false, SingleSpc, 4, 2 ,true},
220 { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
221 { ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, false, SingleSpc, 4, 8 ,true},
222 { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
224 { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
225 { ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, false, OddDblSpc, 4, 4 ,true},
226 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, true, OddDblSpc, 4, 4 ,true},
227 { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
228 { ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, false, OddDblSpc, 4, 2 ,true},
229 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, true, OddDblSpc, 4, 2 ,true},
230 { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, true, EvenDblSpc, 4, 8 ,true},
231 { ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, false, OddDblSpc, 4, 8 ,true},
232 { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, true, OddDblSpc, 4, 8 ,true},
234 { ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, false, EvenDblSpc, 1, 4 ,true},
235 { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD, false, true, true, EvenDblSpc, 1, 4 ,true},
236 { ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, false, EvenDblSpc, 1, 2 ,true},
237 { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD, false, true, true, EvenDblSpc, 1, 2 ,true},
238 { ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, false, EvenDblSpc, 1, 8 ,true},
239 { ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, true, EvenDblSpc, 1, 8 ,true},
241 { ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, false, SingleSpc, 4, 1 ,false},
242 { ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed, false, true, false, SingleSpc, 4, 1 ,false},
243 { ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register, false, true, true, SingleSpc, 4, 1 ,false},
244 { ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,false},
245 { ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed, false, true, false, SingleSpc, 3, 1 ,false},
246 { ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register, false, true, true, SingleSpc, 3, 1 ,false},
248 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, false, SingleSpc, 2, 4 ,true},
249 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true, SingleSpc, 2, 4 ,true},
250 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, false, SingleSpc, 2, 2 ,true},
251 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, true, SingleSpc, 2, 2 ,true},
252 { ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, false, SingleSpc, 2, 8 ,true},
253 { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, true, SingleSpc, 2, 8 ,true},
254 { ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, false, EvenDblSpc, 2, 4,true},
255 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, true, EvenDblSpc, 2, 4,true},
256 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, false, EvenDblSpc, 2, 2,true},
257 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, true, EvenDblSpc, 2, 2,true},
259 { ARM::VST2q16Pseudo, ARM::VST2q16, false, false, false, SingleSpc, 4, 4 ,false},
260 { ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed, false, true, false, SingleSpc, 4, 4 ,false},
261 { ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register, false, true, true, SingleSpc, 4, 4 ,false},
262 { ARM::VST2q32Pseudo, ARM::VST2q32, false, false, false, SingleSpc, 4, 2 ,false},
263 { ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed, false, true, false, SingleSpc, 4, 2 ,false},
264 { ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register, false, true, true, SingleSpc, 4, 2 ,false},
265 { ARM::VST2q8Pseudo, ARM::VST2q8, false, false, false, SingleSpc, 4, 8 ,false},
266 { ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed, false, true, false, SingleSpc, 4, 8 ,false},
267 { ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register, false, true, true, SingleSpc, 4, 8 ,false},
269 { ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, false, SingleSpc, 3, 4 ,true},
270 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
271 { ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, false, SingleSpc, 3, 2 ,true},
272 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
273 { ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, false, SingleSpc, 3, 8 ,true},
274 { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
275 { ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, false, EvenDblSpc, 3, 4,true},
276 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, true, EvenDblSpc, 3, 4,true},
277 { ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, false, EvenDblSpc, 3, 2,true},
278 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, true, EvenDblSpc, 3, 2,true},
280 { ARM::VST3d16Pseudo, ARM::VST3d16, false, false, false, SingleSpc, 3, 4 ,true},
281 { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
282 { ARM::VST3d32Pseudo, ARM::VST3d32, false, false, false, SingleSpc, 3, 2 ,true},
283 { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
284 { ARM::VST3d8Pseudo, ARM::VST3d8, false, false, false, SingleSpc, 3, 8 ,true},
285 { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
287 { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, true, EvenDblSpc, 3, 4 ,true},
288 { ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, false, OddDblSpc, 3, 4 ,true},
289 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, true, OddDblSpc, 3, 4 ,true},
290 { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, true, EvenDblSpc, 3, 2 ,true},
291 { ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, false, OddDblSpc, 3, 2 ,true},
292 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, true, OddDblSpc, 3, 2 ,true},
293 { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, true, EvenDblSpc, 3, 8 ,true},
294 { ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, false, OddDblSpc, 3, 8 ,true},
295 { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, true, OddDblSpc, 3, 8 ,true},
297 { ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, false, SingleSpc, 4, 4 ,true},
298 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
299 { ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, false, SingleSpc, 4, 2 ,true},
300 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
301 { ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, false, SingleSpc, 4, 8 ,true},
302 { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
303 { ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, false, EvenDblSpc, 4, 4,true},
304 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, true, EvenDblSpc, 4, 4,true},
305 { ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, false, EvenDblSpc, 4, 2,true},
306 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, true, EvenDblSpc, 4, 2,true},
308 { ARM::VST4d16Pseudo, ARM::VST4d16, false, false, false, SingleSpc, 4, 4 ,true},
309 { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
310 { ARM::VST4d32Pseudo, ARM::VST4d32, false, false, false, SingleSpc, 4, 2 ,true},
311 { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
312 { ARM::VST4d8Pseudo, ARM::VST4d8, false, false, false, SingleSpc, 4, 8 ,true},
313 { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
315 { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, true, EvenDblSpc, 4, 4 ,true},
316 { ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, false, OddDblSpc, 4, 4 ,true},
317 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, true, OddDblSpc, 4, 4 ,true},
318 { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, true, EvenDblSpc, 4, 2 ,true},
319 { ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, false, OddDblSpc, 4, 2 ,true},
320 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, true, OddDblSpc, 4, 2 ,true},
321 { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, true, EvenDblSpc, 4, 8 ,true},
322 { ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, false, OddDblSpc, 4, 8 ,true},
323 { ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, true, OddDblSpc, 4, 8 ,true}
326 /// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON
327 /// load or store pseudo instruction.
328 static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) {
329 const unsigned NumEntries = array_lengthof(NEONLdStTable);
332 // Make sure the table is sorted.
333 static bool TableChecked = false;
335 for (unsigned i = 0; i != NumEntries-1; ++i)
336 assert(NEONLdStTable[i] < NEONLdStTable[i+1] &&
337 "NEONLdStTable is not sorted!");
342 const NEONLdStTableEntry *I =
343 std::lower_bound(NEONLdStTable, NEONLdStTable + NumEntries, Opcode);
344 if (I != NEONLdStTable + NumEntries && I->PseudoOpc == Opcode)
349 /// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register,
350 /// corresponding to the specified register spacing. Not all of the results
351 /// are necessarily valid, e.g., a Q register only has 2 D subregisters.
352 static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc,
353 const TargetRegisterInfo *TRI, unsigned &D0,
354 unsigned &D1, unsigned &D2, unsigned &D3) {
355 if (RegSpc == SingleSpc) {
356 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
357 D1 = TRI->getSubReg(Reg, ARM::dsub_1);
358 D2 = TRI->getSubReg(Reg, ARM::dsub_2);
359 D3 = TRI->getSubReg(Reg, ARM::dsub_3);
360 } else if (RegSpc == EvenDblSpc) {
361 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
362 D1 = TRI->getSubReg(Reg, ARM::dsub_2);
363 D2 = TRI->getSubReg(Reg, ARM::dsub_4);
364 D3 = TRI->getSubReg(Reg, ARM::dsub_6);
366 assert(RegSpc == OddDblSpc && "unknown register spacing");
367 D0 = TRI->getSubReg(Reg, ARM::dsub_1);
368 D1 = TRI->getSubReg(Reg, ARM::dsub_3);
369 D2 = TRI->getSubReg(Reg, ARM::dsub_5);
370 D3 = TRI->getSubReg(Reg, ARM::dsub_7);
374 /// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register
375 /// operands to real VLD instructions with D register operands.
376 void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
377 MachineInstr &MI = *MBBI;
378 MachineBasicBlock &MBB = *MI.getParent();
380 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
381 assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed");
382 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
383 unsigned NumRegs = TableEntry->NumRegs;
385 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
386 TII->get(TableEntry->RealOpc));
389 bool DstIsDead = MI.getOperand(OpIdx).isDead();
390 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
391 unsigned D0, D1, D2, D3;
392 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
393 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
394 if (NumRegs > 1 && TableEntry->copyAllListRegs)
395 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
396 if (NumRegs > 2 && TableEntry->copyAllListRegs)
397 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
398 if (NumRegs > 3 && TableEntry->copyAllListRegs)
399 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
401 if (TableEntry->isUpdating)
402 MIB.addOperand(MI.getOperand(OpIdx++));
404 // Copy the addrmode6 operands.
405 MIB.addOperand(MI.getOperand(OpIdx++));
406 MIB.addOperand(MI.getOperand(OpIdx++));
407 // Copy the am6offset operand.
408 if (TableEntry->hasWritebackOperand)
409 MIB.addOperand(MI.getOperand(OpIdx++));
411 // For an instruction writing double-spaced subregs, the pseudo instruction
412 // has an extra operand that is a use of the super-register. Record the
413 // operand index and skip over it.
414 unsigned SrcOpIdx = 0;
415 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc)
418 // Copy the predicate operands.
419 MIB.addOperand(MI.getOperand(OpIdx++));
420 MIB.addOperand(MI.getOperand(OpIdx++));
422 // Copy the super-register source operand used for double-spaced subregs over
423 // to the new instruction as an implicit operand.
425 MachineOperand MO = MI.getOperand(SrcOpIdx);
426 MO.setImplicit(true);
429 // Add an implicit def for the super-register.
430 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
431 TransferImpOps(MI, MIB, MIB);
433 // Transfer memoperands.
434 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
436 MI.eraseFromParent();
439 /// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register
440 /// operands to real VST instructions with D register operands.
441 void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
442 MachineInstr &MI = *MBBI;
443 MachineBasicBlock &MBB = *MI.getParent();
445 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
446 assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed");
447 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
448 unsigned NumRegs = TableEntry->NumRegs;
450 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
451 TII->get(TableEntry->RealOpc));
453 if (TableEntry->isUpdating)
454 MIB.addOperand(MI.getOperand(OpIdx++));
456 // Copy the addrmode6 operands.
457 MIB.addOperand(MI.getOperand(OpIdx++));
458 MIB.addOperand(MI.getOperand(OpIdx++));
459 // Copy the am6offset operand.
460 if (TableEntry->hasWritebackOperand)
461 MIB.addOperand(MI.getOperand(OpIdx++));
463 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
464 bool SrcIsUndef = MI.getOperand(OpIdx).isUndef();
465 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
466 unsigned D0, D1, D2, D3;
467 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
468 MIB.addReg(D0, getUndefRegState(SrcIsUndef));
469 if (NumRegs > 1 && TableEntry->copyAllListRegs)
470 MIB.addReg(D1, getUndefRegState(SrcIsUndef));
471 if (NumRegs > 2 && TableEntry->copyAllListRegs)
472 MIB.addReg(D2, getUndefRegState(SrcIsUndef));
473 if (NumRegs > 3 && TableEntry->copyAllListRegs)
474 MIB.addReg(D3, getUndefRegState(SrcIsUndef));
476 // Copy the predicate operands.
477 MIB.addOperand(MI.getOperand(OpIdx++));
478 MIB.addOperand(MI.getOperand(OpIdx++));
480 if (SrcIsKill && !SrcIsUndef) // Add an implicit kill for the super-reg.
481 MIB->addRegisterKilled(SrcReg, TRI, true);
482 else if (!SrcIsUndef)
483 MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg.
484 TransferImpOps(MI, MIB, MIB);
486 // Transfer memoperands.
487 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
489 MI.eraseFromParent();
492 /// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ
493 /// register operands to real instructions with D register operands.
494 void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
495 MachineInstr &MI = *MBBI;
496 MachineBasicBlock &MBB = *MI.getParent();
498 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
499 assert(TableEntry && "NEONLdStTable lookup failed");
500 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
501 unsigned NumRegs = TableEntry->NumRegs;
502 unsigned RegElts = TableEntry->RegElts;
504 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
505 TII->get(TableEntry->RealOpc));
507 // The lane operand is always the 3rd from last operand, before the 2
508 // predicate operands.
509 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
511 // Adjust the lane and spacing as needed for Q registers.
512 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane");
513 if (RegSpc == EvenDblSpc && Lane >= RegElts) {
517 assert(Lane < RegElts && "out of range lane for VLD/VST-lane");
519 unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0;
521 bool DstIsDead = false;
522 if (TableEntry->IsLoad) {
523 DstIsDead = MI.getOperand(OpIdx).isDead();
524 DstReg = MI.getOperand(OpIdx++).getReg();
525 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
526 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
528 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
530 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
532 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
535 if (TableEntry->isUpdating)
536 MIB.addOperand(MI.getOperand(OpIdx++));
538 // Copy the addrmode6 operands.
539 MIB.addOperand(MI.getOperand(OpIdx++));
540 MIB.addOperand(MI.getOperand(OpIdx++));
541 // Copy the am6offset operand.
542 if (TableEntry->hasWritebackOperand)
543 MIB.addOperand(MI.getOperand(OpIdx++));
545 // Grab the super-register source.
546 MachineOperand MO = MI.getOperand(OpIdx++);
547 if (!TableEntry->IsLoad)
548 GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3);
550 // Add the subregs as sources of the new instruction.
551 unsigned SrcFlags = (getUndefRegState(MO.isUndef()) |
552 getKillRegState(MO.isKill()));
553 MIB.addReg(D0, SrcFlags);
555 MIB.addReg(D1, SrcFlags);
557 MIB.addReg(D2, SrcFlags);
559 MIB.addReg(D3, SrcFlags);
561 // Add the lane number operand.
565 // Copy the predicate operands.
566 MIB.addOperand(MI.getOperand(OpIdx++));
567 MIB.addOperand(MI.getOperand(OpIdx++));
569 // Copy the super-register source to be an implicit source.
570 MO.setImplicit(true);
572 if (TableEntry->IsLoad)
573 // Add an implicit def for the super-register.
574 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
575 TransferImpOps(MI, MIB, MIB);
576 // Transfer memoperands.
577 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
578 MI.eraseFromParent();
581 /// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ
582 /// register operands to real instructions with D register operands.
583 void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
584 unsigned Opc, bool IsExt) {
585 MachineInstr &MI = *MBBI;
586 MachineBasicBlock &MBB = *MI.getParent();
588 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
591 // Transfer the destination register operand.
592 MIB.addOperand(MI.getOperand(OpIdx++));
594 MIB.addOperand(MI.getOperand(OpIdx++));
596 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
597 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
598 unsigned D0, D1, D2, D3;
599 GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
602 // Copy the other source register operand.
603 MIB.addOperand(MI.getOperand(OpIdx++));
605 // Copy the predicate operands.
606 MIB.addOperand(MI.getOperand(OpIdx++));
607 MIB.addOperand(MI.getOperand(OpIdx++));
609 // Add an implicit kill and use for the super-reg.
610 MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill));
611 TransferImpOps(MI, MIB, MIB);
612 MI.eraseFromParent();
615 void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
616 MachineBasicBlock::iterator &MBBI) {
617 MachineInstr &MI = *MBBI;
618 unsigned Opcode = MI.getOpcode();
619 unsigned PredReg = 0;
620 ARMCC::CondCodes Pred = getInstrPredicate(&MI, PredReg);
621 unsigned DstReg = MI.getOperand(0).getReg();
622 bool DstIsDead = MI.getOperand(0).isDead();
623 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
624 const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1);
625 MachineInstrBuilder LO16, HI16;
627 if (!STI->hasV6T2Ops() &&
628 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) {
629 // Expand into a movi + orr.
630 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
631 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
632 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
635 assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!");
636 unsigned ImmVal = (unsigned)MO.getImm();
637 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
638 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
639 LO16 = LO16.addImm(SOImmValV1);
640 HI16 = HI16.addImm(SOImmValV2);
641 LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
642 HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
643 LO16.addImm(Pred).addReg(PredReg).addReg(0);
644 HI16.addImm(Pred).addReg(PredReg).addReg(0);
645 TransferImpOps(MI, LO16, HI16);
646 MI.eraseFromParent();
650 unsigned LO16Opc = 0;
651 unsigned HI16Opc = 0;
652 if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) {
653 LO16Opc = ARM::t2MOVi16;
654 HI16Opc = ARM::t2MOVTi16;
656 LO16Opc = ARM::MOVi16;
657 HI16Opc = ARM::MOVTi16;
660 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg);
661 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc))
662 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
666 unsigned Imm = MO.getImm();
667 unsigned Lo16 = Imm & 0xffff;
668 unsigned Hi16 = (Imm >> 16) & 0xffff;
669 LO16 = LO16.addImm(Lo16);
670 HI16 = HI16.addImm(Hi16);
672 const GlobalValue *GV = MO.getGlobal();
673 unsigned TF = MO.getTargetFlags();
674 LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16);
675 HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16);
678 LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
679 HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
680 LO16.addImm(Pred).addReg(PredReg);
681 HI16.addImm(Pred).addReg(PredReg);
683 TransferImpOps(MI, LO16, HI16);
684 MI.eraseFromParent();
687 bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
688 MachineBasicBlock::iterator MBBI) {
689 MachineInstr &MI = *MBBI;
690 unsigned Opcode = MI.getOpcode();
696 unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD;
697 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc),
698 MI.getOperand(1).getReg())
699 .addOperand(MI.getOperand(2))
700 .addImm(MI.getOperand(3).getImm()) // 'pred'
701 .addOperand(MI.getOperand(4));
703 MI.eraseFromParent();
708 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr;
709 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
710 MI.getOperand(1).getReg())
711 .addOperand(MI.getOperand(2))
712 .addImm(MI.getOperand(3).getImm()) // 'pred'
713 .addOperand(MI.getOperand(4))
714 .addReg(0); // 's' bit
716 MI.eraseFromParent();
720 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
721 (MI.getOperand(1).getReg()))
722 .addOperand(MI.getOperand(2))
723 .addImm(MI.getOperand(3).getImm())
724 .addImm(MI.getOperand(4).getImm()) // 'pred'
725 .addOperand(MI.getOperand(5))
726 .addReg(0); // 's' bit
728 MI.eraseFromParent();
732 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr),
733 (MI.getOperand(1).getReg()))
734 .addOperand(MI.getOperand(2))
735 .addOperand(MI.getOperand(3))
736 .addImm(MI.getOperand(4).getImm())
737 .addImm(MI.getOperand(5).getImm()) // 'pred'
738 .addOperand(MI.getOperand(6))
739 .addReg(0); // 's' bit
741 MI.eraseFromParent();
744 case ARM::t2MOVCCi16:
745 case ARM::MOVCCi16: {
746 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16;
747 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
748 MI.getOperand(1).getReg())
749 .addImm(MI.getOperand(2).getImm())
750 .addImm(MI.getOperand(3).getImm()) // 'pred'
751 .addOperand(MI.getOperand(4));
752 MI.eraseFromParent();
757 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi;
758 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
759 MI.getOperand(1).getReg())
760 .addImm(MI.getOperand(2).getImm())
761 .addImm(MI.getOperand(3).getImm()) // 'pred'
762 .addOperand(MI.getOperand(4))
763 .addReg(0); // 's' bit
765 MI.eraseFromParent();
770 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi;
771 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
772 MI.getOperand(1).getReg())
773 .addImm(MI.getOperand(2).getImm())
774 .addImm(MI.getOperand(3).getImm()) // 'pred'
775 .addOperand(MI.getOperand(4))
776 .addReg(0); // 's' bit
778 MI.eraseFromParent();
781 case ARM::t2MOVCClsl:
782 case ARM::t2MOVCClsr:
783 case ARM::t2MOVCCasr:
784 case ARM::t2MOVCCror: {
787 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break;
788 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break;
789 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break;
790 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break;
791 default: llvm_unreachable("unexpeced conditional move");
793 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
794 MI.getOperand(1).getReg())
795 .addOperand(MI.getOperand(2))
796 .addImm(MI.getOperand(3).getImm())
797 .addImm(MI.getOperand(4).getImm()) // 'pred'
798 .addOperand(MI.getOperand(5))
799 .addReg(0); // 's' bit
800 MI.eraseFromParent();
803 case ARM::Int_eh_sjlj_dispatchsetup: {
804 MachineFunction &MF = *MI.getParent()->getParent();
805 const ARMBaseInstrInfo *AII =
806 static_cast<const ARMBaseInstrInfo*>(TII);
807 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
808 // For functions using a base pointer, we rematerialize it (via the frame
809 // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it
810 // for us. Otherwise, expand to nothing.
811 if (RI.hasBasePointer(MF)) {
812 int32_t NumBytes = AFI->getFramePtrSpillOffset();
813 unsigned FramePtr = RI.getFrameRegister(MF);
814 assert(MF.getTarget().getFrameLowering()->hasFP(MF) &&
815 "base pointer without frame pointer?");
817 if (AFI->isThumb2Function()) {
818 emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
819 FramePtr, -NumBytes, ARMCC::AL, 0, *TII);
820 } else if (AFI->isThumbFunction()) {
821 emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
822 FramePtr, -NumBytes, *TII, RI);
824 emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
825 FramePtr, -NumBytes, ARMCC::AL, 0,
828 // If there's dynamic realignment, adjust for it.
829 if (RI.needsStackRealignment(MF)) {
830 MachineFrameInfo *MFI = MF.getFrameInfo();
831 unsigned MaxAlign = MFI->getMaxAlignment();
832 assert (!AFI->isThumb1OnlyFunction());
833 // Emit bic r6, r6, MaxAlign
834 unsigned bicOpc = AFI->isThumbFunction() ?
835 ARM::t2BICri : ARM::BICri;
836 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
837 TII->get(bicOpc), ARM::R6)
838 .addReg(ARM::R6, RegState::Kill)
839 .addImm(MaxAlign-1)));
843 MI.eraseFromParent();
847 case ARM::MOVsrl_flag:
848 case ARM::MOVsra_flag: {
849 // These are just fancy MOVs instructions.
850 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
851 MI.getOperand(0).getReg())
852 .addOperand(MI.getOperand(1))
853 .addImm(ARM_AM::getSORegOpc((Opcode == ARM::MOVsrl_flag ?
854 ARM_AM::lsr : ARM_AM::asr),
856 .addReg(ARM::CPSR, RegState::Define);
857 MI.eraseFromParent();
861 // This encodes as "MOVs Rd, Rm, rrx
862 MachineInstrBuilder MIB =
863 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),TII->get(ARM::MOVsi),
864 MI.getOperand(0).getReg())
865 .addOperand(MI.getOperand(1))
866 .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0)))
868 TransferImpOps(MI, MIB, MIB);
869 MI.eraseFromParent();
874 MachineInstrBuilder MIB =
875 BuildMI(MBB, MBBI, MI.getDebugLoc(),
876 TII->get(Opcode == ARM::tTPsoft ? ARM::tBL : ARM::BL))
877 .addExternalSymbol("__aeabi_read_tp", 0);
879 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
880 TransferImpOps(MI, MIB, MIB);
881 MI.eraseFromParent();
884 case ARM::tLDRpci_pic:
885 case ARM::t2LDRpci_pic: {
886 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
887 ? ARM::tLDRpci : ARM::t2LDRpci;
888 unsigned DstReg = MI.getOperand(0).getReg();
889 bool DstIsDead = MI.getOperand(0).isDead();
890 MachineInstrBuilder MIB1 =
891 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
892 TII->get(NewLdOpc), DstReg)
893 .addOperand(MI.getOperand(1)));
894 MIB1->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
895 MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
896 TII->get(ARM::tPICADD))
897 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
899 .addOperand(MI.getOperand(2));
900 TransferImpOps(MI, MIB1, MIB2);
901 MI.eraseFromParent();
905 case ARM::LDRLIT_ga_abs:
906 case ARM::LDRLIT_ga_pcrel:
907 case ARM::LDRLIT_ga_pcrel_ldr:
908 case ARM::tLDRLIT_ga_abs:
909 case ARM::tLDRLIT_ga_pcrel: {
910 unsigned DstReg = MI.getOperand(0).getReg();
911 bool DstIsDead = MI.getOperand(0).isDead();
912 const MachineOperand &MO1 = MI.getOperand(1);
913 const GlobalValue *GV = MO1.getGlobal();
915 Opcode != ARM::tLDRLIT_ga_pcrel && Opcode != ARM::tLDRLIT_ga_abs;
917 Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs;
918 unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci;
921 ? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICADD : ARM::PICLDR)
924 // We need a new const-pool entry to load from.
925 MachineConstantPool *MCP = MBB.getParent()->getConstantPool();
926 unsigned ARMPCLabelIndex = 0;
927 MachineConstantPoolValue *CPV;
930 unsigned PCAdj = IsARM ? 8 : 4;
931 ARMPCLabelIndex = AFI->createPICLabelUId();
932 CPV = ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex,
933 ARMCP::CPValue, PCAdj);
935 CPV = ARMConstantPoolConstant::Create(GV, ARMCP::no_modifier);
937 MachineInstrBuilder MIB =
938 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LDRLITOpc), DstReg)
939 .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, 4));
945 MachineInstrBuilder MIB =
946 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(PICAddOpc))
947 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
949 .addImm(ARMPCLabelIndex);
955 MI.eraseFromParent();
958 case ARM::MOV_ga_pcrel:
959 case ARM::MOV_ga_pcrel_ldr:
960 case ARM::t2MOV_ga_pcrel: {
961 // Expand into movw + movw. Also "add pc" / ldr [pc] in PIC mode.
962 unsigned LabelId = AFI->createPICLabelUId();
963 unsigned DstReg = MI.getOperand(0).getReg();
964 bool DstIsDead = MI.getOperand(0).isDead();
965 const MachineOperand &MO1 = MI.getOperand(1);
966 const GlobalValue *GV = MO1.getGlobal();
967 unsigned TF = MO1.getTargetFlags();
968 bool isARM = Opcode != ARM::t2MOV_ga_pcrel;
969 unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel;
970 unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel;
971 unsigned LO16TF = TF | ARMII::MO_LO16;
972 unsigned HI16TF = TF | ARMII::MO_HI16;
973 unsigned PICAddOpc = isARM
974 ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
976 MachineInstrBuilder MIB1 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
977 TII->get(LO16Opc), DstReg)
978 .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF)
981 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc), DstReg)
983 .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF)
986 MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
988 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
989 .addReg(DstReg).addImm(LabelId);
991 AddDefaultPred(MIB3);
992 if (Opcode == ARM::MOV_ga_pcrel_ldr)
993 MIB3->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
995 TransferImpOps(MI, MIB1, MIB3);
996 MI.eraseFromParent();
1000 case ARM::MOVi32imm:
1001 case ARM::MOVCCi32imm:
1002 case ARM::t2MOVi32imm:
1003 case ARM::t2MOVCCi32imm:
1004 ExpandMOV32BitImm(MBB, MBBI);
1007 case ARM::SUBS_PC_LR: {
1008 MachineInstrBuilder MIB =
1009 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC)
1011 .addOperand(MI.getOperand(0))
1012 .addOperand(MI.getOperand(1))
1013 .addOperand(MI.getOperand(2))
1014 .addReg(ARM::CPSR, RegState::Undef);
1015 TransferImpOps(MI, MIB, MIB);
1016 MI.eraseFromParent();
1019 case ARM::VLDMQIA: {
1020 unsigned NewOpc = ARM::VLDMDIA;
1021 MachineInstrBuilder MIB =
1022 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1025 // Grab the Q register destination.
1026 bool DstIsDead = MI.getOperand(OpIdx).isDead();
1027 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
1029 // Copy the source register.
1030 MIB.addOperand(MI.getOperand(OpIdx++));
1032 // Copy the predicate operands.
1033 MIB.addOperand(MI.getOperand(OpIdx++));
1034 MIB.addOperand(MI.getOperand(OpIdx++));
1036 // Add the destination operands (D subregs).
1037 unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0);
1038 unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1);
1039 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
1040 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
1042 // Add an implicit def for the super-register.
1043 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
1044 TransferImpOps(MI, MIB, MIB);
1045 MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1046 MI.eraseFromParent();
1050 case ARM::VSTMQIA: {
1051 unsigned NewOpc = ARM::VSTMDIA;
1052 MachineInstrBuilder MIB =
1053 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1056 // Grab the Q register source.
1057 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
1058 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
1060 // Copy the destination register.
1061 MIB.addOperand(MI.getOperand(OpIdx++));
1063 // Copy the predicate operands.
1064 MIB.addOperand(MI.getOperand(OpIdx++));
1065 MIB.addOperand(MI.getOperand(OpIdx++));
1067 // Add the source operands (D subregs).
1068 unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
1069 unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
1070 MIB.addReg(D0).addReg(D1);
1072 if (SrcIsKill) // Add an implicit kill for the Q register.
1073 MIB->addRegisterKilled(SrcReg, TRI, true);
1075 TransferImpOps(MI, MIB, MIB);
1076 MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1077 MI.eraseFromParent();
1082 unsigned NewOpc = Opcode == ARM::VDUPfqf ? ARM::VDUPLN32q :
1084 MachineInstrBuilder MIB =
1085 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1087 unsigned SrcReg = MI.getOperand(1).getReg();
1088 unsigned Lane = TRI->getEncodingValue(SrcReg) & 1;
1089 unsigned DReg = TRI->getMatchingSuperReg(SrcReg,
1090 Lane & 1 ? ARM::ssub_1 : ARM::ssub_0,
1091 &ARM::DPR_VFP2RegClass);
1092 // The lane is [0,1] for the containing DReg superregister.
1093 // Copy the dst/src register operands.
1094 MIB.addOperand(MI.getOperand(OpIdx++));
1097 // Add the lane select operand.
1099 // Add the predicate operands.
1100 MIB.addOperand(MI.getOperand(OpIdx++));
1101 MIB.addOperand(MI.getOperand(OpIdx++));
1103 TransferImpOps(MI, MIB, MIB);
1104 MI.eraseFromParent();
1108 case ARM::VLD2q8Pseudo:
1109 case ARM::VLD2q16Pseudo:
1110 case ARM::VLD2q32Pseudo:
1111 case ARM::VLD2q8PseudoWB_fixed:
1112 case ARM::VLD2q16PseudoWB_fixed:
1113 case ARM::VLD2q32PseudoWB_fixed:
1114 case ARM::VLD2q8PseudoWB_register:
1115 case ARM::VLD2q16PseudoWB_register:
1116 case ARM::VLD2q32PseudoWB_register:
1117 case ARM::VLD3d8Pseudo:
1118 case ARM::VLD3d16Pseudo:
1119 case ARM::VLD3d32Pseudo:
1120 case ARM::VLD1d64TPseudo:
1121 case ARM::VLD3d8Pseudo_UPD:
1122 case ARM::VLD3d16Pseudo_UPD:
1123 case ARM::VLD3d32Pseudo_UPD:
1124 case ARM::VLD3q8Pseudo_UPD:
1125 case ARM::VLD3q16Pseudo_UPD:
1126 case ARM::VLD3q32Pseudo_UPD:
1127 case ARM::VLD3q8oddPseudo:
1128 case ARM::VLD3q16oddPseudo:
1129 case ARM::VLD3q32oddPseudo:
1130 case ARM::VLD3q8oddPseudo_UPD:
1131 case ARM::VLD3q16oddPseudo_UPD:
1132 case ARM::VLD3q32oddPseudo_UPD:
1133 case ARM::VLD4d8Pseudo:
1134 case ARM::VLD4d16Pseudo:
1135 case ARM::VLD4d32Pseudo:
1136 case ARM::VLD1d64QPseudo:
1137 case ARM::VLD4d8Pseudo_UPD:
1138 case ARM::VLD4d16Pseudo_UPD:
1139 case ARM::VLD4d32Pseudo_UPD:
1140 case ARM::VLD4q8Pseudo_UPD:
1141 case ARM::VLD4q16Pseudo_UPD:
1142 case ARM::VLD4q32Pseudo_UPD:
1143 case ARM::VLD4q8oddPseudo:
1144 case ARM::VLD4q16oddPseudo:
1145 case ARM::VLD4q32oddPseudo:
1146 case ARM::VLD4q8oddPseudo_UPD:
1147 case ARM::VLD4q16oddPseudo_UPD:
1148 case ARM::VLD4q32oddPseudo_UPD:
1149 case ARM::VLD3DUPd8Pseudo:
1150 case ARM::VLD3DUPd16Pseudo:
1151 case ARM::VLD3DUPd32Pseudo:
1152 case ARM::VLD3DUPd8Pseudo_UPD:
1153 case ARM::VLD3DUPd16Pseudo_UPD:
1154 case ARM::VLD3DUPd32Pseudo_UPD:
1155 case ARM::VLD4DUPd8Pseudo:
1156 case ARM::VLD4DUPd16Pseudo:
1157 case ARM::VLD4DUPd32Pseudo:
1158 case ARM::VLD4DUPd8Pseudo_UPD:
1159 case ARM::VLD4DUPd16Pseudo_UPD:
1160 case ARM::VLD4DUPd32Pseudo_UPD:
1164 case ARM::VST2q8Pseudo:
1165 case ARM::VST2q16Pseudo:
1166 case ARM::VST2q32Pseudo:
1167 case ARM::VST2q8PseudoWB_fixed:
1168 case ARM::VST2q16PseudoWB_fixed:
1169 case ARM::VST2q32PseudoWB_fixed:
1170 case ARM::VST2q8PseudoWB_register:
1171 case ARM::VST2q16PseudoWB_register:
1172 case ARM::VST2q32PseudoWB_register:
1173 case ARM::VST3d8Pseudo:
1174 case ARM::VST3d16Pseudo:
1175 case ARM::VST3d32Pseudo:
1176 case ARM::VST1d64TPseudo:
1177 case ARM::VST3d8Pseudo_UPD:
1178 case ARM::VST3d16Pseudo_UPD:
1179 case ARM::VST3d32Pseudo_UPD:
1180 case ARM::VST1d64TPseudoWB_fixed:
1181 case ARM::VST1d64TPseudoWB_register:
1182 case ARM::VST3q8Pseudo_UPD:
1183 case ARM::VST3q16Pseudo_UPD:
1184 case ARM::VST3q32Pseudo_UPD:
1185 case ARM::VST3q8oddPseudo:
1186 case ARM::VST3q16oddPseudo:
1187 case ARM::VST3q32oddPseudo:
1188 case ARM::VST3q8oddPseudo_UPD:
1189 case ARM::VST3q16oddPseudo_UPD:
1190 case ARM::VST3q32oddPseudo_UPD:
1191 case ARM::VST4d8Pseudo:
1192 case ARM::VST4d16Pseudo:
1193 case ARM::VST4d32Pseudo:
1194 case ARM::VST1d64QPseudo:
1195 case ARM::VST4d8Pseudo_UPD:
1196 case ARM::VST4d16Pseudo_UPD:
1197 case ARM::VST4d32Pseudo_UPD:
1198 case ARM::VST1d64QPseudoWB_fixed:
1199 case ARM::VST1d64QPseudoWB_register:
1200 case ARM::VST4q8Pseudo_UPD:
1201 case ARM::VST4q16Pseudo_UPD:
1202 case ARM::VST4q32Pseudo_UPD:
1203 case ARM::VST4q8oddPseudo:
1204 case ARM::VST4q16oddPseudo:
1205 case ARM::VST4q32oddPseudo:
1206 case ARM::VST4q8oddPseudo_UPD:
1207 case ARM::VST4q16oddPseudo_UPD:
1208 case ARM::VST4q32oddPseudo_UPD:
1212 case ARM::VLD1LNq8Pseudo:
1213 case ARM::VLD1LNq16Pseudo:
1214 case ARM::VLD1LNq32Pseudo:
1215 case ARM::VLD1LNq8Pseudo_UPD:
1216 case ARM::VLD1LNq16Pseudo_UPD:
1217 case ARM::VLD1LNq32Pseudo_UPD:
1218 case ARM::VLD2LNd8Pseudo:
1219 case ARM::VLD2LNd16Pseudo:
1220 case ARM::VLD2LNd32Pseudo:
1221 case ARM::VLD2LNq16Pseudo:
1222 case ARM::VLD2LNq32Pseudo:
1223 case ARM::VLD2LNd8Pseudo_UPD:
1224 case ARM::VLD2LNd16Pseudo_UPD:
1225 case ARM::VLD2LNd32Pseudo_UPD:
1226 case ARM::VLD2LNq16Pseudo_UPD:
1227 case ARM::VLD2LNq32Pseudo_UPD:
1228 case ARM::VLD3LNd8Pseudo:
1229 case ARM::VLD3LNd16Pseudo:
1230 case ARM::VLD3LNd32Pseudo:
1231 case ARM::VLD3LNq16Pseudo:
1232 case ARM::VLD3LNq32Pseudo:
1233 case ARM::VLD3LNd8Pseudo_UPD:
1234 case ARM::VLD3LNd16Pseudo_UPD:
1235 case ARM::VLD3LNd32Pseudo_UPD:
1236 case ARM::VLD3LNq16Pseudo_UPD:
1237 case ARM::VLD3LNq32Pseudo_UPD:
1238 case ARM::VLD4LNd8Pseudo:
1239 case ARM::VLD4LNd16Pseudo:
1240 case ARM::VLD4LNd32Pseudo:
1241 case ARM::VLD4LNq16Pseudo:
1242 case ARM::VLD4LNq32Pseudo:
1243 case ARM::VLD4LNd8Pseudo_UPD:
1244 case ARM::VLD4LNd16Pseudo_UPD:
1245 case ARM::VLD4LNd32Pseudo_UPD:
1246 case ARM::VLD4LNq16Pseudo_UPD:
1247 case ARM::VLD4LNq32Pseudo_UPD:
1248 case ARM::VST1LNq8Pseudo:
1249 case ARM::VST1LNq16Pseudo:
1250 case ARM::VST1LNq32Pseudo:
1251 case ARM::VST1LNq8Pseudo_UPD:
1252 case ARM::VST1LNq16Pseudo_UPD:
1253 case ARM::VST1LNq32Pseudo_UPD:
1254 case ARM::VST2LNd8Pseudo:
1255 case ARM::VST2LNd16Pseudo:
1256 case ARM::VST2LNd32Pseudo:
1257 case ARM::VST2LNq16Pseudo:
1258 case ARM::VST2LNq32Pseudo:
1259 case ARM::VST2LNd8Pseudo_UPD:
1260 case ARM::VST2LNd16Pseudo_UPD:
1261 case ARM::VST2LNd32Pseudo_UPD:
1262 case ARM::VST2LNq16Pseudo_UPD:
1263 case ARM::VST2LNq32Pseudo_UPD:
1264 case ARM::VST3LNd8Pseudo:
1265 case ARM::VST3LNd16Pseudo:
1266 case ARM::VST3LNd32Pseudo:
1267 case ARM::VST3LNq16Pseudo:
1268 case ARM::VST3LNq32Pseudo:
1269 case ARM::VST3LNd8Pseudo_UPD:
1270 case ARM::VST3LNd16Pseudo_UPD:
1271 case ARM::VST3LNd32Pseudo_UPD:
1272 case ARM::VST3LNq16Pseudo_UPD:
1273 case ARM::VST3LNq32Pseudo_UPD:
1274 case ARM::VST4LNd8Pseudo:
1275 case ARM::VST4LNd16Pseudo:
1276 case ARM::VST4LNd32Pseudo:
1277 case ARM::VST4LNq16Pseudo:
1278 case ARM::VST4LNq32Pseudo:
1279 case ARM::VST4LNd8Pseudo_UPD:
1280 case ARM::VST4LNd16Pseudo_UPD:
1281 case ARM::VST4LNd32Pseudo_UPD:
1282 case ARM::VST4LNq16Pseudo_UPD:
1283 case ARM::VST4LNq32Pseudo_UPD:
1287 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true;
1288 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true;
1289 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true;
1290 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true;
1294 bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
1295 bool Modified = false;
1297 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
1299 MachineBasicBlock::iterator NMBBI = llvm::next(MBBI);
1300 Modified |= ExpandMI(MBB, MBBI);
1307 bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
1308 const TargetMachine &TM = MF.getTarget();
1309 TII = static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo());
1310 TRI = TM.getRegisterInfo();
1311 STI = &TM.getSubtarget<ARMSubtarget>();
1312 AFI = MF.getInfo<ARMFunctionInfo>();
1314 bool Modified = false;
1315 for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
1317 Modified |= ExpandMBB(*MFI);
1318 if (VerifyARMPseudo)
1319 MF.verify(this, "After expanding ARM pseudo instructions.");
1323 /// createARMExpandPseudoPass - returns an instance of the pseudo instruction
1325 FunctionPass *llvm::createARMExpandPseudoPass() {
1326 return new ARMExpandPseudo();