1 //===-- ARMConstantIslandPass.cpp - ARM constant islands --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a pass that splits the constant pool up into 'islands'
11 // which are scattered through-out the function. This is required due to the
12 // limited pc-relative displacements that ARM has.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "arm-cp-islands"
18 #include "ARMAddressingModes.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMInstrInfo.h"
21 #include "llvm/CodeGen/MachineConstantPool.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineJumpTableInfo.h"
25 #include "llvm/Target/TargetData.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/raw_ostream.h"
30 #include "llvm/ADT/SmallSet.h"
31 #include "llvm/ADT/SmallVector.h"
32 #include "llvm/ADT/STLExtras.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/Support/CommandLine.h"
38 STATISTIC(NumCPEs, "Number of constpool entries");
39 STATISTIC(NumSplit, "Number of uncond branches inserted");
40 STATISTIC(NumCBrFixed, "Number of cond branches fixed");
41 STATISTIC(NumUBrFixed, "Number of uncond branches fixed");
42 STATISTIC(NumTBs, "Number of table branches generated");
43 STATISTIC(NumT2CPShrunk, "Number of Thumb2 constantpool instructions shrunk");
44 STATISTIC(NumT2BrShrunk, "Number of Thumb2 immediate branches shrunk");
45 STATISTIC(NumCBZ, "Number of CBZ / CBNZ formed");
46 STATISTIC(NumJTMoved, "Number of jump table destination blocks moved");
47 STATISTIC(NumJTInserted, "Number of jump table intermediate blocks inserted");
51 AdjustJumpTableBlocks("arm-adjust-jump-tables", cl::Hidden, cl::init(true),
52 cl::desc("Adjust basic block layout to better use TB[BH]"));
55 /// ARMConstantIslands - Due to limited PC-relative displacements, ARM
56 /// requires constant pool entries to be scattered among the instructions
57 /// inside a function. To do this, it completely ignores the normal LLVM
58 /// constant pool; instead, it places constants wherever it feels like with
59 /// special instructions.
61 /// The terminology used in this pass includes:
62 /// Islands - Clumps of constants placed in the function.
63 /// Water - Potential places where an island could be formed.
64 /// CPE - A constant pool entry that has been placed somewhere, which
65 /// tracks a list of users.
66 class ARMConstantIslands : public MachineFunctionPass {
67 /// BBSizes - The size of each MachineBasicBlock in bytes of code, indexed
68 /// by MBB Number. The two-byte pads required for Thumb alignment are
69 /// counted as part of the following block (i.e., the offset and size for
70 /// a padded block will both be ==2 mod 4).
71 std::vector<unsigned> BBSizes;
73 /// BBOffsets - the offset of each MBB in bytes, starting from 0.
74 /// The two-byte pads required for Thumb alignment are counted as part of
75 /// the following block.
76 std::vector<unsigned> BBOffsets;
78 /// WaterList - A sorted list of basic blocks where islands could be placed
79 /// (i.e. blocks that don't fall through to the following block, due
80 /// to a return, unreachable, or unconditional branch).
81 std::vector<MachineBasicBlock*> WaterList;
83 /// NewWaterList - The subset of WaterList that was created since the
84 /// previous iteration by inserting unconditional branches.
85 SmallSet<MachineBasicBlock*, 4> NewWaterList;
87 typedef std::vector<MachineBasicBlock*>::iterator water_iterator;
89 /// CPUser - One user of a constant pool, keeping the machine instruction
90 /// pointer, the constant pool being referenced, and the max displacement
91 /// allowed from the instruction to the CP. The HighWaterMark records the
92 /// highest basic block where a new CPEntry can be placed. To ensure this
93 /// pass terminates, the CP entries are initially placed at the end of the
94 /// function and then move monotonically to lower addresses. The
95 /// exception to this rule is when the current CP entry for a particular
96 /// CPUser is out of range, but there is another CP entry for the same
97 /// constant value in range. We want to use the existing in-range CP
98 /// entry, but if it later moves out of range, the search for new water
99 /// should resume where it left off. The HighWaterMark is used to record
104 MachineBasicBlock *HighWaterMark;
108 CPUser(MachineInstr *mi, MachineInstr *cpemi, unsigned maxdisp,
109 bool neg, bool soimm)
110 : MI(mi), CPEMI(cpemi), MaxDisp(maxdisp), NegOk(neg), IsSoImm(soimm) {
111 HighWaterMark = CPEMI->getParent();
115 /// CPUsers - Keep track of all of the machine instructions that use various
116 /// constant pools and their max displacement.
117 std::vector<CPUser> CPUsers;
119 /// CPEntry - One per constant pool entry, keeping the machine instruction
120 /// pointer, the constpool index, and the number of CPUser's which
121 /// reference this entry.
126 CPEntry(MachineInstr *cpemi, unsigned cpi, unsigned rc = 0)
127 : CPEMI(cpemi), CPI(cpi), RefCount(rc) {}
130 /// CPEntries - Keep track of all of the constant pool entry machine
131 /// instructions. For each original constpool index (i.e. those that
132 /// existed upon entry to this pass), it keeps a vector of entries.
133 /// Original elements are cloned as we go along; the clones are
134 /// put in the vector of the original element, but have distinct CPIs.
135 std::vector<std::vector<CPEntry> > CPEntries;
137 /// ImmBranch - One per immediate branch, keeping the machine instruction
138 /// pointer, conditional or unconditional, the max displacement,
139 /// and (if isCond is true) the corresponding unconditional branch
143 unsigned MaxDisp : 31;
146 ImmBranch(MachineInstr *mi, unsigned maxdisp, bool cond, int ubr)
147 : MI(mi), MaxDisp(maxdisp), isCond(cond), UncondBr(ubr) {}
150 /// ImmBranches - Keep track of all the immediate branch instructions.
152 std::vector<ImmBranch> ImmBranches;
154 /// PushPopMIs - Keep track of all the Thumb push / pop instructions.
156 SmallVector<MachineInstr*, 4> PushPopMIs;
158 /// T2JumpTables - Keep track of all the Thumb2 jumptable instructions.
159 SmallVector<MachineInstr*, 4> T2JumpTables;
161 /// HasFarJump - True if any far jump instruction has been emitted during
162 /// the branch fix up pass.
165 /// HasInlineAsm - True if the function contains inline assembly.
168 const ARMInstrInfo *TII;
169 const ARMSubtarget *STI;
170 ARMFunctionInfo *AFI;
176 ARMConstantIslands() : MachineFunctionPass(&ID) {}
178 virtual bool runOnMachineFunction(MachineFunction &MF);
180 virtual const char *getPassName() const {
181 return "ARM constant island placement and branch shortening pass";
185 void DoInitialPlacement(MachineFunction &MF,
186 std::vector<MachineInstr*> &CPEMIs);
187 CPEntry *findConstPoolEntry(unsigned CPI, const MachineInstr *CPEMI);
188 void JumpTableFunctionScan(MachineFunction &MF);
189 void InitialFunctionScan(MachineFunction &MF,
190 const std::vector<MachineInstr*> &CPEMIs);
191 MachineBasicBlock *SplitBlockBeforeInstr(MachineInstr *MI);
192 void UpdateForInsertedWaterBlock(MachineBasicBlock *NewBB);
193 void AdjustBBOffsetsAfter(MachineBasicBlock *BB, int delta);
194 bool DecrementOldEntry(unsigned CPI, MachineInstr* CPEMI);
195 int LookForExistingCPEntry(CPUser& U, unsigned UserOffset);
196 bool LookForWater(CPUser&U, unsigned UserOffset, water_iterator &WaterIter);
197 void CreateNewWater(unsigned CPUserIndex, unsigned UserOffset,
198 MachineBasicBlock *&NewMBB);
199 bool HandleConstantPoolUser(MachineFunction &MF, unsigned CPUserIndex);
200 void RemoveDeadCPEMI(MachineInstr *CPEMI);
201 bool RemoveUnusedCPEntries();
202 bool CPEIsInRange(MachineInstr *MI, unsigned UserOffset,
203 MachineInstr *CPEMI, unsigned Disp, bool NegOk,
204 bool DoDump = false);
205 bool WaterIsInRange(unsigned UserOffset, MachineBasicBlock *Water,
207 bool OffsetIsInRange(unsigned UserOffset, unsigned TrialOffset,
208 unsigned Disp, bool NegativeOK, bool IsSoImm = false);
209 bool BBIsInRange(MachineInstr *MI, MachineBasicBlock *BB, unsigned Disp);
210 bool FixUpImmediateBr(MachineFunction &MF, ImmBranch &Br);
211 bool FixUpConditionalBr(MachineFunction &MF, ImmBranch &Br);
212 bool FixUpUnconditionalBr(MachineFunction &MF, ImmBranch &Br);
213 bool UndoLRSpillRestore();
214 bool OptimizeThumb2Instructions(MachineFunction &MF);
215 bool OptimizeThumb2Branches(MachineFunction &MF);
216 bool ReorderThumb2JumpTables(MachineFunction &MF);
217 bool OptimizeThumb2JumpTables(MachineFunction &MF);
218 MachineBasicBlock *AdjustJTTargetBlockForward(MachineBasicBlock *BB,
219 MachineBasicBlock *JTBB);
221 unsigned GetOffsetOf(MachineInstr *MI) const;
223 void verify(MachineFunction &MF);
225 char ARMConstantIslands::ID = 0;
228 /// verify - check BBOffsets, BBSizes, alignment of islands
229 void ARMConstantIslands::verify(MachineFunction &MF) {
230 assert(BBOffsets.size() == BBSizes.size());
231 for (unsigned i = 1, e = BBOffsets.size(); i != e; ++i)
232 assert(BBOffsets[i-1]+BBSizes[i-1] == BBOffsets[i]);
236 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
238 MachineBasicBlock *MBB = MBBI;
240 MBB->begin()->getOpcode() == ARM::CONSTPOOL_ENTRY) {
241 unsigned MBBId = MBB->getNumber();
242 assert(HasInlineAsm ||
243 (BBOffsets[MBBId]%4 == 0 && BBSizes[MBBId]%4 == 0) ||
244 (BBOffsets[MBBId]%4 != 0 && BBSizes[MBBId]%4 != 0));
247 for (unsigned i = 0, e = CPUsers.size(); i != e; ++i) {
248 CPUser &U = CPUsers[i];
249 unsigned UserOffset = GetOffsetOf(U.MI) + (isThumb ? 4 : 8);
250 unsigned CPEOffset = GetOffsetOf(U.CPEMI);
251 unsigned Disp = UserOffset < CPEOffset ? CPEOffset - UserOffset :
252 UserOffset - CPEOffset;
253 assert(Disp <= U.MaxDisp || "Constant pool entry out of range!");
258 /// print block size and offset information - debugging
259 void ARMConstantIslands::dumpBBs() {
260 for (unsigned J = 0, E = BBOffsets.size(); J !=E; ++J) {
261 DEBUG(errs() << "block " << J << " offset " << BBOffsets[J]
262 << " size " << BBSizes[J] << "\n");
266 /// createARMConstantIslandPass - returns an instance of the constpool
268 FunctionPass *llvm::createARMConstantIslandPass() {
269 return new ARMConstantIslands();
272 bool ARMConstantIslands::runOnMachineFunction(MachineFunction &MF) {
273 MachineConstantPool &MCP = *MF.getConstantPool();
275 TII = (const ARMInstrInfo*)MF.getTarget().getInstrInfo();
276 AFI = MF.getInfo<ARMFunctionInfo>();
277 STI = &MF.getTarget().getSubtarget<ARMSubtarget>();
279 isThumb = AFI->isThumbFunction();
280 isThumb1 = AFI->isThumb1OnlyFunction();
281 isThumb2 = AFI->isThumb2Function();
284 HasInlineAsm = false;
286 // Renumber all of the machine basic blocks in the function, guaranteeing that
287 // the numbers agree with the position of the block in the function.
290 // Try to reorder and otherwise adjust the block layout to make good use
291 // of the TB[BH] instructions.
292 bool MadeChange = false;
293 if (isThumb2 && AdjustJumpTableBlocks) {
294 JumpTableFunctionScan(MF);
295 MadeChange |= ReorderThumb2JumpTables(MF);
296 // Data is out of date, so clear it. It'll be re-computed later.
297 T2JumpTables.clear();
298 // Blocks may have shifted around. Keep the numbering up to date.
302 // Thumb1 functions containing constant pools get 4-byte alignment.
303 // This is so we can keep exact track of where the alignment padding goes.
305 // ARM and Thumb2 functions need to be 4-byte aligned.
307 MF.EnsureAlignment(2); // 2 = log2(4)
309 // Perform the initial placement of the constant pool entries. To start with,
310 // we put them all at the end of the function.
311 std::vector<MachineInstr*> CPEMIs;
312 if (!MCP.isEmpty()) {
313 DoInitialPlacement(MF, CPEMIs);
315 MF.EnsureAlignment(2); // 2 = log2(4)
318 /// The next UID to take is the first unused one.
319 AFI->initConstPoolEntryUId(CPEMIs.size());
321 // Do the initial scan of the function, building up information about the
322 // sizes of each block, the location of all the water, and finding all of the
323 // constant pool users.
324 InitialFunctionScan(MF, CPEMIs);
327 /// Remove dead constant pool entries.
328 RemoveUnusedCPEntries();
330 // Iteratively place constant pool entries and fix up branches until there
332 unsigned NoCPIters = 0, NoBRIters = 0;
334 bool CPChange = false;
335 for (unsigned i = 0, e = CPUsers.size(); i != e; ++i)
336 CPChange |= HandleConstantPoolUser(MF, i);
337 if (CPChange && ++NoCPIters > 30)
338 llvm_unreachable("Constant Island pass failed to converge!");
341 // Clear NewWaterList now. If we split a block for branches, it should
342 // appear as "new water" for the next iteration of constant pool placement.
343 NewWaterList.clear();
345 bool BRChange = false;
346 for (unsigned i = 0, e = ImmBranches.size(); i != e; ++i)
347 BRChange |= FixUpImmediateBr(MF, ImmBranches[i]);
348 if (BRChange && ++NoBRIters > 30)
349 llvm_unreachable("Branch Fix Up pass failed to converge!");
352 if (!CPChange && !BRChange)
357 // Shrink 32-bit Thumb2 branch, load, and store instructions.
359 MadeChange |= OptimizeThumb2Instructions(MF);
361 // After a while, this might be made debug-only, but it is not expensive.
364 // If LR has been forced spilled and no far jump (i.e. BL) has been issued,
365 // undo the spill / restore of LR if possible.
366 if (isThumb && !HasFarJump && AFI->isLRSpilledForFarJump())
367 MadeChange |= UndoLRSpillRestore();
369 DEBUG(errs() << '\n'; dumpBBs());
378 T2JumpTables.clear();
383 /// DoInitialPlacement - Perform the initial placement of the constant pool
384 /// entries. To start with, we put them all at the end of the function.
385 void ARMConstantIslands::DoInitialPlacement(MachineFunction &MF,
386 std::vector<MachineInstr*> &CPEMIs) {
387 // Create the basic block to hold the CPE's.
388 MachineBasicBlock *BB = MF.CreateMachineBasicBlock();
391 // Add all of the constants from the constant pool to the end block, use an
392 // identity mapping of CPI's to CPE's.
393 const std::vector<MachineConstantPoolEntry> &CPs =
394 MF.getConstantPool()->getConstants();
396 const TargetData &TD = *MF.getTarget().getTargetData();
397 for (unsigned i = 0, e = CPs.size(); i != e; ++i) {
398 unsigned Size = TD.getTypeAllocSize(CPs[i].getType());
399 // Verify that all constant pool entries are a multiple of 4 bytes. If not,
400 // we would have to pad them out or something so that instructions stay
402 assert((Size & 3) == 0 && "CP Entry not multiple of 4 bytes!");
403 MachineInstr *CPEMI =
404 BuildMI(BB, DebugLoc(), TII->get(ARM::CONSTPOOL_ENTRY))
405 .addImm(i).addConstantPoolIndex(i).addImm(Size);
406 CPEMIs.push_back(CPEMI);
408 // Add a new CPEntry, but no corresponding CPUser yet.
409 std::vector<CPEntry> CPEs;
410 CPEs.push_back(CPEntry(CPEMI, i));
411 CPEntries.push_back(CPEs);
413 DEBUG(errs() << "Moved CPI#" << i << " to end of function as #" << i
418 /// BBHasFallthrough - Return true if the specified basic block can fallthrough
419 /// into the block immediately after it.
420 static bool BBHasFallthrough(MachineBasicBlock *MBB) {
421 // Get the next machine basic block in the function.
422 MachineFunction::iterator MBBI = MBB;
423 // Can't fall off end of function.
424 if (llvm::next(MBBI) == MBB->getParent()->end())
427 MachineBasicBlock *NextBB = llvm::next(MBBI);
428 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
429 E = MBB->succ_end(); I != E; ++I)
436 /// findConstPoolEntry - Given the constpool index and CONSTPOOL_ENTRY MI,
437 /// look up the corresponding CPEntry.
438 ARMConstantIslands::CPEntry
439 *ARMConstantIslands::findConstPoolEntry(unsigned CPI,
440 const MachineInstr *CPEMI) {
441 std::vector<CPEntry> &CPEs = CPEntries[CPI];
442 // Number of entries per constpool index should be small, just do a
444 for (unsigned i = 0, e = CPEs.size(); i != e; ++i) {
445 if (CPEs[i].CPEMI == CPEMI)
451 /// JumpTableFunctionScan - Do a scan of the function, building up
452 /// information about the sizes of each block and the locations of all
454 void ARMConstantIslands::JumpTableFunctionScan(MachineFunction &MF) {
455 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
457 MachineBasicBlock &MBB = *MBBI;
459 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
461 if (I->getDesc().isBranch() && I->getOpcode() == ARM::t2BR_JT)
462 T2JumpTables.push_back(I);
466 /// InitialFunctionScan - Do the initial scan of the function, building up
467 /// information about the sizes of each block, the location of all the water,
468 /// and finding all of the constant pool users.
469 void ARMConstantIslands::InitialFunctionScan(MachineFunction &MF,
470 const std::vector<MachineInstr*> &CPEMIs) {
471 // First thing, see if the function has any inline assembly in it. If so,
472 // we have to be conservative about alignment assumptions, as we don't
473 // know for sure the size of any instructions in the inline assembly.
474 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
476 MachineBasicBlock &MBB = *MBBI;
477 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
479 if (I->getOpcode() == ARM::INLINEASM)
483 // Now go back through the instructions and build up our data structures
485 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
487 MachineBasicBlock &MBB = *MBBI;
489 // If this block doesn't fall through into the next MBB, then this is
490 // 'water' that a constant pool island could be placed.
491 if (!BBHasFallthrough(&MBB))
492 WaterList.push_back(&MBB);
494 unsigned MBBSize = 0;
495 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
497 if (I->isDebugValue())
499 // Add instruction size to MBBSize.
500 MBBSize += TII->GetInstSizeInBytes(I);
502 int Opc = I->getOpcode();
503 if (I->getDesc().isBranch()) {
510 continue; // Ignore other JT branches
512 // A Thumb1 table jump may involve padding; for the offsets to
513 // be right, functions containing these must be 4-byte aligned.
514 // tBR_JTr expands to a mov pc followed by .align 2 and then the jump
515 // table entries. So this code checks whether offset of tBR_JTr + 2
517 MF.EnsureAlignment(2U);
518 if ((Offset+MBBSize+2)%4 != 0 || HasInlineAsm)
519 // FIXME: Add a pseudo ALIGN instruction instead.
520 MBBSize += 2; // padding
521 continue; // Does not get an entry in ImmBranches
523 T2JumpTables.push_back(I);
524 continue; // Does not get an entry in ImmBranches
555 // Record this immediate branch.
556 unsigned MaxOffs = ((1 << (Bits-1))-1) * Scale;
557 ImmBranches.push_back(ImmBranch(I, MaxOffs, isCond, UOpc));
560 if (Opc == ARM::tPUSH || Opc == ARM::tPOP_RET)
561 PushPopMIs.push_back(I);
563 if (Opc == ARM::CONSTPOOL_ENTRY)
566 // Scan the instructions for constant pool operands.
567 for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op)
568 if (I->getOperand(op).isCPI()) {
569 // We found one. The addressing mode tells us the max displacement
570 // from the PC that this instruction permits.
572 // Basic size info comes from the TSFlags field.
576 bool IsSoImm = false;
580 llvm_unreachable("Unknown addressing mode for CP reference!");
583 // Taking the address of a CP entry.
585 // This takes a SoImm, which is 8 bit immediate rotated. We'll
586 // pretend the maximum offset is 255 * 4. Since each instruction
587 // 4 byte wide, this is always correct. We'll check for other
588 // displacements that fits in a SoImm as well.
594 case ARM::t2LEApcrel:
606 Bits = 12; // +-offset_12
613 Scale = 4; // +(offset_8*4)
619 Scale = 4; // +-(offset_8*4)
624 // Remember that this is a user of a CP entry.
625 unsigned CPI = I->getOperand(op).getIndex();
626 MachineInstr *CPEMI = CPEMIs[CPI];
627 unsigned MaxOffs = ((1 << Bits)-1) * Scale;
628 CPUsers.push_back(CPUser(I, CPEMI, MaxOffs, NegOk, IsSoImm));
630 // Increment corresponding CPEntry reference count.
631 CPEntry *CPE = findConstPoolEntry(CPI, CPEMI);
632 assert(CPE && "Cannot find a corresponding CPEntry!");
635 // Instructions can only use one CP entry, don't bother scanning the
636 // rest of the operands.
641 // In thumb mode, if this block is a constpool island, we may need padding
642 // so it's aligned on 4 byte boundary.
645 MBB.begin()->getOpcode() == ARM::CONSTPOOL_ENTRY &&
646 ((Offset%4) != 0 || HasInlineAsm))
649 BBSizes.push_back(MBBSize);
650 BBOffsets.push_back(Offset);
655 /// GetOffsetOf - Return the current offset of the specified machine instruction
656 /// from the start of the function. This offset changes as stuff is moved
657 /// around inside the function.
658 unsigned ARMConstantIslands::GetOffsetOf(MachineInstr *MI) const {
659 MachineBasicBlock *MBB = MI->getParent();
661 // The offset is composed of two things: the sum of the sizes of all MBB's
662 // before this instruction's block, and the offset from the start of the block
664 unsigned Offset = BBOffsets[MBB->getNumber()];
666 // If we're looking for a CONSTPOOL_ENTRY in Thumb, see if this block has
667 // alignment padding, and compensate if so.
669 MI->getOpcode() == ARM::CONSTPOOL_ENTRY &&
670 (Offset%4 != 0 || HasInlineAsm))
673 // Sum instructions before MI in MBB.
674 for (MachineBasicBlock::iterator I = MBB->begin(); ; ++I) {
675 assert(I != MBB->end() && "Didn't find MI in its own basic block?");
676 if (&*I == MI) return Offset;
677 Offset += TII->GetInstSizeInBytes(I);
681 /// CompareMBBNumbers - Little predicate function to sort the WaterList by MBB
683 static bool CompareMBBNumbers(const MachineBasicBlock *LHS,
684 const MachineBasicBlock *RHS) {
685 return LHS->getNumber() < RHS->getNumber();
688 /// UpdateForInsertedWaterBlock - When a block is newly inserted into the
689 /// machine function, it upsets all of the block numbers. Renumber the blocks
690 /// and update the arrays that parallel this numbering.
691 void ARMConstantIslands::UpdateForInsertedWaterBlock(MachineBasicBlock *NewBB) {
692 // Renumber the MBB's to keep them consequtive.
693 NewBB->getParent()->RenumberBlocks(NewBB);
695 // Insert a size into BBSizes to align it properly with the (newly
696 // renumbered) block numbers.
697 BBSizes.insert(BBSizes.begin()+NewBB->getNumber(), 0);
699 // Likewise for BBOffsets.
700 BBOffsets.insert(BBOffsets.begin()+NewBB->getNumber(), 0);
702 // Next, update WaterList. Specifically, we need to add NewMBB as having
703 // available water after it.
705 std::lower_bound(WaterList.begin(), WaterList.end(), NewBB,
707 WaterList.insert(IP, NewBB);
711 /// Split the basic block containing MI into two blocks, which are joined by
712 /// an unconditional branch. Update data structures and renumber blocks to
713 /// account for this change and returns the newly created block.
714 MachineBasicBlock *ARMConstantIslands::SplitBlockBeforeInstr(MachineInstr *MI) {
715 MachineBasicBlock *OrigBB = MI->getParent();
716 MachineFunction &MF = *OrigBB->getParent();
718 // Create a new MBB for the code after the OrigBB.
719 MachineBasicBlock *NewBB =
720 MF.CreateMachineBasicBlock(OrigBB->getBasicBlock());
721 MachineFunction::iterator MBBI = OrigBB; ++MBBI;
722 MF.insert(MBBI, NewBB);
724 // Splice the instructions starting with MI over to NewBB.
725 NewBB->splice(NewBB->end(), OrigBB, MI, OrigBB->end());
727 // Add an unconditional branch from OrigBB to NewBB.
728 // Note the new unconditional branch is not being recorded.
729 // There doesn't seem to be meaningful DebugInfo available; this doesn't
730 // correspond to anything in the source.
731 unsigned Opc = isThumb ? (isThumb2 ? ARM::t2B : ARM::tB) : ARM::B;
732 BuildMI(OrigBB, DebugLoc(), TII->get(Opc)).addMBB(NewBB);
735 // Update the CFG. All succs of OrigBB are now succs of NewBB.
736 while (!OrigBB->succ_empty()) {
737 MachineBasicBlock *Succ = *OrigBB->succ_begin();
738 OrigBB->removeSuccessor(Succ);
739 NewBB->addSuccessor(Succ);
741 // This pass should be run after register allocation, so there should be no
742 // PHI nodes to update.
743 assert((Succ->empty() || !Succ->begin()->isPHI())
744 && "PHI nodes should be eliminated by now!");
747 // OrigBB branches to NewBB.
748 OrigBB->addSuccessor(NewBB);
750 // Update internal data structures to account for the newly inserted MBB.
751 // This is almost the same as UpdateForInsertedWaterBlock, except that
752 // the Water goes after OrigBB, not NewBB.
753 MF.RenumberBlocks(NewBB);
755 // Insert a size into BBSizes to align it properly with the (newly
756 // renumbered) block numbers.
757 BBSizes.insert(BBSizes.begin()+NewBB->getNumber(), 0);
759 // Likewise for BBOffsets.
760 BBOffsets.insert(BBOffsets.begin()+NewBB->getNumber(), 0);
762 // Next, update WaterList. Specifically, we need to add OrigMBB as having
763 // available water after it (but not if it's already there, which happens
764 // when splitting before a conditional branch that is followed by an
765 // unconditional branch - in that case we want to insert NewBB).
767 std::lower_bound(WaterList.begin(), WaterList.end(), OrigBB,
769 MachineBasicBlock* WaterBB = *IP;
770 if (WaterBB == OrigBB)
771 WaterList.insert(llvm::next(IP), NewBB);
773 WaterList.insert(IP, OrigBB);
774 NewWaterList.insert(OrigBB);
776 // Figure out how large the first NewMBB is. (It cannot
777 // contain a constpool_entry or tablejump.)
778 unsigned NewBBSize = 0;
779 for (MachineBasicBlock::iterator I = NewBB->begin(), E = NewBB->end();
781 NewBBSize += TII->GetInstSizeInBytes(I);
783 unsigned OrigBBI = OrigBB->getNumber();
784 unsigned NewBBI = NewBB->getNumber();
785 // Set the size of NewBB in BBSizes.
786 BBSizes[NewBBI] = NewBBSize;
788 // We removed instructions from UserMBB, subtract that off from its size.
789 // Add 2 or 4 to the block to count the unconditional branch we added to it.
790 int delta = isThumb1 ? 2 : 4;
791 BBSizes[OrigBBI] -= NewBBSize - delta;
793 // ...and adjust BBOffsets for NewBB accordingly.
794 BBOffsets[NewBBI] = BBOffsets[OrigBBI] + BBSizes[OrigBBI];
796 // All BBOffsets following these blocks must be modified.
797 AdjustBBOffsetsAfter(NewBB, delta);
802 /// OffsetIsInRange - Checks whether UserOffset (the location of a constant pool
803 /// reference) is within MaxDisp of TrialOffset (a proposed location of a
804 /// constant pool entry).
805 bool ARMConstantIslands::OffsetIsInRange(unsigned UserOffset,
806 unsigned TrialOffset, unsigned MaxDisp,
807 bool NegativeOK, bool IsSoImm) {
808 // On Thumb offsets==2 mod 4 are rounded down by the hardware for
809 // purposes of the displacement computation; compensate for that here.
810 // Effectively, the valid range of displacements is 2 bytes smaller for such
812 unsigned TotalAdj = 0;
813 if (isThumb && UserOffset%4 !=0) {
817 // CPEs will be rounded up to a multiple of 4.
818 if (isThumb && TrialOffset%4 != 0) {
823 // In Thumb2 mode, later branch adjustments can shift instructions up and
824 // cause alignment change. In the worst case scenario this can cause the
825 // user's effective address to be subtracted by 2 and the CPE's address to
827 if (isThumb2 && TotalAdj != 4)
828 MaxDisp -= (4 - TotalAdj);
830 if (UserOffset <= TrialOffset) {
831 // User before the Trial.
832 if (TrialOffset - UserOffset <= MaxDisp)
834 // FIXME: Make use full range of soimm values.
835 } else if (NegativeOK) {
836 if (UserOffset - TrialOffset <= MaxDisp)
838 // FIXME: Make use full range of soimm values.
843 /// WaterIsInRange - Returns true if a CPE placed after the specified
844 /// Water (a basic block) will be in range for the specific MI.
846 bool ARMConstantIslands::WaterIsInRange(unsigned UserOffset,
847 MachineBasicBlock* Water, CPUser &U) {
848 unsigned MaxDisp = U.MaxDisp;
849 unsigned CPEOffset = BBOffsets[Water->getNumber()] +
850 BBSizes[Water->getNumber()];
852 // If the CPE is to be inserted before the instruction, that will raise
853 // the offset of the instruction.
854 if (CPEOffset < UserOffset)
855 UserOffset += U.CPEMI->getOperand(2).getImm();
857 return OffsetIsInRange(UserOffset, CPEOffset, MaxDisp, U.NegOk, U.IsSoImm);
860 /// CPEIsInRange - Returns true if the distance between specific MI and
861 /// specific ConstPool entry instruction can fit in MI's displacement field.
862 bool ARMConstantIslands::CPEIsInRange(MachineInstr *MI, unsigned UserOffset,
863 MachineInstr *CPEMI, unsigned MaxDisp,
864 bool NegOk, bool DoDump) {
865 unsigned CPEOffset = GetOffsetOf(CPEMI);
866 assert((CPEOffset%4 == 0 || HasInlineAsm) && "Misaligned CPE");
869 DEBUG(errs() << "User of CPE#" << CPEMI->getOperand(0).getImm()
870 << " max delta=" << MaxDisp
871 << " insn address=" << UserOffset
872 << " CPE address=" << CPEOffset
873 << " offset=" << int(CPEOffset-UserOffset) << "\t" << *MI);
876 return OffsetIsInRange(UserOffset, CPEOffset, MaxDisp, NegOk);
880 /// BBIsJumpedOver - Return true of the specified basic block's only predecessor
881 /// unconditionally branches to its only successor.
882 static bool BBIsJumpedOver(MachineBasicBlock *MBB) {
883 if (MBB->pred_size() != 1 || MBB->succ_size() != 1)
886 MachineBasicBlock *Succ = *MBB->succ_begin();
887 MachineBasicBlock *Pred = *MBB->pred_begin();
888 MachineInstr *PredMI = &Pred->back();
889 if (PredMI->getOpcode() == ARM::B || PredMI->getOpcode() == ARM::tB
890 || PredMI->getOpcode() == ARM::t2B)
891 return PredMI->getOperand(0).getMBB() == Succ;
896 void ARMConstantIslands::AdjustBBOffsetsAfter(MachineBasicBlock *BB,
898 MachineFunction::iterator MBBI = BB; MBBI = llvm::next(MBBI);
899 for(unsigned i = BB->getNumber()+1, e = BB->getParent()->getNumBlockIDs();
901 BBOffsets[i] += delta;
902 // If some existing blocks have padding, adjust the padding as needed, a
903 // bit tricky. delta can be negative so don't use % on that.
906 MachineBasicBlock *MBB = MBBI;
907 if (!MBB->empty() && !HasInlineAsm) {
908 // Constant pool entries require padding.
909 if (MBB->begin()->getOpcode() == ARM::CONSTPOOL_ENTRY) {
910 unsigned OldOffset = BBOffsets[i] - delta;
911 if ((OldOffset%4) == 0 && (BBOffsets[i]%4) != 0) {
915 } else if ((OldOffset%4) != 0 && (BBOffsets[i]%4) == 0) {
916 // remove existing padding
921 // Thumb1 jump tables require padding. They should be at the end;
922 // following unconditional branches are removed by AnalyzeBranch.
923 // tBR_JTr expands to a mov pc followed by .align 2 and then the jump
924 // table entries. So this code checks whether offset of tBR_JTr + 2
926 MachineInstr *ThumbJTMI = prior(MBB->end());
927 if (ThumbJTMI->getOpcode() == ARM::tBR_JTr) {
928 unsigned NewMIOffset = GetOffsetOf(ThumbJTMI) + 2;
929 unsigned OldMIOffset = NewMIOffset - delta;
930 if ((OldMIOffset%4) == 0 && (NewMIOffset%4) != 0) {
931 // remove existing padding
934 } else if ((OldMIOffset%4) != 0 && (NewMIOffset%4) == 0) {
943 MBBI = llvm::next(MBBI);
947 /// DecrementOldEntry - find the constant pool entry with index CPI
948 /// and instruction CPEMI, and decrement its refcount. If the refcount
949 /// becomes 0 remove the entry and instruction. Returns true if we removed
950 /// the entry, false if we didn't.
952 bool ARMConstantIslands::DecrementOldEntry(unsigned CPI, MachineInstr *CPEMI) {
953 // Find the old entry. Eliminate it if it is no longer used.
954 CPEntry *CPE = findConstPoolEntry(CPI, CPEMI);
955 assert(CPE && "Unexpected!");
956 if (--CPE->RefCount == 0) {
957 RemoveDeadCPEMI(CPEMI);
965 /// LookForCPEntryInRange - see if the currently referenced CPE is in range;
966 /// if not, see if an in-range clone of the CPE is in range, and if so,
967 /// change the data structures so the user references the clone. Returns:
968 /// 0 = no existing entry found
969 /// 1 = entry found, and there were no code insertions or deletions
970 /// 2 = entry found, and there were code insertions or deletions
971 int ARMConstantIslands::LookForExistingCPEntry(CPUser& U, unsigned UserOffset)
973 MachineInstr *UserMI = U.MI;
974 MachineInstr *CPEMI = U.CPEMI;
976 // Check to see if the CPE is already in-range.
977 if (CPEIsInRange(UserMI, UserOffset, CPEMI, U.MaxDisp, U.NegOk, true)) {
978 DEBUG(errs() << "In range\n");
982 // No. Look for previously created clones of the CPE that are in range.
983 unsigned CPI = CPEMI->getOperand(1).getIndex();
984 std::vector<CPEntry> &CPEs = CPEntries[CPI];
985 for (unsigned i = 0, e = CPEs.size(); i != e; ++i) {
986 // We already tried this one
987 if (CPEs[i].CPEMI == CPEMI)
989 // Removing CPEs can leave empty entries, skip
990 if (CPEs[i].CPEMI == NULL)
992 if (CPEIsInRange(UserMI, UserOffset, CPEs[i].CPEMI, U.MaxDisp, U.NegOk)) {
993 DEBUG(errs() << "Replacing CPE#" << CPI << " with CPE#"
994 << CPEs[i].CPI << "\n");
995 // Point the CPUser node to the replacement
996 U.CPEMI = CPEs[i].CPEMI;
997 // Change the CPI in the instruction operand to refer to the clone.
998 for (unsigned j = 0, e = UserMI->getNumOperands(); j != e; ++j)
999 if (UserMI->getOperand(j).isCPI()) {
1000 UserMI->getOperand(j).setIndex(CPEs[i].CPI);
1003 // Adjust the refcount of the clone...
1005 // ...and the original. If we didn't remove the old entry, none of the
1006 // addresses changed, so we don't need another pass.
1007 return DecrementOldEntry(CPI, CPEMI) ? 2 : 1;
1013 /// getUnconditionalBrDisp - Returns the maximum displacement that can fit in
1014 /// the specific unconditional branch instruction.
1015 static inline unsigned getUnconditionalBrDisp(int Opc) {
1018 return ((1<<10)-1)*2;
1020 return ((1<<23)-1)*2;
1025 return ((1<<23)-1)*4;
1028 /// LookForWater - Look for an existing entry in the WaterList in which
1029 /// we can place the CPE referenced from U so it's within range of U's MI.
1030 /// Returns true if found, false if not. If it returns true, WaterIter
1031 /// is set to the WaterList entry. For Thumb, prefer water that will not
1032 /// introduce padding to water that will. To ensure that this pass
1033 /// terminates, the CPE location for a particular CPUser is only allowed to
1034 /// move to a lower address, so search backward from the end of the list and
1035 /// prefer the first water that is in range.
1036 bool ARMConstantIslands::LookForWater(CPUser &U, unsigned UserOffset,
1037 water_iterator &WaterIter) {
1038 if (WaterList.empty())
1041 bool FoundWaterThatWouldPad = false;
1042 water_iterator IPThatWouldPad;
1043 for (water_iterator IP = prior(WaterList.end()),
1044 B = WaterList.begin();; --IP) {
1045 MachineBasicBlock* WaterBB = *IP;
1046 // Check if water is in range and is either at a lower address than the
1047 // current "high water mark" or a new water block that was created since
1048 // the previous iteration by inserting an unconditional branch. In the
1049 // latter case, we want to allow resetting the high water mark back to
1050 // this new water since we haven't seen it before. Inserting branches
1051 // should be relatively uncommon and when it does happen, we want to be
1052 // sure to take advantage of it for all the CPEs near that block, so that
1053 // we don't insert more branches than necessary.
1054 if (WaterIsInRange(UserOffset, WaterBB, U) &&
1055 (WaterBB->getNumber() < U.HighWaterMark->getNumber() ||
1056 NewWaterList.count(WaterBB))) {
1057 unsigned WBBId = WaterBB->getNumber();
1059 (BBOffsets[WBBId] + BBSizes[WBBId])%4 != 0) {
1060 // This is valid Water, but would introduce padding. Remember
1061 // it in case we don't find any Water that doesn't do this.
1062 if (!FoundWaterThatWouldPad) {
1063 FoundWaterThatWouldPad = true;
1064 IPThatWouldPad = IP;
1074 if (FoundWaterThatWouldPad) {
1075 WaterIter = IPThatWouldPad;
1081 /// CreateNewWater - No existing WaterList entry will work for
1082 /// CPUsers[CPUserIndex], so create a place to put the CPE. The end of the
1083 /// block is used if in range, and the conditional branch munged so control
1084 /// flow is correct. Otherwise the block is split to create a hole with an
1085 /// unconditional branch around it. In either case NewMBB is set to a
1086 /// block following which the new island can be inserted (the WaterList
1087 /// is not adjusted).
1088 void ARMConstantIslands::CreateNewWater(unsigned CPUserIndex,
1089 unsigned UserOffset,
1090 MachineBasicBlock *&NewMBB) {
1091 CPUser &U = CPUsers[CPUserIndex];
1092 MachineInstr *UserMI = U.MI;
1093 MachineInstr *CPEMI = U.CPEMI;
1094 MachineBasicBlock *UserMBB = UserMI->getParent();
1095 unsigned OffsetOfNextBlock = BBOffsets[UserMBB->getNumber()] +
1096 BBSizes[UserMBB->getNumber()];
1097 assert(OffsetOfNextBlock== BBOffsets[UserMBB->getNumber()+1]);
1099 // If the block does not end in an unconditional branch already, and if the
1100 // end of the block is within range, make new water there. (The addition
1101 // below is for the unconditional branch we will be adding: 4 bytes on ARM +
1102 // Thumb2, 2 on Thumb1. Possible Thumb1 alignment padding is allowed for
1103 // inside OffsetIsInRange.
1104 if (BBHasFallthrough(UserMBB) &&
1105 OffsetIsInRange(UserOffset, OffsetOfNextBlock + (isThumb1 ? 2: 4),
1106 U.MaxDisp, U.NegOk, U.IsSoImm)) {
1107 DEBUG(errs() << "Split at end of block\n");
1108 if (&UserMBB->back() == UserMI)
1109 assert(BBHasFallthrough(UserMBB) && "Expected a fallthrough BB!");
1110 NewMBB = llvm::next(MachineFunction::iterator(UserMBB));
1111 // Add an unconditional branch from UserMBB to fallthrough block.
1112 // Record it for branch lengthening; this new branch will not get out of
1113 // range, but if the preceding conditional branch is out of range, the
1114 // targets will be exchanged, and the altered branch may be out of
1115 // range, so the machinery has to know about it.
1116 int UncondBr = isThumb ? ((isThumb2) ? ARM::t2B : ARM::tB) : ARM::B;
1117 BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB);
1118 unsigned MaxDisp = getUnconditionalBrDisp(UncondBr);
1119 ImmBranches.push_back(ImmBranch(&UserMBB->back(),
1120 MaxDisp, false, UncondBr));
1121 int delta = isThumb1 ? 2 : 4;
1122 BBSizes[UserMBB->getNumber()] += delta;
1123 AdjustBBOffsetsAfter(UserMBB, delta);
1125 // What a big block. Find a place within the block to split it.
1126 // This is a little tricky on Thumb1 since instructions are 2 bytes
1127 // and constant pool entries are 4 bytes: if instruction I references
1128 // island CPE, and instruction I+1 references CPE', it will
1129 // not work well to put CPE as far forward as possible, since then
1130 // CPE' cannot immediately follow it (that location is 2 bytes
1131 // farther away from I+1 than CPE was from I) and we'd need to create
1132 // a new island. So, we make a first guess, then walk through the
1133 // instructions between the one currently being looked at and the
1134 // possible insertion point, and make sure any other instructions
1135 // that reference CPEs will be able to use the same island area;
1136 // if not, we back up the insertion point.
1138 // The 4 in the following is for the unconditional branch we'll be
1139 // inserting (allows for long branch on Thumb1). Alignment of the
1140 // island is handled inside OffsetIsInRange.
1141 unsigned BaseInsertOffset = UserOffset + U.MaxDisp -4;
1142 // This could point off the end of the block if we've already got
1143 // constant pool entries following this block; only the last one is
1144 // in the water list. Back past any possible branches (allow for a
1145 // conditional and a maximally long unconditional).
1146 if (BaseInsertOffset >= BBOffsets[UserMBB->getNumber()+1])
1147 BaseInsertOffset = BBOffsets[UserMBB->getNumber()+1] -
1149 unsigned EndInsertOffset = BaseInsertOffset +
1150 CPEMI->getOperand(2).getImm();
1151 MachineBasicBlock::iterator MI = UserMI;
1153 unsigned CPUIndex = CPUserIndex+1;
1154 for (unsigned Offset = UserOffset+TII->GetInstSizeInBytes(UserMI);
1155 Offset < BaseInsertOffset;
1156 Offset += TII->GetInstSizeInBytes(MI),
1157 MI = llvm::next(MI)) {
1158 if (CPUIndex < CPUsers.size() && CPUsers[CPUIndex].MI == MI) {
1159 CPUser &U = CPUsers[CPUIndex];
1160 if (!OffsetIsInRange(Offset, EndInsertOffset,
1161 U.MaxDisp, U.NegOk, U.IsSoImm)) {
1162 BaseInsertOffset -= (isThumb1 ? 2 : 4);
1163 EndInsertOffset -= (isThumb1 ? 2 : 4);
1165 // This is overly conservative, as we don't account for CPEMIs
1166 // being reused within the block, but it doesn't matter much.
1167 EndInsertOffset += CPUsers[CPUIndex].CPEMI->getOperand(2).getImm();
1171 DEBUG(errs() << "Split in middle of big block\n");
1172 NewMBB = SplitBlockBeforeInstr(prior(MI));
1176 /// HandleConstantPoolUser - Analyze the specified user, checking to see if it
1177 /// is out-of-range. If so, pick up the constant pool value and move it some
1178 /// place in-range. Return true if we changed any addresses (thus must run
1179 /// another pass of branch lengthening), false otherwise.
1180 bool ARMConstantIslands::HandleConstantPoolUser(MachineFunction &MF,
1181 unsigned CPUserIndex) {
1182 CPUser &U = CPUsers[CPUserIndex];
1183 MachineInstr *UserMI = U.MI;
1184 MachineInstr *CPEMI = U.CPEMI;
1185 unsigned CPI = CPEMI->getOperand(1).getIndex();
1186 unsigned Size = CPEMI->getOperand(2).getImm();
1187 // Compute this only once, it's expensive. The 4 or 8 is the value the
1188 // hardware keeps in the PC.
1189 unsigned UserOffset = GetOffsetOf(UserMI) + (isThumb ? 4 : 8);
1191 // See if the current entry is within range, or there is a clone of it
1193 int result = LookForExistingCPEntry(U, UserOffset);
1194 if (result==1) return false;
1195 else if (result==2) return true;
1197 // No existing clone of this CPE is within range.
1198 // We will be generating a new clone. Get a UID for it.
1199 unsigned ID = AFI->createConstPoolEntryUId();
1201 // Look for water where we can place this CPE.
1202 MachineBasicBlock *NewIsland = MF.CreateMachineBasicBlock();
1203 MachineBasicBlock *NewMBB;
1205 if (LookForWater(U, UserOffset, IP)) {
1206 DEBUG(errs() << "found water in range\n");
1207 MachineBasicBlock *WaterBB = *IP;
1209 // If the original WaterList entry was "new water" on this iteration,
1210 // propagate that to the new island. This is just keeping NewWaterList
1211 // updated to match the WaterList, which will be updated below.
1212 if (NewWaterList.count(WaterBB)) {
1213 NewWaterList.erase(WaterBB);
1214 NewWaterList.insert(NewIsland);
1216 // The new CPE goes before the following block (NewMBB).
1217 NewMBB = llvm::next(MachineFunction::iterator(WaterBB));
1221 DEBUG(errs() << "No water found\n");
1222 CreateNewWater(CPUserIndex, UserOffset, NewMBB);
1224 // SplitBlockBeforeInstr adds to WaterList, which is important when it is
1225 // called while handling branches so that the water will be seen on the
1226 // next iteration for constant pools, but in this context, we don't want
1227 // it. Check for this so it will be removed from the WaterList.
1228 // Also remove any entry from NewWaterList.
1229 MachineBasicBlock *WaterBB = prior(MachineFunction::iterator(NewMBB));
1230 IP = std::find(WaterList.begin(), WaterList.end(), WaterBB);
1231 if (IP != WaterList.end())
1232 NewWaterList.erase(WaterBB);
1234 // We are adding new water. Update NewWaterList.
1235 NewWaterList.insert(NewIsland);
1238 // Remove the original WaterList entry; we want subsequent insertions in
1239 // this vicinity to go after the one we're about to insert. This
1240 // considerably reduces the number of times we have to move the same CPE
1241 // more than once and is also important to ensure the algorithm terminates.
1242 if (IP != WaterList.end())
1243 WaterList.erase(IP);
1245 // Okay, we know we can put an island before NewMBB now, do it!
1246 MF.insert(NewMBB, NewIsland);
1248 // Update internal data structures to account for the newly inserted MBB.
1249 UpdateForInsertedWaterBlock(NewIsland);
1251 // Decrement the old entry, and remove it if refcount becomes 0.
1252 DecrementOldEntry(CPI, CPEMI);
1254 // Now that we have an island to add the CPE to, clone the original CPE and
1255 // add it to the island.
1256 U.HighWaterMark = NewIsland;
1257 U.CPEMI = BuildMI(NewIsland, DebugLoc(), TII->get(ARM::CONSTPOOL_ENTRY))
1258 .addImm(ID).addConstantPoolIndex(CPI).addImm(Size);
1259 CPEntries[CPI].push_back(CPEntry(U.CPEMI, ID, 1));
1262 BBOffsets[NewIsland->getNumber()] = BBOffsets[NewMBB->getNumber()];
1263 // Compensate for .align 2 in thumb mode.
1264 if (isThumb && (BBOffsets[NewIsland->getNumber()]%4 != 0 || HasInlineAsm))
1266 // Increase the size of the island block to account for the new entry.
1267 BBSizes[NewIsland->getNumber()] += Size;
1268 AdjustBBOffsetsAfter(NewIsland, Size);
1270 // Finally, change the CPI in the instruction operand to be ID.
1271 for (unsigned i = 0, e = UserMI->getNumOperands(); i != e; ++i)
1272 if (UserMI->getOperand(i).isCPI()) {
1273 UserMI->getOperand(i).setIndex(ID);
1277 DEBUG(errs() << " Moved CPE to #" << ID << " CPI=" << CPI
1278 << '\t' << *UserMI);
1283 /// RemoveDeadCPEMI - Remove a dead constant pool entry instruction. Update
1284 /// sizes and offsets of impacted basic blocks.
1285 void ARMConstantIslands::RemoveDeadCPEMI(MachineInstr *CPEMI) {
1286 MachineBasicBlock *CPEBB = CPEMI->getParent();
1287 unsigned Size = CPEMI->getOperand(2).getImm();
1288 CPEMI->eraseFromParent();
1289 BBSizes[CPEBB->getNumber()] -= Size;
1290 // All succeeding offsets have the current size value added in, fix this.
1291 if (CPEBB->empty()) {
1292 // In thumb1 mode, the size of island may be padded by two to compensate for
1293 // the alignment requirement. Then it will now be 2 when the block is
1294 // empty, so fix this.
1295 // All succeeding offsets have the current size value added in, fix this.
1296 if (BBSizes[CPEBB->getNumber()] != 0) {
1297 Size += BBSizes[CPEBB->getNumber()];
1298 BBSizes[CPEBB->getNumber()] = 0;
1301 AdjustBBOffsetsAfter(CPEBB, -Size);
1302 // An island has only one predecessor BB and one successor BB. Check if
1303 // this BB's predecessor jumps directly to this BB's successor. This
1304 // shouldn't happen currently.
1305 assert(!BBIsJumpedOver(CPEBB) && "How did this happen?");
1306 // FIXME: remove the empty blocks after all the work is done?
1309 /// RemoveUnusedCPEntries - Remove constant pool entries whose refcounts
1311 bool ARMConstantIslands::RemoveUnusedCPEntries() {
1312 unsigned MadeChange = false;
1313 for (unsigned i = 0, e = CPEntries.size(); i != e; ++i) {
1314 std::vector<CPEntry> &CPEs = CPEntries[i];
1315 for (unsigned j = 0, ee = CPEs.size(); j != ee; ++j) {
1316 if (CPEs[j].RefCount == 0 && CPEs[j].CPEMI) {
1317 RemoveDeadCPEMI(CPEs[j].CPEMI);
1318 CPEs[j].CPEMI = NULL;
1326 /// BBIsInRange - Returns true if the distance between specific MI and
1327 /// specific BB can fit in MI's displacement field.
1328 bool ARMConstantIslands::BBIsInRange(MachineInstr *MI,MachineBasicBlock *DestBB,
1330 unsigned PCAdj = isThumb ? 4 : 8;
1331 unsigned BrOffset = GetOffsetOf(MI) + PCAdj;
1332 unsigned DestOffset = BBOffsets[DestBB->getNumber()];
1334 DEBUG(errs() << "Branch of destination BB#" << DestBB->getNumber()
1335 << " from BB#" << MI->getParent()->getNumber()
1336 << " max delta=" << MaxDisp
1337 << " from " << GetOffsetOf(MI) << " to " << DestOffset
1338 << " offset " << int(DestOffset-BrOffset) << "\t" << *MI);
1340 if (BrOffset <= DestOffset) {
1341 // Branch before the Dest.
1342 if (DestOffset-BrOffset <= MaxDisp)
1345 if (BrOffset-DestOffset <= MaxDisp)
1351 /// FixUpImmediateBr - Fix up an immediate branch whose destination is too far
1352 /// away to fit in its displacement field.
1353 bool ARMConstantIslands::FixUpImmediateBr(MachineFunction &MF, ImmBranch &Br) {
1354 MachineInstr *MI = Br.MI;
1355 MachineBasicBlock *DestBB = MI->getOperand(0).getMBB();
1357 // Check to see if the DestBB is already in-range.
1358 if (BBIsInRange(MI, DestBB, Br.MaxDisp))
1362 return FixUpUnconditionalBr(MF, Br);
1363 return FixUpConditionalBr(MF, Br);
1366 /// FixUpUnconditionalBr - Fix up an unconditional branch whose destination is
1367 /// too far away to fit in its displacement field. If the LR register has been
1368 /// spilled in the epilogue, then we can use BL to implement a far jump.
1369 /// Otherwise, add an intermediate branch instruction to a branch.
1371 ARMConstantIslands::FixUpUnconditionalBr(MachineFunction &MF, ImmBranch &Br) {
1372 MachineInstr *MI = Br.MI;
1373 MachineBasicBlock *MBB = MI->getParent();
1375 llvm_unreachable("FixUpUnconditionalBr is Thumb1 only!");
1377 // Use BL to implement far jump.
1378 Br.MaxDisp = (1 << 21) * 2;
1379 MI->setDesc(TII->get(ARM::tBfar));
1380 BBSizes[MBB->getNumber()] += 2;
1381 AdjustBBOffsetsAfter(MBB, 2);
1385 DEBUG(errs() << " Changed B to long jump " << *MI);
1390 /// FixUpConditionalBr - Fix up a conditional branch whose destination is too
1391 /// far away to fit in its displacement field. It is converted to an inverse
1392 /// conditional branch + an unconditional branch to the destination.
1394 ARMConstantIslands::FixUpConditionalBr(MachineFunction &MF, ImmBranch &Br) {
1395 MachineInstr *MI = Br.MI;
1396 MachineBasicBlock *DestBB = MI->getOperand(0).getMBB();
1398 // Add an unconditional branch to the destination and invert the branch
1399 // condition to jump over it:
1405 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(1).getImm();
1406 CC = ARMCC::getOppositeCondition(CC);
1407 unsigned CCReg = MI->getOperand(2).getReg();
1409 // If the branch is at the end of its MBB and that has a fall-through block,
1410 // direct the updated conditional branch to the fall-through block. Otherwise,
1411 // split the MBB before the next instruction.
1412 MachineBasicBlock *MBB = MI->getParent();
1413 MachineInstr *BMI = &MBB->back();
1414 bool NeedSplit = (BMI != MI) || !BBHasFallthrough(MBB);
1418 if (llvm::next(MachineBasicBlock::iterator(MI)) == prior(MBB->end()) &&
1419 BMI->getOpcode() == Br.UncondBr) {
1420 // Last MI in the BB is an unconditional branch. Can we simply invert the
1421 // condition and swap destinations:
1427 MachineBasicBlock *NewDest = BMI->getOperand(0).getMBB();
1428 if (BBIsInRange(MI, NewDest, Br.MaxDisp)) {
1429 DEBUG(errs() << " Invert Bcc condition and swap its destination with "
1431 BMI->getOperand(0).setMBB(DestBB);
1432 MI->getOperand(0).setMBB(NewDest);
1433 MI->getOperand(1).setImm(CC);
1440 SplitBlockBeforeInstr(MI);
1441 // No need for the branch to the next block. We're adding an unconditional
1442 // branch to the destination.
1443 int delta = TII->GetInstSizeInBytes(&MBB->back());
1444 BBSizes[MBB->getNumber()] -= delta;
1445 MachineBasicBlock* SplitBB = llvm::next(MachineFunction::iterator(MBB));
1446 AdjustBBOffsetsAfter(SplitBB, -delta);
1447 MBB->back().eraseFromParent();
1448 // BBOffsets[SplitBB] is wrong temporarily, fixed below
1450 MachineBasicBlock *NextBB = llvm::next(MachineFunction::iterator(MBB));
1452 DEBUG(errs() << " Insert B to BB#" << DestBB->getNumber()
1453 << " also invert condition and change dest. to BB#"
1454 << NextBB->getNumber() << "\n");
1456 // Insert a new conditional branch and a new unconditional branch.
1457 // Also update the ImmBranch as well as adding a new entry for the new branch.
1458 BuildMI(MBB, DebugLoc(), TII->get(MI->getOpcode()))
1459 .addMBB(NextBB).addImm(CC).addReg(CCReg);
1460 Br.MI = &MBB->back();
1461 BBSizes[MBB->getNumber()] += TII->GetInstSizeInBytes(&MBB->back());
1462 BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);
1463 BBSizes[MBB->getNumber()] += TII->GetInstSizeInBytes(&MBB->back());
1464 unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr);
1465 ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr));
1467 // Remove the old conditional branch. It may or may not still be in MBB.
1468 BBSizes[MI->getParent()->getNumber()] -= TII->GetInstSizeInBytes(MI);
1469 MI->eraseFromParent();
1471 // The net size change is an addition of one unconditional branch.
1472 int delta = TII->GetInstSizeInBytes(&MBB->back());
1473 AdjustBBOffsetsAfter(MBB, delta);
1477 /// UndoLRSpillRestore - Remove Thumb push / pop instructions that only spills
1478 /// LR / restores LR to pc. FIXME: This is done here because it's only possible
1479 /// to do this if tBfar is not used.
1480 bool ARMConstantIslands::UndoLRSpillRestore() {
1481 bool MadeChange = false;
1482 for (unsigned i = 0, e = PushPopMIs.size(); i != e; ++i) {
1483 MachineInstr *MI = PushPopMIs[i];
1484 // First two operands are predicates.
1485 if (MI->getOpcode() == ARM::tPOP_RET &&
1486 MI->getOperand(2).getReg() == ARM::PC &&
1487 MI->getNumExplicitOperands() == 3) {
1488 BuildMI(MI->getParent(), MI->getDebugLoc(), TII->get(ARM::tBX_RET));
1489 MI->eraseFromParent();
1496 bool ARMConstantIslands::OptimizeThumb2Instructions(MachineFunction &MF) {
1497 bool MadeChange = false;
1499 // Shrink ADR and LDR from constantpool.
1500 for (unsigned i = 0, e = CPUsers.size(); i != e; ++i) {
1501 CPUser &U = CPUsers[i];
1502 unsigned Opcode = U.MI->getOpcode();
1503 unsigned NewOpc = 0;
1508 case ARM::t2LEApcrel:
1509 if (isARMLowRegister(U.MI->getOperand(0).getReg())) {
1510 NewOpc = ARM::tLEApcrel;
1516 if (isARMLowRegister(U.MI->getOperand(0).getReg())) {
1517 NewOpc = ARM::tLDRpci;
1527 unsigned UserOffset = GetOffsetOf(U.MI) + 4;
1528 unsigned MaxOffs = ((1 << Bits) - 1) * Scale;
1529 // FIXME: Check if offset is multiple of scale if scale is not 4.
1530 if (CPEIsInRange(U.MI, UserOffset, U.CPEMI, MaxOffs, false, true)) {
1531 U.MI->setDesc(TII->get(NewOpc));
1532 MachineBasicBlock *MBB = U.MI->getParent();
1533 BBSizes[MBB->getNumber()] -= 2;
1534 AdjustBBOffsetsAfter(MBB, -2);
1540 MadeChange |= OptimizeThumb2Branches(MF);
1541 MadeChange |= OptimizeThumb2JumpTables(MF);
1545 bool ARMConstantIslands::OptimizeThumb2Branches(MachineFunction &MF) {
1546 bool MadeChange = false;
1548 for (unsigned i = 0, e = ImmBranches.size(); i != e; ++i) {
1549 ImmBranch &Br = ImmBranches[i];
1550 unsigned Opcode = Br.MI->getOpcode();
1551 unsigned NewOpc = 0;
1569 unsigned MaxOffs = ((1 << (Bits-1))-1) * Scale;
1570 MachineBasicBlock *DestBB = Br.MI->getOperand(0).getMBB();
1571 if (BBIsInRange(Br.MI, DestBB, MaxOffs)) {
1572 Br.MI->setDesc(TII->get(NewOpc));
1573 MachineBasicBlock *MBB = Br.MI->getParent();
1574 BBSizes[MBB->getNumber()] -= 2;
1575 AdjustBBOffsetsAfter(MBB, -2);
1581 Opcode = Br.MI->getOpcode();
1582 if (Opcode != ARM::tBcc)
1586 unsigned PredReg = 0;
1587 ARMCC::CondCodes Pred = llvm::getInstrPredicate(Br.MI, PredReg);
1588 if (Pred == ARMCC::EQ)
1590 else if (Pred == ARMCC::NE)
1591 NewOpc = ARM::tCBNZ;
1594 MachineBasicBlock *DestBB = Br.MI->getOperand(0).getMBB();
1595 // Check if the distance is within 126. Subtract starting offset by 2
1596 // because the cmp will be eliminated.
1597 unsigned BrOffset = GetOffsetOf(Br.MI) + 4 - 2;
1598 unsigned DestOffset = BBOffsets[DestBB->getNumber()];
1599 if (BrOffset < DestOffset && (DestOffset - BrOffset) <= 126) {
1600 MachineBasicBlock::iterator CmpMI = Br.MI; --CmpMI;
1601 if (CmpMI->getOpcode() == ARM::tCMPzi8) {
1602 unsigned Reg = CmpMI->getOperand(0).getReg();
1603 Pred = llvm::getInstrPredicate(CmpMI, PredReg);
1604 if (Pred == ARMCC::AL &&
1605 CmpMI->getOperand(1).getImm() == 0 &&
1606 isARMLowRegister(Reg)) {
1607 MachineBasicBlock *MBB = Br.MI->getParent();
1608 MachineInstr *NewBR =
1609 BuildMI(*MBB, CmpMI, Br.MI->getDebugLoc(), TII->get(NewOpc))
1610 .addReg(Reg).addMBB(DestBB, Br.MI->getOperand(0).getTargetFlags());
1611 CmpMI->eraseFromParent();
1612 Br.MI->eraseFromParent();
1614 BBSizes[MBB->getNumber()] -= 2;
1615 AdjustBBOffsetsAfter(MBB, -2);
1626 /// OptimizeThumb2JumpTables - Use tbb / tbh instructions to generate smaller
1627 /// jumptables when it's possible.
1628 bool ARMConstantIslands::OptimizeThumb2JumpTables(MachineFunction &MF) {
1629 bool MadeChange = false;
1631 // FIXME: After the tables are shrunk, can we get rid some of the
1632 // constantpool tables?
1633 MachineJumpTableInfo *MJTI = MF.getJumpTableInfo();
1634 if (MJTI == 0) return false;
1636 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1637 for (unsigned i = 0, e = T2JumpTables.size(); i != e; ++i) {
1638 MachineInstr *MI = T2JumpTables[i];
1639 const TargetInstrDesc &TID = MI->getDesc();
1640 unsigned NumOps = TID.getNumOperands();
1641 unsigned JTOpIdx = NumOps - (TID.isPredicable() ? 3 : 2);
1642 MachineOperand JTOP = MI->getOperand(JTOpIdx);
1643 unsigned JTI = JTOP.getIndex();
1644 assert(JTI < JT.size());
1647 bool HalfWordOk = true;
1648 unsigned JTOffset = GetOffsetOf(MI) + 4;
1649 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1650 for (unsigned j = 0, ee = JTBBs.size(); j != ee; ++j) {
1651 MachineBasicBlock *MBB = JTBBs[j];
1652 unsigned DstOffset = BBOffsets[MBB->getNumber()];
1653 // Negative offset is not ok. FIXME: We should change BB layout to make
1654 // sure all the branches are forward.
1655 if (ByteOk && (DstOffset - JTOffset) > ((1<<8)-1)*2)
1657 unsigned TBHLimit = ((1<<16)-1)*2;
1658 if (HalfWordOk && (DstOffset - JTOffset) > TBHLimit)
1660 if (!ByteOk && !HalfWordOk)
1664 if (ByteOk || HalfWordOk) {
1665 MachineBasicBlock *MBB = MI->getParent();
1666 unsigned BaseReg = MI->getOperand(0).getReg();
1667 bool BaseRegKill = MI->getOperand(0).isKill();
1670 unsigned IdxReg = MI->getOperand(1).getReg();
1671 bool IdxRegKill = MI->getOperand(1).isKill();
1673 // Scan backwards to find the instruction that defines the base
1674 // register. Due to post-RA scheduling, we can't count on it
1675 // immediately preceding the branch instruction.
1676 MachineBasicBlock::iterator PrevI = MI;
1677 MachineBasicBlock::iterator B = MBB->begin();
1678 while (PrevI != B && !PrevI->definesRegister(BaseReg))
1681 // If for some reason we didn't find it, we can't do anything, so
1682 // just skip this one.
1683 if (!PrevI->definesRegister(BaseReg))
1686 MachineInstr *AddrMI = PrevI;
1688 // Examine the instruction that calculates the jumptable entry address.
1689 // Make sure it only defines the base register and kills any uses
1690 // other than the index register.
1691 for (unsigned k = 0, eee = AddrMI->getNumOperands(); k != eee; ++k) {
1692 const MachineOperand &MO = AddrMI->getOperand(k);
1693 if (!MO.isReg() || !MO.getReg())
1695 if (MO.isDef() && MO.getReg() != BaseReg) {
1699 if (MO.isUse() && !MO.isKill() && MO.getReg() != IdxReg) {
1707 // Now scan back again to find the tLEApcrel or t2LEApcrelJT instruction
1708 // that gave us the initial base register definition.
1709 for (--PrevI; PrevI != B && !PrevI->definesRegister(BaseReg); --PrevI)
1712 // The instruction should be a tLEApcrel or t2LEApcrelJT; we want
1713 // to delete it as well.
1714 MachineInstr *LeaMI = PrevI;
1715 if ((LeaMI->getOpcode() != ARM::tLEApcrelJT &&
1716 LeaMI->getOpcode() != ARM::t2LEApcrelJT) ||
1717 LeaMI->getOperand(0).getReg() != BaseReg)
1723 unsigned Opc = ByteOk ? ARM::t2TBB : ARM::t2TBH;
1724 MachineInstr *NewJTMI = BuildMI(MBB, MI->getDebugLoc(), TII->get(Opc))
1725 .addReg(IdxReg, getKillRegState(IdxRegKill))
1726 .addJumpTableIndex(JTI, JTOP.getTargetFlags())
1727 .addImm(MI->getOperand(JTOpIdx+1).getImm());
1728 // FIXME: Insert an "ALIGN" instruction to ensure the next instruction
1729 // is 2-byte aligned. For now, asm printer will fix it up.
1730 unsigned NewSize = TII->GetInstSizeInBytes(NewJTMI);
1731 unsigned OrigSize = TII->GetInstSizeInBytes(AddrMI);
1732 OrigSize += TII->GetInstSizeInBytes(LeaMI);
1733 OrigSize += TII->GetInstSizeInBytes(MI);
1735 AddrMI->eraseFromParent();
1736 LeaMI->eraseFromParent();
1737 MI->eraseFromParent();
1739 int delta = OrigSize - NewSize;
1740 BBSizes[MBB->getNumber()] -= delta;
1741 AdjustBBOffsetsAfter(MBB, -delta);
1751 /// ReorderThumb2JumpTables - Adjust the function's block layout to ensure that
1752 /// jump tables always branch forwards, since that's what tbb and tbh need.
1753 bool ARMConstantIslands::ReorderThumb2JumpTables(MachineFunction &MF) {
1754 bool MadeChange = false;
1756 MachineJumpTableInfo *MJTI = MF.getJumpTableInfo();
1757 if (MJTI == 0) return false;
1759 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1760 for (unsigned i = 0, e = T2JumpTables.size(); i != e; ++i) {
1761 MachineInstr *MI = T2JumpTables[i];
1762 const TargetInstrDesc &TID = MI->getDesc();
1763 unsigned NumOps = TID.getNumOperands();
1764 unsigned JTOpIdx = NumOps - (TID.isPredicable() ? 3 : 2);
1765 MachineOperand JTOP = MI->getOperand(JTOpIdx);
1766 unsigned JTI = JTOP.getIndex();
1767 assert(JTI < JT.size());
1769 // We prefer if target blocks for the jump table come after the jump
1770 // instruction so we can use TB[BH]. Loop through the target blocks
1771 // and try to adjust them such that that's true.
1772 int JTNumber = MI->getParent()->getNumber();
1773 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1774 for (unsigned j = 0, ee = JTBBs.size(); j != ee; ++j) {
1775 MachineBasicBlock *MBB = JTBBs[j];
1776 int DTNumber = MBB->getNumber();
1778 if (DTNumber < JTNumber) {
1779 // The destination precedes the switch. Try to move the block forward
1780 // so we have a positive offset.
1781 MachineBasicBlock *NewBB =
1782 AdjustJTTargetBlockForward(MBB, MI->getParent());
1784 MJTI->ReplaceMBBInJumpTable(JTI, JTBBs[j], NewBB);
1793 MachineBasicBlock *ARMConstantIslands::
1794 AdjustJTTargetBlockForward(MachineBasicBlock *BB, MachineBasicBlock *JTBB)
1796 MachineFunction &MF = *BB->getParent();
1798 // If the destination block is terminated by an unconditional branch,
1799 // try to move it; otherwise, create a new block following the jump
1800 // table that branches back to the actual target. This is a very simple
1801 // heuristic. FIXME: We can definitely improve it.
1802 MachineBasicBlock *TBB = 0, *FBB = 0;
1803 SmallVector<MachineOperand, 4> Cond;
1804 SmallVector<MachineOperand, 4> CondPrior;
1805 MachineFunction::iterator BBi = BB;
1806 MachineFunction::iterator OldPrior = prior(BBi);
1808 // If the block terminator isn't analyzable, don't try to move the block
1809 bool B = TII->AnalyzeBranch(*BB, TBB, FBB, Cond);
1811 // If the block ends in an unconditional branch, move it. The prior block
1812 // has to have an analyzable terminator for us to move this one. Be paranoid
1813 // and make sure we're not trying to move the entry block of the function.
1814 if (!B && Cond.empty() && BB != MF.begin() &&
1815 !TII->AnalyzeBranch(*OldPrior, TBB, FBB, CondPrior)) {
1816 BB->moveAfter(JTBB);
1817 OldPrior->updateTerminator();
1818 BB->updateTerminator();
1819 // Update numbering to account for the block being moved.
1820 MF.RenumberBlocks();
1825 // Create a new MBB for the code after the jump BB.
1826 MachineBasicBlock *NewBB =
1827 MF.CreateMachineBasicBlock(JTBB->getBasicBlock());
1828 MachineFunction::iterator MBBI = JTBB; ++MBBI;
1829 MF.insert(MBBI, NewBB);
1831 // Add an unconditional branch from NewBB to BB.
1832 // There doesn't seem to be meaningful DebugInfo available; this doesn't
1833 // correspond directly to anything in the source.
1834 assert (isThumb2 && "Adjusting for TB[BH] but not in Thumb2?");
1835 BuildMI(NewBB, DebugLoc(), TII->get(ARM::t2B)).addMBB(BB);
1837 // Update internal data structures to account for the newly inserted MBB.
1838 MF.RenumberBlocks(NewBB);
1841 NewBB->addSuccessor(BB);
1842 JTBB->removeSuccessor(BB);
1843 JTBB->addSuccessor(NewBB);