1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/MachineCodeEmitter.h"
28 #include "llvm/CodeGen/JITCodeEmitter.h"
29 #include "llvm/CodeGen/ObjectCodeEmitter.h"
30 #include "llvm/CodeGen/MachineConstantPool.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineInstr.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/Passes.h"
35 #include "llvm/ADT/Statistic.h"
36 #include "llvm/Support/Compiler.h"
37 #include "llvm/Support/Debug.h"
43 STATISTIC(NumEmitted, "Number of machine instructions emitted");
47 class ARMCodeEmitter {
49 /// getBinaryCodeForInstr - This function, generated by the
50 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
51 /// machine instructions.
52 unsigned getBinaryCodeForInstr(const MachineInstr &MI);
55 template<class CodeEmitter>
56 class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass,
57 public ARMCodeEmitter {
59 const ARMInstrInfo *II;
63 const std::vector<MachineConstantPoolEntry> *MCPEs;
64 const std::vector<MachineJumpTableEntry> *MJTEs;
69 explicit Emitter(TargetMachine &tm, CodeEmitter &mce)
70 : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm),
71 MCE(mce), MCPEs(0), MJTEs(0),
72 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
73 Emitter(TargetMachine &tm, CodeEmitter &mce,
74 const ARMInstrInfo &ii, const TargetData &td)
75 : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm),
76 MCE(mce), MCPEs(0), MJTEs(0),
77 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
79 bool runOnMachineFunction(MachineFunction &MF);
81 virtual const char *getPassName() const {
82 return "ARM Machine Code Emitter";
85 void emitInstruction(const MachineInstr &MI);
89 void emitWordLE(unsigned Binary);
91 void emitDWordLE(uint64_t Binary);
93 void emitConstPoolInstruction(const MachineInstr &MI);
95 void emitMOVi2piecesInstruction(const MachineInstr &MI);
97 void emitLEApcrelJTInstruction(const MachineInstr &MI);
99 void emitPseudoMoveInstruction(const MachineInstr &MI);
101 void addPCLabel(unsigned LabelID);
103 void emitPseudoInstruction(const MachineInstr &MI);
105 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
106 const TargetInstrDesc &TID,
107 const MachineOperand &MO,
110 unsigned getMachineSoImmOpValue(unsigned SoImm);
112 unsigned getAddrModeSBit(const MachineInstr &MI,
113 const TargetInstrDesc &TID) const;
115 void emitDataProcessingInstruction(const MachineInstr &MI,
116 unsigned ImplicitRd = 0,
117 unsigned ImplicitRn = 0);
119 void emitLoadStoreInstruction(const MachineInstr &MI,
120 unsigned ImplicitRd = 0,
121 unsigned ImplicitRn = 0);
123 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
124 unsigned ImplicitRn = 0);
126 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
128 void emitMulFrmInstruction(const MachineInstr &MI);
130 void emitExtendInstruction(const MachineInstr &MI);
132 void emitMiscArithInstruction(const MachineInstr &MI);
134 void emitBranchInstruction(const MachineInstr &MI);
136 void emitInlineJumpTable(unsigned JTIndex);
138 void emitMiscBranchInstruction(const MachineInstr &MI);
140 void emitVFPArithInstruction(const MachineInstr &MI);
142 void emitVFPConversionInstruction(const MachineInstr &MI);
144 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
146 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
148 void emitMiscInstruction(const MachineInstr &MI);
150 /// getMachineOpValue - Return binary encoding of operand. If the machine
151 /// operand requires relocation, record the relocation and return zero.
152 unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
153 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
154 return getMachineOpValue(MI, MI.getOperand(OpIdx));
157 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
159 unsigned getShiftOp(unsigned Imm) const ;
161 /// Routines that handle operands which add machine relocations which are
162 /// fixed up by the relocation stage.
163 void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
164 bool NeedStub, intptr_t ACPV = 0);
165 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
166 void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
167 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
168 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
169 intptr_t JTBase = 0);
171 template <class CodeEmitter>
172 char Emitter<CodeEmitter>::ID = 0;
175 /// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
176 /// to the specified MCE object.
178 FunctionPass *llvm::createARMCodeEmitterPass(ARMBaseTargetMachine &TM,
179 MachineCodeEmitter &MCE) {
180 return new Emitter<MachineCodeEmitter>(TM, MCE);
182 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
183 JITCodeEmitter &JCE) {
184 return new Emitter<JITCodeEmitter>(TM, JCE);
186 FunctionPass *llvm::createARMObjectCodeEmitterPass(ARMBaseTargetMachine &TM,
187 ObjectCodeEmitter &OCE) {
188 return new Emitter<ObjectCodeEmitter>(TM, OCE);
191 template<class CodeEmitter>
192 bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
193 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
194 MF.getTarget().getRelocationModel() != Reloc::Static) &&
195 "JIT relocation model must be set to static or default!");
196 II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
197 TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
198 JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
199 MCPEs = &MF.getConstantPool()->getConstants();
200 MJTEs = &MF.getJumpTableInfo()->getJumpTables();
201 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
202 JTI->Initialize(MF, IsPIC);
205 DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
206 MCE.startFunction(MF);
207 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
209 MCE.StartMachineBasicBlock(MBB);
210 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
214 } while (MCE.finishFunction(MF));
219 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
221 template<class CodeEmitter>
222 unsigned Emitter<CodeEmitter>::getShiftOp(unsigned Imm) const {
223 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
224 default: assert(0 && "Unknown shift opc!");
225 case ARM_AM::asr: return 2;
226 case ARM_AM::lsl: return 0;
227 case ARM_AM::lsr: return 1;
229 case ARM_AM::rrx: return 3;
234 /// getMachineOpValue - Return binary encoding of operand. If the machine
235 /// operand requires relocation, record the relocation and return zero.
236 template<class CodeEmitter>
237 unsigned Emitter<CodeEmitter>::getMachineOpValue(const MachineInstr &MI,
238 const MachineOperand &MO) {
240 return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
242 return static_cast<unsigned>(MO.getImm());
243 else if (MO.isGlobal())
244 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true);
245 else if (MO.isSymbol())
246 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
247 else if (MO.isCPI()) {
248 const TargetInstrDesc &TID = MI.getDesc();
249 // For VFP load, the immediate offset is multiplied by 4.
250 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
251 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
252 emitConstPoolAddress(MO.getIndex(), Reloc);
253 } else if (MO.isJTI())
254 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
256 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
258 cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
264 /// emitGlobalAddress - Emit the specified address to the code stream.
266 template<class CodeEmitter>
267 void Emitter<CodeEmitter>::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
268 bool NeedStub, intptr_t ACPV) {
269 MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
270 GV, ACPV, NeedStub));
273 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
274 /// be emitted to the current location in the function, and allow it to be PC
276 template<class CodeEmitter>
277 void Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES,
279 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
283 /// emitConstPoolAddress - Arrange for the address of an constant pool
284 /// to be emitted to the current location in the function, and allow it to be PC
286 template<class CodeEmitter>
287 void Emitter<CodeEmitter>::emitConstPoolAddress(unsigned CPI,
289 // Tell JIT emitter we'll resolve the address.
290 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
291 Reloc, CPI, 0, true));
294 /// emitJumpTableAddress - Arrange for the address of a jump table to
295 /// be emitted to the current location in the function, and allow it to be PC
297 template<class CodeEmitter>
298 void Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTIndex,
300 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
301 Reloc, JTIndex, 0, true));
304 /// emitMachineBasicBlock - Emit the specified address basic block.
305 template<class CodeEmitter>
306 void Emitter<CodeEmitter>::emitMachineBasicBlock(MachineBasicBlock *BB,
307 unsigned Reloc, intptr_t JTBase) {
308 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
312 template<class CodeEmitter>
313 void Emitter<CodeEmitter>::emitWordLE(unsigned Binary) {
315 DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0')
316 << Binary << std::dec << "\n";
318 MCE.emitWordLE(Binary);
321 template<class CodeEmitter>
322 void Emitter<CodeEmitter>::emitDWordLE(uint64_t Binary) {
324 DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0')
325 << (unsigned)Binary << std::dec << "\n";
326 DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0')
327 << (unsigned)(Binary >> 32) << std::dec << "\n";
329 MCE.emitDWordLE(Binary);
332 template<class CodeEmitter>
333 void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI) {
334 DOUT << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI;
336 NumEmitted++; // Keep track of the # of mi's emitted
337 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
339 assert(0 && "Unhandled instruction encoding format!");
343 emitPseudoInstruction(MI);
346 case ARMII::DPSoRegFrm:
347 emitDataProcessingInstruction(MI);
351 emitLoadStoreInstruction(MI);
353 case ARMII::LdMiscFrm:
354 case ARMII::StMiscFrm:
355 emitMiscLoadStoreInstruction(MI);
357 case ARMII::LdStMulFrm:
358 emitLoadStoreMultipleInstruction(MI);
361 emitMulFrmInstruction(MI);
364 emitExtendInstruction(MI);
366 case ARMII::ArithMiscFrm:
367 emitMiscArithInstruction(MI);
370 emitBranchInstruction(MI);
372 case ARMII::BrMiscFrm:
373 emitMiscBranchInstruction(MI);
376 case ARMII::VFPUnaryFrm:
377 case ARMII::VFPBinaryFrm:
378 emitVFPArithInstruction(MI);
380 case ARMII::VFPConv1Frm:
381 case ARMII::VFPConv2Frm:
382 case ARMII::VFPConv3Frm:
383 case ARMII::VFPConv4Frm:
384 case ARMII::VFPConv5Frm:
385 emitVFPConversionInstruction(MI);
387 case ARMII::VFPLdStFrm:
388 emitVFPLoadStoreInstruction(MI);
390 case ARMII::VFPLdStMulFrm:
391 emitVFPLoadStoreMultipleInstruction(MI);
393 case ARMII::VFPMiscFrm:
394 emitMiscInstruction(MI);
399 template<class CodeEmitter>
400 void Emitter<CodeEmitter>::emitConstPoolInstruction(const MachineInstr &MI) {
401 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
402 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
403 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
405 // Remember the CONSTPOOL_ENTRY address for later relocation.
406 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
408 // Emit constpool island entry. In most cases, the actual values will be
409 // resolved and relocated after code emission.
410 if (MCPE.isMachineConstantPoolEntry()) {
411 ARMConstantPoolValue *ACPV =
412 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
414 DOUT << " ** ARM constant pool #" << CPI << " @ "
415 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n';
417 GlobalValue *GV = ACPV->getGV();
419 assert(!ACPV->isStub() && "Don't know how to deal this yet!");
420 if (ACPV->isNonLazyPointer())
421 MCE.addRelocation(MachineRelocation::getIndirectSymbol(
422 MCE.getCurrentPCOffset(), ARM::reloc_arm_machine_cp_entry, GV,
423 (intptr_t)ACPV, false));
425 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
426 ACPV->isStub() || isa<Function>(GV), (intptr_t)ACPV);
428 assert(!ACPV->isNonLazyPointer() && "Don't know how to deal this yet!");
429 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
433 Constant *CV = MCPE.Val.ConstVal;
436 DOUT << " ** Constant pool #" << CPI << " @ "
437 << (void*)MCE.getCurrentPCValue() << " ";
438 if (const Function *F = dyn_cast<Function>(CV))
439 DOUT << F->getName();
445 if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
446 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV));
448 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
449 uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
451 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
452 if (CFP->getType() == Type::FloatTy)
453 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
454 else if (CFP->getType() == Type::DoubleTy)
455 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
457 assert(0 && "Unable to handle this constantpool entry!");
461 assert(0 && "Unable to handle this constantpool entry!");
467 template<class CodeEmitter>
468 void Emitter<CodeEmitter>::emitMOVi2piecesInstruction(const MachineInstr &MI) {
469 const MachineOperand &MO0 = MI.getOperand(0);
470 const MachineOperand &MO1 = MI.getOperand(1);
471 assert(MO1.isImm() && "Not a valid so_imm value!");
472 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
473 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
475 // Emit the 'mov' instruction.
476 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
478 // Set the conditional execution predicate.
479 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
482 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
485 // Set bit I(25) to identify this is the immediate form of <shifter_op>
486 Binary |= 1 << ARMII::I_BitShift;
487 Binary |= getMachineSoImmOpValue(ARM_AM::getSOImmVal(V1));
490 // Now the 'orr' instruction.
491 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
493 // Set the conditional execution predicate.
494 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
497 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
500 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
503 // Set bit I(25) to identify this is the immediate form of <shifter_op>
504 Binary |= 1 << ARMII::I_BitShift;
505 Binary |= getMachineSoImmOpValue(ARM_AM::getSOImmVal(V2));
509 template<class CodeEmitter>
510 void Emitter<CodeEmitter>::emitLEApcrelJTInstruction(const MachineInstr &MI) {
511 // It's basically add r, pc, (LJTI - $+8)
513 const TargetInstrDesc &TID = MI.getDesc();
515 // Emit the 'add' instruction.
516 unsigned Binary = 0x4 << 21; // add: Insts{24-31} = 0b0100
518 // Set the conditional execution predicate
519 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
521 // Encode S bit if MI modifies CPSR.
522 Binary |= getAddrModeSBit(MI, TID);
525 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
527 // Encode Rn which is PC.
528 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
530 // Encode the displacement.
531 // Set bit I(25) to identify this is the immediate form of <shifter_op>.
532 Binary |= 1 << ARMII::I_BitShift;
533 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
538 template<class CodeEmitter>
539 void Emitter<CodeEmitter>::emitPseudoMoveInstruction(const MachineInstr &MI) {
540 unsigned Opcode = MI.getDesc().Opcode;
542 // Part of binary is determined by TableGn.
543 unsigned Binary = getBinaryCodeForInstr(MI);
545 // Set the conditional execution predicate
546 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
548 // Encode S bit if MI modifies CPSR.
549 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
550 Binary |= 1 << ARMII::S_BitShift;
552 // Encode register def if there is one.
553 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
555 // Encode the shift operation.
562 case ARM::MOVsrl_flag:
564 Binary |= (0x2 << 4) | (1 << 7);
566 case ARM::MOVsra_flag:
568 Binary |= (0x4 << 4) | (1 << 7);
572 // Encode register Rm.
573 Binary |= getMachineOpValue(MI, 1);
578 template<class CodeEmitter>
579 void Emitter<CodeEmitter>::addPCLabel(unsigned LabelID) {
580 DOUT << " ** LPC" << LabelID << " @ "
581 << (void*)MCE.getCurrentPCValue() << '\n';
582 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
585 template<class CodeEmitter>
586 void Emitter<CodeEmitter>::emitPseudoInstruction(const MachineInstr &MI) {
587 unsigned Opcode = MI.getDesc().Opcode;
591 case TargetInstrInfo::INLINEASM: {
592 // We allow inline assembler nodes with empty bodies - they can
593 // implicitly define registers, which is ok for JIT.
594 if (MI.getOperand(0).getSymbolName()[0]) {
595 assert(0 && "JIT does not support inline asm!\n");
600 case TargetInstrInfo::DBG_LABEL:
601 case TargetInstrInfo::EH_LABEL:
602 MCE.emitLabel(MI.getOperand(0).getImm());
604 case TargetInstrInfo::IMPLICIT_DEF:
605 case TargetInstrInfo::DECLARE:
609 case ARM::CONSTPOOL_ENTRY:
610 emitConstPoolInstruction(MI);
613 // Remember of the address of the PC label for relocation later.
614 addPCLabel(MI.getOperand(2).getImm());
615 // PICADD is just an add instruction that implicitly read pc.
616 emitDataProcessingInstruction(MI, 0, ARM::PC);
623 // Remember of the address of the PC label for relocation later.
624 addPCLabel(MI.getOperand(2).getImm());
625 // These are just load / store instructions that implicitly read pc.
626 emitLoadStoreInstruction(MI, 0, ARM::PC);
633 // Remember of the address of the PC label for relocation later.
634 addPCLabel(MI.getOperand(2).getImm());
635 // These are just load / store instructions that implicitly read pc.
636 emitMiscLoadStoreInstruction(MI, ARM::PC);
639 case ARM::MOVi2pieces:
640 // Two instructions to materialize a constant.
641 emitMOVi2piecesInstruction(MI);
643 case ARM::LEApcrelJT:
644 // Materialize jumptable address.
645 emitLEApcrelJTInstruction(MI);
648 case ARM::MOVsrl_flag:
649 case ARM::MOVsra_flag:
650 emitPseudoMoveInstruction(MI);
655 template<class CodeEmitter>
656 unsigned Emitter<CodeEmitter>::getMachineSoRegOpValue(
657 const MachineInstr &MI,
658 const TargetInstrDesc &TID,
659 const MachineOperand &MO,
661 unsigned Binary = getMachineOpValue(MI, MO);
663 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
664 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
665 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
667 // Encode the shift opcode.
669 unsigned Rs = MO1.getReg();
671 // Set shift operand (bit[7:4]).
676 // RRX - 0110 and bit[11:8] clear.
678 default: assert(0 && "Unknown shift opc!");
679 case ARM_AM::lsl: SBits = 0x1; break;
680 case ARM_AM::lsr: SBits = 0x3; break;
681 case ARM_AM::asr: SBits = 0x5; break;
682 case ARM_AM::ror: SBits = 0x7; break;
683 case ARM_AM::rrx: SBits = 0x6; break;
686 // Set shift operand (bit[6:4]).
692 default: assert(0 && "Unknown shift opc!");
693 case ARM_AM::lsl: SBits = 0x0; break;
694 case ARM_AM::lsr: SBits = 0x2; break;
695 case ARM_AM::asr: SBits = 0x4; break;
696 case ARM_AM::ror: SBits = 0x6; break;
699 Binary |= SBits << 4;
700 if (SOpc == ARM_AM::rrx)
703 // Encode the shift operation Rs or shift_imm (except rrx).
705 // Encode Rs bit[11:8].
706 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
708 (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
711 // Encode shift_imm bit[11:7].
712 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
715 template<class CodeEmitter>
716 unsigned Emitter<CodeEmitter>::getMachineSoImmOpValue(unsigned SoImm) {
717 // Encode rotate_imm.
718 unsigned Binary = (ARM_AM::getSOImmValRot(SoImm) >> 1)
719 << ARMII::SoRotImmShift;
722 Binary |= ARM_AM::getSOImmValImm(SoImm);
726 template<class CodeEmitter>
727 unsigned Emitter<CodeEmitter>::getAddrModeSBit(const MachineInstr &MI,
728 const TargetInstrDesc &TID) const {
729 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
730 const MachineOperand &MO = MI.getOperand(i-1);
731 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
732 return 1 << ARMII::S_BitShift;
737 template<class CodeEmitter>
738 void Emitter<CodeEmitter>::emitDataProcessingInstruction(
739 const MachineInstr &MI,
741 unsigned ImplicitRn) {
742 const TargetInstrDesc &TID = MI.getDesc();
744 if (TID.Opcode == ARM::BFC) {
745 cerr << "ERROR: ARMv6t2 JIT is not yet supported.\n";
749 // Part of binary is determined by TableGn.
750 unsigned Binary = getBinaryCodeForInstr(MI);
752 // Set the conditional execution predicate
753 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
755 // Encode S bit if MI modifies CPSR.
756 Binary |= getAddrModeSBit(MI, TID);
758 // Encode register def if there is one.
759 unsigned NumDefs = TID.getNumDefs();
762 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
764 // Special handling for implicit use (e.g. PC).
765 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
766 << ARMII::RegRdShift);
768 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
769 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
772 // Encode first non-shifter register operand if there is one.
773 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
776 // Special handling for implicit use (e.g. PC).
777 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
778 << ARMII::RegRnShift);
780 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
785 // Encode shifter operand.
786 const MachineOperand &MO = MI.getOperand(OpIdx);
787 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
789 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
794 // Encode register Rm.
795 emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
800 // Set bit I(25) to identify this is the immediate form of <shifter_op>.
801 Binary |= 1 << ARMII::I_BitShift;
802 Binary |= getMachineSoImmOpValue(MO.getImm());
807 template<class CodeEmitter>
808 void Emitter<CodeEmitter>::emitLoadStoreInstruction(
809 const MachineInstr &MI,
811 unsigned ImplicitRn) {
812 const TargetInstrDesc &TID = MI.getDesc();
813 unsigned Form = TID.TSFlags & ARMII::FormMask;
814 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
816 // Part of binary is determined by TableGn.
817 unsigned Binary = getBinaryCodeForInstr(MI);
819 // Set the conditional execution predicate
820 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
824 // Operand 0 of a pre- and post-indexed store is the address base
825 // writeback. Skip it.
826 bool Skipped = false;
827 if (IsPrePost && Form == ARMII::StFrm) {
834 // Special handling for implicit use (e.g. PC).
835 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
836 << ARMII::RegRdShift);
838 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
840 // Set second operand
842 // Special handling for implicit use (e.g. PC).
843 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
844 << ARMII::RegRnShift);
846 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
848 // If this is a two-address operand, skip it. e.g. LDR_PRE.
849 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
852 const MachineOperand &MO2 = MI.getOperand(OpIdx);
853 unsigned AM2Opc = (ImplicitRn == ARM::PC)
854 ? 0 : MI.getOperand(OpIdx+1).getImm();
856 // Set bit U(23) according to sign of immed value (positive or negative).
857 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
859 if (!MO2.getReg()) { // is immediate
860 if (ARM_AM::getAM2Offset(AM2Opc))
861 // Set the value of offset_12 field
862 Binary |= ARM_AM::getAM2Offset(AM2Opc);
867 // Set bit I(25), because this is not in immediate enconding.
868 Binary |= 1 << ARMII::I_BitShift;
869 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
870 // Set bit[3:0] to the corresponding Rm register
871 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
873 // If this instr is in scaled register offset/index instruction, set
874 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
875 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
876 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
877 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
883 template<class CodeEmitter>
884 void Emitter<CodeEmitter>::emitMiscLoadStoreInstruction(const MachineInstr &MI,
885 unsigned ImplicitRn) {
886 const TargetInstrDesc &TID = MI.getDesc();
887 unsigned Form = TID.TSFlags & ARMII::FormMask;
888 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
890 // Part of binary is determined by TableGn.
891 unsigned Binary = getBinaryCodeForInstr(MI);
893 // Set the conditional execution predicate
894 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
898 // Operand 0 of a pre- and post-indexed store is the address base
899 // writeback. Skip it.
900 bool Skipped = false;
901 if (IsPrePost && Form == ARMII::StMiscFrm) {
907 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
909 // Skip LDRD and STRD's second operand.
910 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
913 // Set second operand
915 // Special handling for implicit use (e.g. PC).
916 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
917 << ARMII::RegRnShift);
919 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
921 // If this is a two-address operand, skip it. e.g. LDRH_POST.
922 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
925 const MachineOperand &MO2 = MI.getOperand(OpIdx);
926 unsigned AM3Opc = (ImplicitRn == ARM::PC)
927 ? 0 : MI.getOperand(OpIdx+1).getImm();
929 // Set bit U(23) according to sign of immed value (positive or negative)
930 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
933 // If this instr is in register offset/index encoding, set bit[3:0]
934 // to the corresponding Rm register.
936 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
941 // This instr is in immediate offset/index encoding, set bit 22 to 1.
942 Binary |= 1 << ARMII::AM3_I_BitShift;
943 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
945 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
946 Binary |= (ImmOffs & 0xF); // immedL
952 static unsigned getAddrModeUPBits(unsigned Mode) {
955 // Set addressing mode by modifying bits U(23) and P(24)
956 // IA - Increment after - bit U = 1 and bit P = 0
957 // IB - Increment before - bit U = 1 and bit P = 1
958 // DA - Decrement after - bit U = 0 and bit P = 0
959 // DB - Decrement before - bit U = 0 and bit P = 1
961 default: assert(0 && "Unknown addressing sub-mode!");
962 case ARM_AM::da: break;
963 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
964 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
965 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
971 template<class CodeEmitter>
972 void Emitter<CodeEmitter>::emitLoadStoreMultipleInstruction(
973 const MachineInstr &MI) {
974 // Part of binary is determined by TableGn.
975 unsigned Binary = getBinaryCodeForInstr(MI);
977 // Set the conditional execution predicate
978 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
980 // Set base address operand
981 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
983 // Set addressing mode by modifying bits U(23) and P(24)
984 const MachineOperand &MO = MI.getOperand(1);
985 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
988 if (ARM_AM::getAM4WBFlag(MO.getImm()))
989 Binary |= 0x1 << ARMII::W_BitShift;
992 for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) {
993 const MachineOperand &MO = MI.getOperand(i);
994 if (!MO.isReg() || MO.isImplicit())
996 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
997 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
999 Binary |= 0x1 << RegNum;
1005 template<class CodeEmitter>
1006 void Emitter<CodeEmitter>::emitMulFrmInstruction(const MachineInstr &MI) {
1007 const TargetInstrDesc &TID = MI.getDesc();
1009 // Part of binary is determined by TableGn.
1010 unsigned Binary = getBinaryCodeForInstr(MI);
1012 // Set the conditional execution predicate
1013 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1015 // Encode S bit if MI modifies CPSR.
1016 Binary |= getAddrModeSBit(MI, TID);
1018 // 32x32->64bit operations have two destination registers. The number
1019 // of register definitions will tell us if that's what we're dealing with.
1021 if (TID.getNumDefs() == 2)
1022 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1025 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1028 Binary |= getMachineOpValue(MI, OpIdx++);
1031 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1033 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1034 // it as Rn (for multiply, that's in the same offset as RdLo.
1035 if (TID.getNumOperands() > OpIdx &&
1036 !TID.OpInfo[OpIdx].isPredicate() &&
1037 !TID.OpInfo[OpIdx].isOptionalDef())
1038 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1043 template<class CodeEmitter>
1044 void Emitter<CodeEmitter>::emitExtendInstruction(const MachineInstr &MI) {
1045 const TargetInstrDesc &TID = MI.getDesc();
1047 // Part of binary is determined by TableGn.
1048 unsigned Binary = getBinaryCodeForInstr(MI);
1050 // Set the conditional execution predicate
1051 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1056 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1058 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1059 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1061 // Two register operand form.
1063 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1066 Binary |= getMachineOpValue(MI, MO2);
1069 Binary |= getMachineOpValue(MI, MO1);
1072 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1073 if (MI.getOperand(OpIdx).isImm() &&
1074 !TID.OpInfo[OpIdx].isPredicate() &&
1075 !TID.OpInfo[OpIdx].isOptionalDef())
1076 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1081 template<class CodeEmitter>
1082 void Emitter<CodeEmitter>::emitMiscArithInstruction(const MachineInstr &MI) {
1083 const TargetInstrDesc &TID = MI.getDesc();
1085 // Part of binary is determined by TableGn.
1086 unsigned Binary = getBinaryCodeForInstr(MI);
1088 // Set the conditional execution predicate
1089 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1094 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1096 const MachineOperand &MO = MI.getOperand(OpIdx++);
1097 if (OpIdx == TID.getNumOperands() ||
1098 TID.OpInfo[OpIdx].isPredicate() ||
1099 TID.OpInfo[OpIdx].isOptionalDef()) {
1100 // Encode Rm and it's done.
1101 Binary |= getMachineOpValue(MI, MO);
1107 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1110 Binary |= getMachineOpValue(MI, OpIdx++);
1112 // Encode shift_imm.
1113 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1114 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1115 Binary |= ShiftAmt << ARMII::ShiftShift;
1120 template<class CodeEmitter>
1121 void Emitter<CodeEmitter>::emitBranchInstruction(const MachineInstr &MI) {
1122 const TargetInstrDesc &TID = MI.getDesc();
1124 if (TID.Opcode == ARM::TPsoft)
1127 // Part of binary is determined by TableGn.
1128 unsigned Binary = getBinaryCodeForInstr(MI);
1130 // Set the conditional execution predicate
1131 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1133 // Set signed_immed_24 field
1134 Binary |= getMachineOpValue(MI, 0);
1139 template<class CodeEmitter>
1140 void Emitter<CodeEmitter>::emitInlineJumpTable(unsigned JTIndex) {
1141 // Remember the base address of the inline jump table.
1142 uintptr_t JTBase = MCE.getCurrentPCValue();
1143 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1144 DOUT << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase << '\n';
1146 // Now emit the jump table entries.
1147 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1148 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1150 // DestBB address - JT base.
1151 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1153 // Absolute DestBB address.
1154 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1159 template<class CodeEmitter>
1160 void Emitter<CodeEmitter>::emitMiscBranchInstruction(const MachineInstr &MI) {
1161 const TargetInstrDesc &TID = MI.getDesc();
1163 // Handle jump tables.
1164 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd ||
1165 TID.Opcode == ARM::t2BR_JTr || TID.Opcode == ARM::t2BR_JTadd) {
1166 // First emit a ldr pc, [] instruction.
1167 emitDataProcessingInstruction(MI, ARM::PC);
1169 // Then emit the inline jump table.
1170 unsigned JTIndex = (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::t2BR_JTr)
1171 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1172 emitInlineJumpTable(JTIndex);
1174 } else if (TID.Opcode == ARM::BR_JTm || TID.Opcode == ARM::t2BR_JTm) {
1175 // First emit a ldr pc, [] instruction.
1176 emitLoadStoreInstruction(MI, ARM::PC);
1178 // Then emit the inline jump table.
1179 emitInlineJumpTable(MI.getOperand(3).getIndex());
1183 // Part of binary is determined by TableGn.
1184 unsigned Binary = getBinaryCodeForInstr(MI);
1186 // Set the conditional execution predicate
1187 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1189 if (TID.Opcode == ARM::BX_RET)
1190 // The return register is LR.
1191 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1193 // otherwise, set the return register
1194 Binary |= getMachineOpValue(MI, 0);
1199 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1200 unsigned RegD = MI.getOperand(OpIdx).getReg();
1201 unsigned Binary = 0;
1202 bool isSPVFP = false;
1203 RegD = ARMRegisterInfo::getRegisterNumbering(RegD, isSPVFP);
1205 Binary |= RegD << ARMII::RegRdShift;
1207 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1208 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1213 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1214 unsigned RegN = MI.getOperand(OpIdx).getReg();
1215 unsigned Binary = 0;
1216 bool isSPVFP = false;
1217 RegN = ARMRegisterInfo::getRegisterNumbering(RegN, isSPVFP);
1219 Binary |= RegN << ARMII::RegRnShift;
1221 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1222 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1227 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1228 unsigned RegM = MI.getOperand(OpIdx).getReg();
1229 unsigned Binary = 0;
1230 bool isSPVFP = false;
1231 RegM = ARMRegisterInfo::getRegisterNumbering(RegM, isSPVFP);
1235 Binary |= ((RegM & 0x1E) >> 1);
1236 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1241 template<class CodeEmitter>
1242 void Emitter<CodeEmitter>::emitVFPArithInstruction(const MachineInstr &MI) {
1243 const TargetInstrDesc &TID = MI.getDesc();
1245 // Part of binary is determined by TableGn.
1246 unsigned Binary = getBinaryCodeForInstr(MI);
1248 // Set the conditional execution predicate
1249 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1252 assert((Binary & ARMII::D_BitShift) == 0 &&
1253 (Binary & ARMII::N_BitShift) == 0 &&
1254 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1257 Binary |= encodeVFPRd(MI, OpIdx++);
1259 // If this is a two-address operand, skip it, e.g. FMACD.
1260 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1264 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1265 Binary |= encodeVFPRn(MI, OpIdx++);
1267 if (OpIdx == TID.getNumOperands() ||
1268 TID.OpInfo[OpIdx].isPredicate() ||
1269 TID.OpInfo[OpIdx].isOptionalDef()) {
1270 // FCMPEZD etc. has only one operand.
1276 Binary |= encodeVFPRm(MI, OpIdx);
1281 template<class CodeEmitter>
1282 void Emitter<CodeEmitter>::emitVFPConversionInstruction(
1283 const MachineInstr &MI) {
1284 const TargetInstrDesc &TID = MI.getDesc();
1285 unsigned Form = TID.TSFlags & ARMII::FormMask;
1287 // Part of binary is determined by TableGn.
1288 unsigned Binary = getBinaryCodeForInstr(MI);
1290 // Set the conditional execution predicate
1291 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1295 case ARMII::VFPConv1Frm:
1296 case ARMII::VFPConv2Frm:
1297 case ARMII::VFPConv3Frm:
1299 Binary |= encodeVFPRd(MI, 0);
1301 case ARMII::VFPConv4Frm:
1303 Binary |= encodeVFPRn(MI, 0);
1305 case ARMII::VFPConv5Frm:
1307 Binary |= encodeVFPRm(MI, 0);
1313 case ARMII::VFPConv1Frm:
1315 Binary |= encodeVFPRm(MI, 1);
1317 case ARMII::VFPConv2Frm:
1318 case ARMII::VFPConv3Frm:
1320 Binary |= encodeVFPRn(MI, 1);
1322 case ARMII::VFPConv4Frm:
1323 case ARMII::VFPConv5Frm:
1325 Binary |= encodeVFPRd(MI, 1);
1329 if (Form == ARMII::VFPConv5Frm)
1331 Binary |= encodeVFPRn(MI, 2);
1332 else if (Form == ARMII::VFPConv3Frm)
1334 Binary |= encodeVFPRm(MI, 2);
1339 template<class CodeEmitter>
1340 void Emitter<CodeEmitter>::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1341 // Part of binary is determined by TableGn.
1342 unsigned Binary = getBinaryCodeForInstr(MI);
1344 // Set the conditional execution predicate
1345 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1350 Binary |= encodeVFPRd(MI, OpIdx++);
1352 // Encode address base.
1353 const MachineOperand &Base = MI.getOperand(OpIdx++);
1354 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1356 // If there is a non-zero immediate offset, encode it.
1358 const MachineOperand &Offset = MI.getOperand(OpIdx);
1359 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1360 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1361 Binary |= 1 << ARMII::U_BitShift;
1368 // If immediate offset is omitted, default to +0.
1369 Binary |= 1 << ARMII::U_BitShift;
1374 template<class CodeEmitter>
1375 void Emitter<CodeEmitter>::emitVFPLoadStoreMultipleInstruction(
1376 const MachineInstr &MI) {
1377 // Part of binary is determined by TableGn.
1378 unsigned Binary = getBinaryCodeForInstr(MI);
1380 // Set the conditional execution predicate
1381 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1383 // Set base address operand
1384 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
1386 // Set addressing mode by modifying bits U(23) and P(24)
1387 const MachineOperand &MO = MI.getOperand(1);
1388 Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
1391 if (ARM_AM::getAM5WBFlag(MO.getImm()))
1392 Binary |= 0x1 << ARMII::W_BitShift;
1394 // First register is encoded in Dd.
1395 Binary |= encodeVFPRd(MI, 4);
1397 // Number of registers are encoded in offset field.
1398 unsigned NumRegs = 1;
1399 for (unsigned i = 5, e = MI.getNumOperands(); i != e; ++i) {
1400 const MachineOperand &MO = MI.getOperand(i);
1401 if (!MO.isReg() || MO.isImplicit())
1405 Binary |= NumRegs * 2;
1410 template<class CodeEmitter>
1411 void Emitter<CodeEmitter>::emitMiscInstruction(const MachineInstr &MI) {
1412 // Part of binary is determined by TableGn.
1413 unsigned Binary = getBinaryCodeForInstr(MI);
1415 // Set the conditional execution predicate
1416 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1421 #include "ARMGenCodeEmitter.inc"