1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/MachineCodeEmitter.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/Support/Compiler.h"
34 #include "llvm/Support/Debug.h"
37 STATISTIC(NumEmitted, "Number of machine instructions emitted");
40 class VISIBILITY_HIDDEN ARMCodeEmitter : public MachineFunctionPass {
42 const ARMInstrInfo *II;
45 MachineCodeEmitter &MCE;
46 const MachineConstantPool *MCP;
49 explicit ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce)
50 : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm),
52 ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce,
53 const ARMInstrInfo &ii, const TargetData &td)
54 : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm),
57 bool runOnMachineFunction(MachineFunction &MF);
59 virtual const char *getPassName() const {
60 return "ARM Machine Code Emitter";
63 void emitInstruction(const MachineInstr &MI);
67 void emitConstPoolInstruction(const MachineInstr &MI);
69 void emitPseudoInstruction(const MachineInstr &MI);
71 unsigned getAddrModeNoneInstrBinary(const MachineInstr &MI,
72 const TargetInstrDesc &TID,
75 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
76 const TargetInstrDesc &TID,
79 unsigned getAddrMode1SBit(const MachineInstr &MI,
80 const TargetInstrDesc &TID) const;
82 unsigned getAddrMode1InstrBinary(const MachineInstr &MI,
83 const TargetInstrDesc &TID,
85 unsigned getAddrMode2InstrBinary(const MachineInstr &MI,
86 const TargetInstrDesc &TID,
88 unsigned getAddrMode3InstrBinary(const MachineInstr &MI,
89 const TargetInstrDesc &TID,
91 unsigned getAddrMode4InstrBinary(const MachineInstr &MI,
92 const TargetInstrDesc &TID,
95 /// getInstrBinary - Return binary encoding for the specified
96 /// machine instruction.
97 unsigned getInstrBinary(const MachineInstr &MI);
99 /// getBinaryCodeForInstr - This function, generated by the
100 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
101 /// machine instructions.
103 unsigned getBinaryCodeForInstr(const MachineInstr &MI);
105 /// getMachineOpValue - Return binary encoding of operand. If the machine
106 /// operand requires relocation, record the relocation and return zero.
107 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
108 return getMachineOpValue(MI, MI.getOperand(OpIdx));
110 unsigned getMachineOpValue(const MachineInstr &MI,
111 const MachineOperand &MO);
113 /// getBaseOpcodeFor - Return the opcode value.
115 unsigned getBaseOpcodeFor(const TargetInstrDesc &TID) const {
116 return (TID.TSFlags & ARMII::OpcodeMask) >> ARMII::OpcodeShift;
119 /// getShiftOp - Return the shift opcode (bit[6:5]) of the machine operand.
121 unsigned getShiftOp(const MachineOperand &MO) const ;
123 /// Routines that handle operands which add machine relocations which are
124 /// fixed up by the JIT fixup stage.
125 void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
127 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
128 void emitConstPoolAddress(unsigned CPI, unsigned Reloc,
129 int Disp = 0, unsigned PCAdj = 0 );
130 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc,
132 void emitGlobalConstant(const Constant *CV);
133 void emitMachineBasicBlock(MachineBasicBlock *BB);
135 char ARMCodeEmitter::ID = 0;
138 /// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
139 /// to the specified MCE object.
140 FunctionPass *llvm::createARMCodeEmitterPass(ARMTargetMachine &TM,
141 MachineCodeEmitter &MCE) {
142 return new ARMCodeEmitter(TM, MCE);
145 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
146 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
147 MF.getTarget().getRelocationModel() != Reloc::Static) &&
148 "JIT relocation model must be set to static or default!");
149 II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
150 TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
151 JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
152 MCP = MF.getConstantPool();
155 DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
156 MCE.startFunction(MF);
157 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
159 MCE.StartMachineBasicBlock(MBB);
160 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
164 } while (MCE.finishFunction(MF));
169 /// getShiftOp - Return the shift opcode (bit[6:5]) of the machine operand.
171 unsigned ARMCodeEmitter::getShiftOp(const MachineOperand &MO) const {
172 switch (ARM_AM::getAM2ShiftOpc(MO.getImm())) {
173 default: assert(0 && "Unknown shift opc!");
174 case ARM_AM::asr: return 2;
175 case ARM_AM::lsl: return 0;
176 case ARM_AM::lsr: return 1;
178 case ARM_AM::rrx: return 3;
183 /// getMachineOpValue - Return binary encoding of operand. If the machine
184 /// operand requires relocation, record the relocation and return zero.
185 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
186 const MachineOperand &MO) {
188 return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
190 return static_cast<unsigned>(MO.getImm());
191 else if (MO.isGlobal())
192 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true);
193 else if (MO.isSymbol())
194 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_relative);
196 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
198 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
200 emitMachineBasicBlock(MO.getMBB());
202 cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
208 /// emitGlobalAddress - Emit the specified address to the code stream.
210 void ARMCodeEmitter::emitGlobalAddress(GlobalValue *GV,
211 unsigned Reloc, bool NeedStub) {
212 MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
213 Reloc, GV, 0, NeedStub));
216 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
217 /// be emitted to the current location in the function, and allow it to be PC
219 void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
220 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
224 /// emitConstPoolAddress - Arrange for the address of an constant pool
225 /// to be emitted to the current location in the function, and allow it to be PC
227 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
229 unsigned PCAdj /* = 0 */) {
230 // Tell JIT emitter we'll resolve the address.
231 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
232 Reloc, CPI, PCAdj, true));
235 /// emitJumpTableAddress - Arrange for the address of a jump table to
236 /// be emitted to the current location in the function, and allow it to be PC
238 void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc,
239 unsigned PCAdj /* = 0 */) {
240 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
241 Reloc, JTIndex, PCAdj));
244 /// emitMachineBasicBlock - Emit the specified address basic block.
245 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB) {
246 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
247 ARM::reloc_arm_branch, BB));
250 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
251 DOUT << "JIT: " << "0x" << MCE.getCurrentPCValue() << ":\t" << MI;
253 NumEmitted++; // Keep track of the # of mi's emitted
254 if ((MI.getDesc().TSFlags & ARMII::FormMask) == ARMII::Pseudo)
255 emitPseudoInstruction(MI);
257 MCE.emitWordLE(getInstrBinary(MI));
260 unsigned ARMCodeEmitter::getAddrModeNoneInstrBinary(const MachineInstr &MI,
261 const TargetInstrDesc &TID,
263 // Set the conditional execution predicate
264 Binary |= II->getPredicate(&MI) << 28;
266 switch (TID.TSFlags & ARMII::FormMask) {
268 assert(0 && "Unknown instruction subtype!");
270 case ARMII::Branch: {
271 // Set signed_immed_24 field
272 Binary |= getMachineOpValue(MI, 0);
274 // if it is a conditional branch, set cond field
275 if (TID.Opcode == ARM::Bcc) {
276 Binary &= 0x0FFFFFFF; // clear conditional field
277 Binary |= getMachineOpValue(MI, 1) << 28; // set conditional field
281 case ARMII::BranchMisc: {
282 if (TID.Opcode == ARM::BX)
284 if (TID.Opcode == ARM::BX_RET)
285 Binary |= 0xe; // the return register is LR
287 // otherwise, set the return register
288 Binary |= getMachineOpValue(MI, 0);
296 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
297 const TargetInstrDesc &TID,
299 // Set last operand (register Rm)
300 unsigned Binary = getMachineOpValue(MI, OpIdx);
302 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
303 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
304 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
306 // Encode the shift opcode.
308 unsigned Rs = MO1.getReg();
310 // Set shift operand (bit[7:4]).
315 // RRX - 0110 and bit[11:8] clear.
317 default: assert(0 && "Unknown shift opc!");
318 case ARM_AM::lsl: SBits = 0x1; break;
319 case ARM_AM::lsr: SBits = 0x3; break;
320 case ARM_AM::asr: SBits = 0x5; break;
321 case ARM_AM::ror: SBits = 0x7; break;
322 case ARM_AM::rrx: SBits = 0x6; break;
325 // Set shift operand (bit[6:4]).
331 default: assert(0 && "Unknown shift opc!");
332 case ARM_AM::lsl: SBits = 0x0; break;
333 case ARM_AM::lsr: SBits = 0x2; break;
334 case ARM_AM::asr: SBits = 0x4; break;
335 case ARM_AM::ror: SBits = 0x6; break;
338 Binary |= SBits << 4;
339 if (SOpc == ARM_AM::rrx)
342 // Encode the shift operation Rs or shift_imm (except rrx).
344 // Encode Rs bit[11:8].
345 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
347 (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
350 // Encode shift_imm bit[11:7].
351 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
354 unsigned ARMCodeEmitter::getAddrMode1SBit(const MachineInstr &MI,
355 const TargetInstrDesc &TID) const {
356 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
357 const MachineOperand &MO = MI.getOperand(i-1);
358 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
359 return 1 << ARMII::S_BitShift;
364 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
365 unsigned CPI = MI.getOperand(0).getImm();
366 unsigned CPIndex = MI.getOperand(1).getIndex();
367 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIndex];
369 // Remember the CONSTPOOL_ENTRY address for later relocation.
370 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
372 // Emit constpool island entry. In most cases, the actual values will be
373 // resolved and relocated after code emission.
374 if (MCPE.isMachineConstantPoolEntry()) {
375 ARMConstantPoolValue *ACPV =
376 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
378 DOUT << "\t** ARM constant pool #" << CPI << ", ' @ "
379 << (void*)MCE.getCurrentPCValue() << *ACPV << '\n';
381 GlobalValue *GV = ACPV->getGV();
383 assert(!ACPV->isStub() && "Don't know how to deal this yet!");
384 emitGlobalAddress(GV, ARM::reloc_arm_absolute, false);
386 assert(!ACPV->isNonLazyPointer() && "Don't know how to deal this yet!");
387 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
391 Constant *CV = MCPE.Val.ConstVal;
393 DOUT << "\t** Constant pool #" << CPI << ", ' @ "
394 << (void*)MCE.getCurrentPCValue() << *CV << '\n';
396 if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
397 emitGlobalAddress(GV, ARM::reloc_arm_absolute, false);
400 abort(); // FIXME: Is this right?
401 const ConstantInt *CI = dyn_cast<ConstantInt>(CV);
402 uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
408 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
409 unsigned Opcode = MI.getDesc().Opcode;
413 case ARM::CONSTPOOL_ENTRY: {
414 emitConstPoolInstruction(MI);
420 unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI,
421 const TargetInstrDesc &TID,
423 // Set the conditional execution predicate
424 Binary |= II->getPredicate(&MI) << 28;
426 // Encode S bit if MI modifies CPSR.
427 Binary |= getAddrMode1SBit(MI, TID);
429 // Encode register def if there is one.
430 unsigned NumDefs = TID.getNumDefs();
433 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdShift;
437 // Encode first non-shifter register operand if there is one.
438 unsigned Format = TID.TSFlags & ARMII::FormMask;
439 bool hasRnOperand= !(Format == ARMII::DPRdMisc ||
440 Format == ARMII::DPRdIm ||
441 Format == ARMII::DPRdReg ||
442 Format == ARMII::DPRdSoReg);
444 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
448 // Encode shifter operand.
449 bool HasSoReg = (Format == ARMII::DPRdSoReg ||
450 Format == ARMII::DPRnSoReg ||
451 Format == ARMII::DPRSoReg ||
452 Format == ARMII::DPRSoRegS);
455 return Binary | getMachineSoRegOpValue(MI, TID, OpIdx);
457 const MachineOperand &MO = MI.getOperand(OpIdx);
459 // Encode register Rm.
460 return Binary | getMachineOpValue(MI, NumDefs);
463 // Set bit I(25) to identify this is the immediate form of <shifter_op>
464 Binary |= 1 << ARMII::I_BitShift;
465 unsigned SoImm = MO.getImm();
466 // Encode rotate_imm.
467 Binary |= ARM_AM::getSOImmValRot(SoImm) << ARMII::RotImmShift;
469 Binary |= ARM_AM::getSOImmVal(SoImm);
473 unsigned ARMCodeEmitter::getAddrMode2InstrBinary(const MachineInstr &MI,
474 const TargetInstrDesc &TID,
476 // Set the conditional execution predicate
477 Binary |= II->getPredicate(&MI) << 28;
480 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
482 // Set second operand
483 Binary |= getMachineOpValue(MI, 1) << ARMII::RegRnShift;
485 const MachineOperand &MO2 = MI.getOperand(2);
486 const MachineOperand &MO3 = MI.getOperand(3);
488 // Set bit U(23) according to sign of immed value (positive or negative).
489 Binary |= ((ARM_AM::getAM2Op(MO3.getImm()) == ARM_AM::add ? 1 : 0) <<
491 if (!MO2.getReg()) { // is immediate
492 if (ARM_AM::getAM2Offset(MO3.getImm()))
493 // Set the value of offset_12 field
494 Binary |= ARM_AM::getAM2Offset(MO3.getImm());
498 // Set bit I(25), because this is not in immediate enconding.
499 Binary |= 1 << ARMII::I_BitShift;
500 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
501 // Set bit[3:0] to the corresponding Rm register
502 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
504 // if this instr is in scaled register offset/index instruction, set
505 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
506 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm())) {
507 Binary |= getShiftOp(MO3) << 5; // shift
508 Binary |= ShImm << 7; // shift_immed
514 unsigned ARMCodeEmitter::getAddrMode3InstrBinary(const MachineInstr &MI,
515 const TargetInstrDesc &TID,
517 // Set the conditional execution predicate
518 Binary |= II->getPredicate(&MI) << 28;
521 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
523 // Set second operand
524 Binary |= getMachineOpValue(MI, 1) << ARMII::RegRnShift;
526 const MachineOperand &MO2 = MI.getOperand(2);
527 const MachineOperand &MO3 = MI.getOperand(3);
529 // Set bit U(23) according to sign of immed value (positive or negative)
530 Binary |= ((ARM_AM::getAM2Op(MO3.getImm()) == ARM_AM::add ? 1 : 0) <<
533 // If this instr is in register offset/index encoding, set bit[3:0]
534 // to the corresponding Rm register.
536 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
540 // if this instr is in immediate offset/index encoding, set bit 22 to 1
541 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm())) {
544 Binary |= (ImmOffs >> 4) << 8; // immedH
545 Binary |= (ImmOffs & ~0xF); // immedL
551 unsigned ARMCodeEmitter::getAddrMode4InstrBinary(const MachineInstr &MI,
552 const TargetInstrDesc &TID,
554 // Set the conditional execution predicate
555 Binary |= II->getPredicate(&MI) << 28;
558 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
560 // Set addressing mode by modifying bits U(23) and P(24)
561 // IA - Increment after - bit U = 1 and bit P = 0
562 // IB - Increment before - bit U = 1 and bit P = 1
563 // DA - Decrement after - bit U = 0 and bit P = 0
564 // DB - Decrement before - bit U = 0 and bit P = 1
565 const MachineOperand &MO = MI.getOperand(1);
566 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO.getImm());
568 default: assert(0 && "Unknown addressing sub-mode!");
569 case ARM_AM::da: break;
570 case ARM_AM::db: Binary |= 0x1 << 24; break;
571 case ARM_AM::ia: Binary |= 0x1 << 23; break;
572 case ARM_AM::ib: Binary |= 0x3 << 23; break;
576 if (ARM_AM::getAM4WBFlag(MO.getImm()))
580 for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) {
581 const MachineOperand &MO = MI.getOperand(i);
582 if (MO.isReg() && MO.isImplicit())
584 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
585 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
587 Binary |= 0x1 << RegNum;
593 /// getInstrBinary - Return binary encoding for the specified
594 /// machine instruction.
595 unsigned ARMCodeEmitter::getInstrBinary(const MachineInstr &MI) {
596 // Part of binary is determined by TableGn.
597 unsigned Binary = getBinaryCodeForInstr(MI);
599 const TargetInstrDesc &TID = MI.getDesc();
600 switch (TID.TSFlags & ARMII::AddrModeMask) {
601 case ARMII::AddrModeNone:
602 return getAddrModeNoneInstrBinary(MI, TID, Binary);
603 case ARMII::AddrMode1:
604 return getAddrMode1InstrBinary(MI, TID, Binary);
605 case ARMII::AddrMode2:
606 return getAddrMode2InstrBinary(MI, TID, Binary);
607 case ARMII::AddrMode3:
608 return getAddrMode3InstrBinary(MI, TID, Binary);
609 case ARMII::AddrMode4:
610 return getAddrMode4InstrBinary(MI, TID, Binary);
617 #include "ARMGenCodeEmitter.inc"