1 //===- ARMBaseRegisterInfo.h - ARM Register Information Impl ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMBASEREGISTERINFO_H
15 #define ARMBASEREGISTERINFO_H
18 #include "llvm/Target/TargetRegisterInfo.h"
19 #include "ARMGenRegisterInfo.h.inc"
23 class ARMBaseInstrInfo;
26 /// Register allocation hints.
34 /// isARMLowRegister - Returns true if the register is low register r0-r7.
36 static inline bool isARMLowRegister(unsigned Reg) {
39 case R0: case R1: case R2: case R3:
40 case R4: case R5: case R6: case R7:
47 class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
49 const ARMBaseInstrInfo &TII;
50 const ARMSubtarget &STI;
52 /// FramePtr - ARM physical register used as frame ptr.
55 /// BasePtr - ARM physical register used as a base ptr in complex stack
56 /// frames. I.e., when we need a 3rd base, not just SP and FP, due to
57 /// variable size stack objects.
60 // Can be only subclassed.
61 explicit ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
62 const ARMSubtarget &STI);
64 // Return the opcode that implements 'Op', or 0 if no opcode
65 unsigned getOpcode(int Op) const;
68 /// getRegisterNumbering - Given the enum value for some register, e.g.
69 /// ARM::LR, return the number that it corresponds to (e.g. 14).
70 static unsigned getRegisterNumbering(unsigned Reg);
72 /// Code Generation virtual methods...
73 const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
75 BitVector getReservedRegs(const MachineFunction &MF) const;
77 /// getMatchingSuperRegClass - Return a subclass of the specified register
78 /// class A so that each register in it has a sub-register of the
79 /// specified sub-register index which is in the specified register class B.
80 virtual const TargetRegisterClass *
81 getMatchingSuperRegClass(const TargetRegisterClass *A,
82 const TargetRegisterClass *B, unsigned Idx) const;
84 /// canCombineSubRegIndices - Given a register class and a list of
85 /// subregister indices, return true if it's possible to combine the
86 /// subregister indices into one that corresponds to a larger
87 /// subregister. Return the new subregister index by reference. Note the
88 /// new index may be zero if the given subregisters can be combined to
89 /// form the whole register.
90 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC,
91 SmallVectorImpl<unsigned> &SubIndices,
92 unsigned &NewSubIdx) const;
94 const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const;
96 std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
97 getAllocationOrder(const TargetRegisterClass *RC,
98 unsigned HintType, unsigned HintReg,
99 const MachineFunction &MF) const;
101 unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
102 const MachineFunction &MF) const;
104 void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
105 MachineFunction &MF) const;
107 bool hasFP(const MachineFunction &MF) const;
108 bool hasBasePointer(const MachineFunction &MF) const;
110 bool canRealignStack(const MachineFunction &MF) const;
111 bool needsStackRealignment(const MachineFunction &MF) const;
112 int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const;
113 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const;
114 void materializeFrameBaseRegister(MachineBasicBlock::iterator I,
115 unsigned BaseReg, int FrameIdx,
116 int64_t Offset) const;
117 void resolveFrameIndex(MachineBasicBlock::iterator I,
118 unsigned BaseReg, int64_t Offset) const;
119 bool isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const;
121 bool cannotEliminateFrame(const MachineFunction &MF) const;
123 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
124 RegScavenger *RS = NULL) const;
126 // Debug information queries.
127 unsigned getRARegister() const;
128 unsigned getFrameRegister(const MachineFunction &MF) const;
129 int getFrameIndexReference(const MachineFunction &MF, int FI,
130 unsigned &FrameReg) const;
131 int ResolveFrameIndexReference(const MachineFunction &MF, int FI,
132 unsigned &FrameReg, int SPAdj) const;
133 int getFrameIndexOffset(const MachineFunction &MF, int FI) const;
135 // Exception handling queries.
136 unsigned getEHExceptionRegister() const;
137 unsigned getEHHandlerRegister() const;
139 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
141 bool isLowRegister(unsigned Reg) const;
144 /// emitLoadConstPool - Emits a load from constpool to materialize the
145 /// specified immediate.
146 virtual void emitLoadConstPool(MachineBasicBlock &MBB,
147 MachineBasicBlock::iterator &MBBI,
149 unsigned DestReg, unsigned SubIdx,
151 ARMCC::CondCodes Pred = ARMCC::AL,
152 unsigned PredReg = 0) const;
154 /// Code Generation virtual methods...
155 virtual bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
157 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const;
159 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const;
161 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const;
163 virtual bool hasReservedCallFrame(const MachineFunction &MF) const;
164 virtual bool canSimplifyCallFramePseudos(const MachineFunction &MF) const;
166 virtual void eliminateCallFramePseudoInstr(MachineFunction &MF,
167 MachineBasicBlock &MBB,
168 MachineBasicBlock::iterator I) const;
170 virtual void eliminateFrameIndex(MachineBasicBlock::iterator II,
171 int SPAdj, RegScavenger *RS = NULL) const;
173 virtual void emitPrologue(MachineFunction &MF) const;
174 virtual void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
177 unsigned estimateRSStackSizeLimit(MachineFunction &MF) const;
179 unsigned getRegisterPairEven(unsigned Reg, const MachineFunction &MF) const;
181 unsigned getRegisterPairOdd(unsigned Reg, const MachineFunction &MF) const;
184 } // end namespace llvm