1 //===- ARMBaseRegisterInfo.h - ARM Register Information Impl --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMBASEREGISTERINFO_H
15 #define ARMBASEREGISTERINFO_H
18 #include "llvm/Target/TargetRegisterInfo.h"
19 #include "ARMGenRegisterInfo.h.inc"
23 class TargetInstrInfo;
26 /// Register allocation hints.
34 /// isARMLowRegister - Returns true if the register is low register r0-r7.
36 static inline bool isARMLowRegister(unsigned Reg) {
39 case R0: case R1: case R2: case R3:
40 case R4: case R5: case R6: case R7:
47 struct ARMBaseRegisterInfo : public ARMGenRegisterInfo {
49 const TargetInstrInfo &TII;
50 const ARMSubtarget &STI;
52 /// FramePtr - ARM physical register used as frame ptr.
55 ARMBaseRegisterInfo(const TargetInstrInfo &tii, const ARMSubtarget &STI);
57 /// getRegisterNumbering - Given the enum value for some register, e.g.
58 /// ARM::LR, return the number that it corresponds to (e.g. 14).
59 static unsigned getRegisterNumbering(unsigned RegEnum);
61 /// Same as previous getRegisterNumbering except it returns true in isSPVFP
62 /// if the register is a single precision VFP register.
63 static unsigned getRegisterNumbering(unsigned RegEnum, bool &isSPVFP);
65 /// Code Generation virtual methods...
66 const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
68 const TargetRegisterClass* const*
69 getCalleeSavedRegClasses(const MachineFunction *MF = 0) const;
71 BitVector getReservedRegs(const MachineFunction &MF) const;
73 bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
75 const TargetRegisterClass *getPointerRegClass() const;
77 std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
78 getAllocationOrder(const TargetRegisterClass *RC,
79 unsigned HintType, unsigned HintReg,
80 const MachineFunction &MF) const;
82 unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
83 const MachineFunction &MF) const;
85 void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
86 MachineFunction &MF) const;
88 bool hasFP(const MachineFunction &MF) const;
90 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
91 RegScavenger *RS = NULL) const;
93 // Debug information queries.
94 unsigned getRARegister() const;
95 unsigned getFrameRegister(MachineFunction &MF) const;
97 // Exception handling queries.
98 unsigned getEHExceptionRegister() const;
99 unsigned getEHHandlerRegister() const;
101 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
103 bool isLowRegister(unsigned Reg) const;
106 unsigned getRegisterPairEven(unsigned Reg, const MachineFunction &MF) const;
108 unsigned getRegisterPairOdd(unsigned Reg, const MachineFunction &MF) const;
111 } // end namespace llvm