1 //===- ARMBaseRegisterInfo.h - ARM Register Information Impl ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMBASEREGISTERINFO_H
15 #define ARMBASEREGISTERINFO_H
18 #include "llvm/Target/TargetRegisterInfo.h"
19 #include "ARMGenRegisterInfo.h.inc"
23 class ARMBaseInstrInfo;
26 /// Register allocation hints.
34 /// isARMLowRegister - Returns true if the register is low register r0-r7.
36 static inline bool isARMLowRegister(unsigned Reg) {
39 case R0: case R1: case R2: case R3:
40 case R4: case R5: case R6: case R7:
47 class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
49 const ARMBaseInstrInfo &TII;
50 const ARMSubtarget &STI;
52 /// FramePtr - ARM physical register used as frame ptr.
55 /// BasePtr - ARM physical register used as a base ptr in complex stack
56 /// frames. I.e., when we need a 3rd base, not just SP and FP, due to
57 /// variable size stack objects.
60 // Can be only subclassed.
61 explicit ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
62 const ARMSubtarget &STI);
64 // Return the opcode that implements 'Op', or 0 if no opcode
65 unsigned getOpcode(int Op) const;
68 /// Code Generation virtual methods...
69 const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
71 BitVector getReservedRegs(const MachineFunction &MF) const;
73 /// getMatchingSuperRegClass - Return a subclass of the specified register
74 /// class A so that each register in it has a sub-register of the
75 /// specified sub-register index which is in the specified register class B.
76 virtual const TargetRegisterClass *
77 getMatchingSuperRegClass(const TargetRegisterClass *A,
78 const TargetRegisterClass *B, unsigned Idx) const;
80 /// canCombineSubRegIndices - Given a register class and a list of
81 /// subregister indices, return true if it's possible to combine the
82 /// subregister indices into one that corresponds to a larger
83 /// subregister. Return the new subregister index by reference. Note the
84 /// new index may be zero if the given subregisters can be combined to
85 /// form the whole register.
86 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC,
87 SmallVectorImpl<unsigned> &SubIndices,
88 unsigned &NewSubIdx) const;
90 const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const;
92 std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
93 getAllocationOrder(const TargetRegisterClass *RC,
94 unsigned HintType, unsigned HintReg,
95 const MachineFunction &MF) const;
97 unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
98 const MachineFunction &MF) const;
100 void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
101 MachineFunction &MF) const;
103 bool hasFP(const MachineFunction &MF) const;
104 bool hasBasePointer(const MachineFunction &MF) const;
106 bool canRealignStack(const MachineFunction &MF) const;
107 bool needsStackRealignment(const MachineFunction &MF) const;
108 int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const;
109 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const;
110 void materializeFrameBaseRegister(MachineBasicBlock::iterator I,
111 unsigned BaseReg, int FrameIdx,
112 int64_t Offset) const;
113 void resolveFrameIndex(MachineBasicBlock::iterator I,
114 unsigned BaseReg, int64_t Offset) const;
115 bool isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const;
117 bool cannotEliminateFrame(const MachineFunction &MF) const;
119 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
120 RegScavenger *RS = NULL) const;
122 // Debug information queries.
123 unsigned getRARegister() const;
124 unsigned getFrameRegister(const MachineFunction &MF) const;
125 unsigned getBaseRegister() const { return BasePtr; }
126 int getFrameIndexReference(const MachineFunction &MF, int FI,
127 unsigned &FrameReg) const;
128 int ResolveFrameIndexReference(const MachineFunction &MF, int FI,
129 unsigned &FrameReg, int SPAdj) const;
130 int getFrameIndexOffset(const MachineFunction &MF, int FI) const;
132 // Exception handling queries.
133 unsigned getEHExceptionRegister() const;
134 unsigned getEHHandlerRegister() const;
136 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
138 bool isLowRegister(unsigned Reg) const;
141 /// emitLoadConstPool - Emits a load from constpool to materialize the
142 /// specified immediate.
143 virtual void emitLoadConstPool(MachineBasicBlock &MBB,
144 MachineBasicBlock::iterator &MBBI,
146 unsigned DestReg, unsigned SubIdx,
148 ARMCC::CondCodes Pred = ARMCC::AL,
149 unsigned PredReg = 0) const;
151 /// Code Generation virtual methods...
152 virtual bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
154 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const;
156 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const;
158 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const;
160 virtual bool hasReservedCallFrame(const MachineFunction &MF) const;
161 virtual bool canSimplifyCallFramePseudos(const MachineFunction &MF) const;
163 virtual void eliminateCallFramePseudoInstr(MachineFunction &MF,
164 MachineBasicBlock &MBB,
165 MachineBasicBlock::iterator I) const;
167 virtual void eliminateFrameIndex(MachineBasicBlock::iterator II,
168 int SPAdj, RegScavenger *RS = NULL) const;
171 unsigned estimateRSStackSizeLimit(MachineFunction &MF) const;
173 unsigned getRegisterPairEven(unsigned Reg, const MachineFunction &MF) const;
175 unsigned getRegisterPairOdd(unsigned Reg, const MachineFunction &MF) const;
178 } // end namespace llvm