1 //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseRegisterInfo.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMFrameLowering.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSubtarget.h"
20 #include "MCTargetDesc/ARMAddressingModes.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/RegisterScavenging.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetFrameLowering.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/ADT/BitVector.h"
38 #include "llvm/ADT/SmallVector.h"
39 #include "llvm/Support/CommandLine.h"
41 #define GET_REGINFO_TARGET_DESC
42 #include "ARMGenRegisterInfo.inc"
47 ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false),
48 cl::desc("Force use of virtual base registers for stack load/store"));
50 EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden,
51 cl::desc("Enable pre-regalloc stack frame index allocation"));
53 EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
54 cl::desc("Enable use of a base pointer for complex stack frames"));
56 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
57 const ARMSubtarget &sti)
58 : ARMGenRegisterInfo(ARM::LR), TII(tii), STI(sti),
59 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
64 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
68 const Function *F = MF->getFunction();
69 ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
73 return CSR_GHC_SaveList;
76 return (STI.isTargetIOS() && !STI.isAAPCS_ABI())
77 ? CSR_iOS_SaveList : CSR_AAPCS_SaveList;
82 ARMBaseRegisterInfo::getCallPreservedMask(CallingConv::ID) const {
83 return (STI.isTargetIOS() && !STI.isAAPCS_ABI())
84 ? CSR_iOS_RegMask : CSR_AAPCS_RegMask;
87 BitVector ARMBaseRegisterInfo::
88 getReservedRegs(const MachineFunction &MF) const {
89 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
91 // FIXME: avoid re-calculating this every time.
92 BitVector Reserved(getNumRegs());
93 Reserved.set(ARM::SP);
94 Reserved.set(ARM::PC);
95 Reserved.set(ARM::FPSCR);
97 Reserved.set(FramePtr);
98 if (hasBasePointer(MF))
99 Reserved.set(BasePtr);
100 // Some targets reserve R9.
101 if (STI.isR9Reserved())
102 Reserved.set(ARM::R9);
103 // Reserve D16-D31 if the subtarget doesn't support them.
104 if (!STI.hasVFP3() || STI.hasD16()) {
105 assert(ARM::D31 == ARM::D16 + 15);
106 for (unsigned i = 0; i != 16; ++i)
107 Reserved.set(ARM::D16 + i);
112 bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
113 unsigned Reg) const {
114 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
122 if (hasBasePointer(MF))
127 if (FramePtr == Reg && TFI->hasFP(MF))
131 return STI.isR9Reserved();
138 ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
139 SmallVectorImpl<unsigned> &SubIndices,
140 unsigned &NewSubIdx) const {
142 unsigned Size = RC->getSize() * 8;
146 NewSubIdx = 0; // Whole register.
147 unsigned NumRegs = SubIndices.size();
149 // 8 D registers -> 1 QQQQ register.
150 return (Size == 512 &&
151 SubIndices[0] == ARM::dsub_0 &&
152 SubIndices[1] == ARM::dsub_1 &&
153 SubIndices[2] == ARM::dsub_2 &&
154 SubIndices[3] == ARM::dsub_3 &&
155 SubIndices[4] == ARM::dsub_4 &&
156 SubIndices[5] == ARM::dsub_5 &&
157 SubIndices[6] == ARM::dsub_6 &&
158 SubIndices[7] == ARM::dsub_7);
159 } else if (NumRegs == 4) {
160 if (SubIndices[0] == ARM::qsub_0) {
161 // 4 Q registers -> 1 QQQQ register.
162 return (Size == 512 &&
163 SubIndices[1] == ARM::qsub_1 &&
164 SubIndices[2] == ARM::qsub_2 &&
165 SubIndices[3] == ARM::qsub_3);
166 } else if (SubIndices[0] == ARM::dsub_0) {
167 // 4 D registers -> 1 QQ register.
169 SubIndices[1] == ARM::dsub_1 &&
170 SubIndices[2] == ARM::dsub_2 &&
171 SubIndices[3] == ARM::dsub_3) {
173 NewSubIdx = ARM::qqsub_0;
176 } else if (SubIndices[0] == ARM::dsub_4) {
177 // 4 D registers -> 1 QQ register (2nd).
179 SubIndices[1] == ARM::dsub_5 &&
180 SubIndices[2] == ARM::dsub_6 &&
181 SubIndices[3] == ARM::dsub_7) {
182 NewSubIdx = ARM::qqsub_1;
185 } else if (SubIndices[0] == ARM::ssub_0) {
186 // 4 S registers -> 1 Q register.
188 SubIndices[1] == ARM::ssub_1 &&
189 SubIndices[2] == ARM::ssub_2 &&
190 SubIndices[3] == ARM::ssub_3) {
192 NewSubIdx = ARM::qsub_0;
196 } else if (NumRegs == 2) {
197 if (SubIndices[0] == ARM::qsub_0) {
198 // 2 Q registers -> 1 QQ register.
199 if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
201 NewSubIdx = ARM::qqsub_0;
204 } else if (SubIndices[0] == ARM::qsub_2) {
205 // 2 Q registers -> 1 QQ register (2nd).
206 if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
207 NewSubIdx = ARM::qqsub_1;
210 } else if (SubIndices[0] == ARM::dsub_0) {
211 // 2 D registers -> 1 Q register.
212 if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
214 NewSubIdx = ARM::qsub_0;
217 } else if (SubIndices[0] == ARM::dsub_2) {
218 // 2 D registers -> 1 Q register (2nd).
219 if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
220 NewSubIdx = ARM::qsub_1;
223 } else if (SubIndices[0] == ARM::dsub_4) {
224 // 2 D registers -> 1 Q register (3rd).
225 if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
226 NewSubIdx = ARM::qsub_2;
229 } else if (SubIndices[0] == ARM::dsub_6) {
230 // 2 D registers -> 1 Q register (3rd).
231 if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
232 NewSubIdx = ARM::qsub_3;
235 } else if (SubIndices[0] == ARM::ssub_0) {
236 // 2 S registers -> 1 D register.
237 if (SubIndices[1] == ARM::ssub_1) {
239 NewSubIdx = ARM::dsub_0;
242 } else if (SubIndices[0] == ARM::ssub_2) {
243 // 2 S registers -> 1 D register (2nd).
244 if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
245 NewSubIdx = ARM::dsub_1;
253 const TargetRegisterClass*
254 ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
256 const TargetRegisterClass *Super = RC;
257 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
259 switch (Super->getID()) {
260 case ARM::GPRRegClassID:
261 case ARM::SPRRegClassID:
262 case ARM::DPRRegClassID:
263 case ARM::QPRRegClassID:
264 case ARM::QQPRRegClassID:
265 case ARM::QQQQPRRegClassID:
273 const TargetRegisterClass *
274 ARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
276 return &ARM::GPRRegClass;
279 const TargetRegisterClass *
280 ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
281 if (RC == &ARM::CCRRegClass)
282 return 0; // Can't copy CCR registers.
287 ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
288 MachineFunction &MF) const {
289 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
291 switch (RC->getID()) {
294 case ARM::tGPRRegClassID:
295 return TFI->hasFP(MF) ? 4 : 5;
296 case ARM::GPRRegClassID: {
297 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
298 return 10 - FP - (STI.isR9Reserved() ? 1 : 0);
300 case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
301 case ARM::DPRRegClassID:
306 /// getRawAllocationOrder - Returns the register allocation order for a
307 /// specified register class with a target-dependent hint.
309 ARMBaseRegisterInfo::getRawAllocationOrder(const TargetRegisterClass *RC,
310 unsigned HintType, unsigned HintReg,
311 const MachineFunction &MF) const {
312 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
313 // Alternative register allocation orders when favoring even / odd registers
314 // of register pairs.
316 // No FP, R9 is available.
317 static const uint16_t GPREven1[] = {
318 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
319 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
322 static const uint16_t GPROdd1[] = {
323 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
324 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
328 // FP is R7, R9 is available.
329 static const uint16_t GPREven2[] = {
330 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10,
331 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
334 static const uint16_t GPROdd2[] = {
335 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
336 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
340 // FP is R11, R9 is available.
341 static const uint16_t GPREven3[] = {
342 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
343 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
346 static const uint16_t GPROdd3[] = {
347 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
348 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
352 // No FP, R9 is not available.
353 static const uint16_t GPREven4[] = {
354 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10,
355 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
358 static const uint16_t GPROdd4[] = {
359 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11,
360 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
364 // FP is R7, R9 is not available.
365 static const uint16_t GPREven5[] = {
366 ARM::R0, ARM::R2, ARM::R4, ARM::R10,
367 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
370 static const uint16_t GPROdd5[] = {
371 ARM::R1, ARM::R3, ARM::R5, ARM::R11,
372 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
376 // FP is R11, R9 is not available.
377 static const uint16_t GPREven6[] = {
378 ARM::R0, ARM::R2, ARM::R4, ARM::R6,
379 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
381 static const uint16_t GPROdd6[] = {
382 ARM::R1, ARM::R3, ARM::R5, ARM::R7,
383 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
386 // We only support even/odd hints for GPR and rGPR.
387 if (RC != &ARM::GPRRegClass && RC != &ARM::rGPRRegClass)
388 return RC->getRawAllocationOrder(MF);
390 if (HintType == ARMRI::RegPairEven) {
391 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
392 // It's no longer possible to fulfill this hint. Return the default
394 return RC->getRawAllocationOrder(MF);
396 if (!TFI->hasFP(MF)) {
397 if (!STI.isR9Reserved())
398 return makeArrayRef(GPREven1);
400 return makeArrayRef(GPREven4);
401 } else if (FramePtr == ARM::R7) {
402 if (!STI.isR9Reserved())
403 return makeArrayRef(GPREven2);
405 return makeArrayRef(GPREven5);
406 } else { // FramePtr == ARM::R11
407 if (!STI.isR9Reserved())
408 return makeArrayRef(GPREven3);
410 return makeArrayRef(GPREven6);
412 } else if (HintType == ARMRI::RegPairOdd) {
413 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
414 // It's no longer possible to fulfill this hint. Return the default
416 return RC->getRawAllocationOrder(MF);
418 if (!TFI->hasFP(MF)) {
419 if (!STI.isR9Reserved())
420 return makeArrayRef(GPROdd1);
422 return makeArrayRef(GPROdd4);
423 } else if (FramePtr == ARM::R7) {
424 if (!STI.isR9Reserved())
425 return makeArrayRef(GPROdd2);
427 return makeArrayRef(GPROdd5);
428 } else { // FramePtr == ARM::R11
429 if (!STI.isR9Reserved())
430 return makeArrayRef(GPROdd3);
432 return makeArrayRef(GPROdd6);
435 return RC->getRawAllocationOrder(MF);
438 /// ResolveRegAllocHint - Resolves the specified register allocation hint
439 /// to a physical register. Returns the physical register if it is successful.
441 ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
442 const MachineFunction &MF) const {
443 if (Reg == 0 || !isPhysicalRegister(Reg))
447 else if (Type == (unsigned)ARMRI::RegPairOdd)
449 return getRegisterPairOdd(Reg, MF);
450 else if (Type == (unsigned)ARMRI::RegPairEven)
452 return getRegisterPairEven(Reg, MF);
457 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
458 MachineFunction &MF) const {
459 MachineRegisterInfo *MRI = &MF.getRegInfo();
460 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
461 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
462 Hint.first == (unsigned)ARMRI::RegPairEven) &&
463 TargetRegisterInfo::isVirtualRegister(Hint.second)) {
464 // If 'Reg' is one of the even / odd register pair and it's now changed
465 // (e.g. coalesced) into a different register. The other register of the
466 // pair allocation hint must be updated to reflect the relationship
468 unsigned OtherReg = Hint.second;
469 Hint = MRI->getRegAllocationHint(OtherReg);
470 if (Hint.second == Reg)
471 // Make sure the pair has not already divorced.
472 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
477 ARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
478 // CortexA9 has a Write-after-write hazard for NEON registers.
482 switch (RC->getID()) {
483 case ARM::DPRRegClassID:
484 case ARM::DPR_8RegClassID:
485 case ARM::DPR_VFP2RegClassID:
486 case ARM::QPRRegClassID:
487 case ARM::QPR_8RegClassID:
488 case ARM::QPR_VFP2RegClassID:
489 case ARM::SPRRegClassID:
490 case ARM::SPR_8RegClassID:
491 // Avoid reusing S, D, and Q registers.
492 // Don't increase register pressure for QQ and QQQQ.
499 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
500 const MachineFrameInfo *MFI = MF.getFrameInfo();
501 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
502 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
504 if (!EnableBasePointer)
507 // When outgoing call frames are so large that we adjust the stack pointer
508 // around the call, we can no longer use the stack pointer to reach the
509 // emergency spill slot.
510 if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF))
513 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
514 // negative range for ldr/str (255), and thumb1 is positive offsets only.
515 // It's going to be better to use the SP or Base Pointer instead. When there
516 // are variable sized objects, we can't reference off of the SP, so we
517 // reserve a Base Pointer.
518 if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
519 // Conservatively estimate whether the negative offset from the frame
520 // pointer will be sufficient to reach. If a function has a smallish
521 // frame, it's less likely to have lots of spills and callee saved
522 // space, so it's all more likely to be within range of the frame pointer.
523 // If it's wrong, the scavenger will still enable access to work, it just
525 if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
533 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
534 const MachineRegisterInfo *MRI = &MF.getRegInfo();
535 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
536 // We can't realign the stack if:
537 // 1. Dynamic stack realignment is explicitly disabled,
538 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
539 // 3. There are VLAs in the function and the base pointer is disabled.
540 if (!MF.getTarget().Options.RealignStack)
542 if (AFI->isThumb1OnlyFunction())
544 // Stack realignment requires a frame pointer. If we already started
545 // register allocation with frame pointer elimination, it is too late now.
546 if (!MRI->canReserveReg(FramePtr))
548 // We may also need a base pointer if there are dynamic allocas or stack
549 // pointer adjustments around calls.
550 if (MF.getTarget().getFrameLowering()->hasReservedCallFrame(MF))
552 if (!EnableBasePointer)
554 // A base pointer is required and allowed. Check that it isn't too late to
556 return MRI->canReserveReg(BasePtr);
559 bool ARMBaseRegisterInfo::
560 needsStackRealignment(const MachineFunction &MF) const {
561 const MachineFrameInfo *MFI = MF.getFrameInfo();
562 const Function *F = MF.getFunction();
563 unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
564 bool requiresRealignment =
565 ((MFI->getMaxAlignment() > StackAlign) ||
566 F->getFnAttributes().hasAttribute(Attributes::StackAlignment));
568 return requiresRealignment && canRealignStack(MF);
571 bool ARMBaseRegisterInfo::
572 cannotEliminateFrame(const MachineFunction &MF) const {
573 const MachineFrameInfo *MFI = MF.getFrameInfo();
574 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack())
576 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
577 || needsStackRealignment(MF);
581 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
582 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
589 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
590 llvm_unreachable("What is the exception register");
593 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
594 llvm_unreachable("What is the exception handler register");
597 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
598 const MachineFunction &MF) const {
601 // Return 0 if either register of the pair is a special register.
603 case ARM::R1: return ARM::R0;
604 case ARM::R3: return ARM::R2;
605 case ARM::R5: return ARM::R4;
607 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
609 case ARM::R9: return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8;
610 case ARM::R11: return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
612 case ARM::S1: return ARM::S0;
613 case ARM::S3: return ARM::S2;
614 case ARM::S5: return ARM::S4;
615 case ARM::S7: return ARM::S6;
616 case ARM::S9: return ARM::S8;
617 case ARM::S11: return ARM::S10;
618 case ARM::S13: return ARM::S12;
619 case ARM::S15: return ARM::S14;
620 case ARM::S17: return ARM::S16;
621 case ARM::S19: return ARM::S18;
622 case ARM::S21: return ARM::S20;
623 case ARM::S23: return ARM::S22;
624 case ARM::S25: return ARM::S24;
625 case ARM::S27: return ARM::S26;
626 case ARM::S29: return ARM::S28;
627 case ARM::S31: return ARM::S30;
629 case ARM::D1: return ARM::D0;
630 case ARM::D3: return ARM::D2;
631 case ARM::D5: return ARM::D4;
632 case ARM::D7: return ARM::D6;
633 case ARM::D9: return ARM::D8;
634 case ARM::D11: return ARM::D10;
635 case ARM::D13: return ARM::D12;
636 case ARM::D15: return ARM::D14;
637 case ARM::D17: return ARM::D16;
638 case ARM::D19: return ARM::D18;
639 case ARM::D21: return ARM::D20;
640 case ARM::D23: return ARM::D22;
641 case ARM::D25: return ARM::D24;
642 case ARM::D27: return ARM::D26;
643 case ARM::D29: return ARM::D28;
644 case ARM::D31: return ARM::D30;
650 unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
651 const MachineFunction &MF) const {
654 // Return 0 if either register of the pair is a special register.
656 case ARM::R0: return ARM::R1;
657 case ARM::R2: return ARM::R3;
658 case ARM::R4: return ARM::R5;
660 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
662 case ARM::R8: return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9;
663 case ARM::R10: return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
665 case ARM::S0: return ARM::S1;
666 case ARM::S2: return ARM::S3;
667 case ARM::S4: return ARM::S5;
668 case ARM::S6: return ARM::S7;
669 case ARM::S8: return ARM::S9;
670 case ARM::S10: return ARM::S11;
671 case ARM::S12: return ARM::S13;
672 case ARM::S14: return ARM::S15;
673 case ARM::S16: return ARM::S17;
674 case ARM::S18: return ARM::S19;
675 case ARM::S20: return ARM::S21;
676 case ARM::S22: return ARM::S23;
677 case ARM::S24: return ARM::S25;
678 case ARM::S26: return ARM::S27;
679 case ARM::S28: return ARM::S29;
680 case ARM::S30: return ARM::S31;
682 case ARM::D0: return ARM::D1;
683 case ARM::D2: return ARM::D3;
684 case ARM::D4: return ARM::D5;
685 case ARM::D6: return ARM::D7;
686 case ARM::D8: return ARM::D9;
687 case ARM::D10: return ARM::D11;
688 case ARM::D12: return ARM::D13;
689 case ARM::D14: return ARM::D15;
690 case ARM::D16: return ARM::D17;
691 case ARM::D18: return ARM::D19;
692 case ARM::D20: return ARM::D21;
693 case ARM::D22: return ARM::D23;
694 case ARM::D24: return ARM::D25;
695 case ARM::D26: return ARM::D27;
696 case ARM::D28: return ARM::D29;
697 case ARM::D30: return ARM::D31;
703 /// emitLoadConstPool - Emits a load from constpool to materialize the
704 /// specified immediate.
705 void ARMBaseRegisterInfo::
706 emitLoadConstPool(MachineBasicBlock &MBB,
707 MachineBasicBlock::iterator &MBBI,
709 unsigned DestReg, unsigned SubIdx, int Val,
710 ARMCC::CondCodes Pred,
711 unsigned PredReg, unsigned MIFlags) const {
712 MachineFunction &MF = *MBB.getParent();
713 MachineConstantPool *ConstantPool = MF.getConstantPool();
715 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
716 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
718 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
719 .addReg(DestReg, getDefRegState(true), SubIdx)
720 .addConstantPoolIndex(Idx)
721 .addImm(0).addImm(Pred).addReg(PredReg)
722 .setMIFlags(MIFlags);
725 bool ARMBaseRegisterInfo::
726 requiresRegisterScavenging(const MachineFunction &MF) const {
730 bool ARMBaseRegisterInfo::
731 trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
735 bool ARMBaseRegisterInfo::
736 requiresFrameIndexScavenging(const MachineFunction &MF) const {
740 bool ARMBaseRegisterInfo::
741 requiresVirtualBaseRegisters(const MachineFunction &MF) const {
742 return EnableLocalStackAlloc;
746 emitSPUpdate(bool isARM,
747 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
748 DebugLoc dl, const ARMBaseInstrInfo &TII,
750 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
752 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
755 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
760 void ARMBaseRegisterInfo::
761 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
762 MachineBasicBlock::iterator I) const {
763 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
764 if (!TFI->hasReservedCallFrame(MF)) {
765 // If we have alloca, convert as follows:
766 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
767 // ADJCALLSTACKUP -> add, sp, sp, amount
768 MachineInstr *Old = I;
769 DebugLoc dl = Old->getDebugLoc();
770 unsigned Amount = Old->getOperand(0).getImm();
772 // We need to keep the stack aligned properly. To do this, we round the
773 // amount of space needed for the outgoing arguments up to the next
774 // alignment boundary.
775 unsigned Align = TFI->getStackAlignment();
776 Amount = (Amount+Align-1)/Align*Align;
778 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
779 assert(!AFI->isThumb1OnlyFunction() &&
780 "This eliminateCallFramePseudoInstr does not support Thumb1!");
781 bool isARM = !AFI->isThumbFunction();
783 // Replace the pseudo instruction with a new instruction...
784 unsigned Opc = Old->getOpcode();
785 int PIdx = Old->findFirstPredOperandIdx();
786 ARMCC::CondCodes Pred = (PIdx == -1)
787 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
788 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
789 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
790 unsigned PredReg = Old->getOperand(2).getReg();
791 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
793 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
794 unsigned PredReg = Old->getOperand(3).getReg();
795 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
796 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
803 int64_t ARMBaseRegisterInfo::
804 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
805 const MCInstrDesc &Desc = MI->getDesc();
806 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
807 int64_t InstrOffs = 0;
811 case ARMII::AddrModeT2_i8:
812 case ARMII::AddrModeT2_i12:
813 case ARMII::AddrMode_i12:
814 InstrOffs = MI->getOperand(Idx+1).getImm();
817 case ARMII::AddrMode5: {
819 const MachineOperand &OffOp = MI->getOperand(Idx+1);
820 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
821 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
822 InstrOffs = -InstrOffs;
826 case ARMII::AddrMode2: {
828 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
829 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
830 InstrOffs = -InstrOffs;
833 case ARMII::AddrMode3: {
835 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
836 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
837 InstrOffs = -InstrOffs;
840 case ARMII::AddrModeT1_s: {
842 InstrOffs = MI->getOperand(ImmIdx).getImm();
847 llvm_unreachable("Unsupported addressing mode!");
850 return InstrOffs * Scale;
853 /// needsFrameBaseReg - Returns true if the instruction's frame index
854 /// reference would be better served by a base register other than FP
855 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
856 /// references it should create new base registers for.
857 bool ARMBaseRegisterInfo::
858 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
859 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
860 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
863 // It's the load/store FI references that cause issues, as it can be difficult
864 // to materialize the offset if it won't fit in the literal field. Estimate
865 // based on the size of the local frame and some conservative assumptions
866 // about the rest of the stack frame (note, this is pre-regalloc, so
867 // we don't know everything for certain yet) whether this offset is likely
868 // to be out of range of the immediate. Return true if so.
870 // We only generate virtual base registers for loads and stores, so
871 // return false for everything else.
872 unsigned Opc = MI->getOpcode();
874 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
875 case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
876 case ARM::t2LDRi12: case ARM::t2LDRi8:
877 case ARM::t2STRi12: case ARM::t2STRi8:
878 case ARM::VLDRS: case ARM::VLDRD:
879 case ARM::VSTRS: case ARM::VSTRD:
880 case ARM::tSTRspi: case ARM::tLDRspi:
881 if (ForceAllBaseRegAlloc)
888 // Without a virtual base register, if the function has variable sized
889 // objects, all fixed-size local references will be via the frame pointer,
890 // Approximate the offset and see if it's legal for the instruction.
891 // Note that the incoming offset is based on the SP value at function entry,
892 // so it'll be negative.
893 MachineFunction &MF = *MI->getParent()->getParent();
894 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
895 MachineFrameInfo *MFI = MF.getFrameInfo();
896 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
898 // Estimate an offset from the frame pointer.
899 // Conservatively assume all callee-saved registers get pushed. R4-R6
900 // will be earlier than the FP, so we ignore those.
902 int64_t FPOffset = Offset - 8;
903 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
904 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
906 // Estimate an offset from the stack pointer.
907 // The incoming offset is relating to the SP at the start of the function,
908 // but when we access the local it'll be relative to the SP after local
909 // allocation, so adjust our SP-relative offset by that allocation size.
911 Offset += MFI->getLocalFrameSize();
912 // Assume that we'll have at least some spill slots allocated.
913 // FIXME: This is a total SWAG number. We should run some statistics
914 // and pick a real one.
915 Offset += 128; // 128 bytes of spill slots
917 // If there is a frame pointer, try using it.
918 // The FP is only available if there is no dynamic realignment. We
919 // don't know for sure yet whether we'll need that, so we guess based
920 // on whether there are any local variables that would trigger it.
921 unsigned StackAlign = TFI->getStackAlignment();
922 if (TFI->hasFP(MF) &&
923 !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
924 if (isFrameOffsetLegal(MI, FPOffset))
927 // If we can reference via the stack pointer, try that.
928 // FIXME: This (and the code that resolves the references) can be improved
929 // to only disallow SP relative references in the live range of
930 // the VLA(s). In practice, it's unclear how much difference that
931 // would make, but it may be worth doing.
932 if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
935 // The offset likely isn't legal, we want to allocate a virtual base register.
939 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
940 /// be a pointer to FrameIdx at the beginning of the basic block.
941 void ARMBaseRegisterInfo::
942 materializeFrameBaseRegister(MachineBasicBlock *MBB,
943 unsigned BaseReg, int FrameIdx,
944 int64_t Offset) const {
945 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
946 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
947 (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
949 MachineBasicBlock::iterator Ins = MBB->begin();
950 DebugLoc DL; // Defaults to "unknown"
951 if (Ins != MBB->end())
952 DL = Ins->getDebugLoc();
954 const MCInstrDesc &MCID = TII.get(ADDriOpc);
955 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
956 const MachineFunction &MF = *MBB->getParent();
957 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
959 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg)
960 .addFrameIndex(FrameIdx).addImm(Offset));
962 if (!AFI->isThumb1OnlyFunction())
967 ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
968 unsigned BaseReg, int64_t Offset) const {
969 MachineInstr &MI = *I;
970 MachineBasicBlock &MBB = *MI.getParent();
971 MachineFunction &MF = *MBB.getParent();
972 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
973 int Off = Offset; // ARM doesn't need the general 64-bit offsets
976 assert(!AFI->isThumb1OnlyFunction() &&
977 "This resolveFrameIndex does not support Thumb1!");
979 while (!MI.getOperand(i).isFI()) {
981 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
984 if (!AFI->isThumbFunction())
985 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
987 assert(AFI->isThumb2Function());
988 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
990 assert (Done && "Unable to resolve frame index!");
994 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
995 int64_t Offset) const {
996 const MCInstrDesc &Desc = MI->getDesc();
997 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1000 while (!MI->getOperand(i).isFI()) {
1002 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
1005 // AddrMode4 and AddrMode6 cannot handle any offset.
1006 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
1009 unsigned NumBits = 0;
1011 bool isSigned = true;
1013 case ARMII::AddrModeT2_i8:
1014 case ARMII::AddrModeT2_i12:
1015 // i8 supports only negative, and i12 supports only positive, so
1016 // based on Offset sign, consider the appropriate instruction
1025 case ARMII::AddrMode5:
1026 // VFP address mode.
1030 case ARMII::AddrMode_i12:
1031 case ARMII::AddrMode2:
1034 case ARMII::AddrMode3:
1037 case ARMII::AddrModeT1_s:
1043 llvm_unreachable("Unsupported addressing mode!");
1046 Offset += getFrameIndexInstrOffset(MI, i);
1047 // Make sure the offset is encodable for instructions that scale the
1049 if ((Offset & (Scale-1)) != 0)
1052 if (isSigned && Offset < 0)
1055 unsigned Mask = (1 << NumBits) - 1;
1056 if ((unsigned)Offset <= Mask * Scale)
1063 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1064 int SPAdj, RegScavenger *RS) const {
1066 MachineInstr &MI = *II;
1067 MachineBasicBlock &MBB = *MI.getParent();
1068 MachineFunction &MF = *MBB.getParent();
1069 const ARMFrameLowering *TFI =
1070 static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering());
1071 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1072 assert(!AFI->isThumb1OnlyFunction() &&
1073 "This eliminateFrameIndex does not support Thumb1!");
1075 while (!MI.getOperand(i).isFI()) {
1077 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1080 int FrameIndex = MI.getOperand(i).getIndex();
1083 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
1085 // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
1086 // call frame setup/destroy instructions have already been eliminated. That
1087 // means the stack pointer cannot be used to access the emergency spill slot
1088 // when !hasReservedCallFrame().
1090 if (RS && FrameReg == ARM::SP && FrameIndex == RS->getScavengingFrameIndex()){
1091 assert(TFI->hasReservedCallFrame(MF) &&
1092 "Cannot use SP to access the emergency spill slot in "
1093 "functions without a reserved call frame");
1094 assert(!MF.getFrameInfo()->hasVarSizedObjects() &&
1095 "Cannot use SP to access the emergency spill slot in "
1096 "functions with variable sized frame objects");
1100 // Special handling of dbg_value instructions.
1101 if (MI.isDebugValue()) {
1102 MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/);
1103 MI.getOperand(i+1).ChangeToImmediate(Offset);
1107 // Modify MI as necessary to handle as much of 'Offset' as possible
1109 if (!AFI->isThumbFunction())
1110 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1112 assert(AFI->isThumb2Function());
1113 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1118 // If we get here, the immediate doesn't fit into the instruction. We folded
1119 // as much as possible above, handle the rest, providing a register that is
1122 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1123 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1124 "This code isn't needed if offset already handled!");
1126 unsigned ScratchReg = 0;
1127 int PIdx = MI.findFirstPredOperandIdx();
1128 ARMCC::CondCodes Pred = (PIdx == -1)
1129 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1130 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1132 // Must be addrmode4/6.
1133 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1135 ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass);
1136 if (!AFI->isThumbFunction())
1137 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1138 Offset, Pred, PredReg, TII);
1140 assert(AFI->isThumb2Function());
1141 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1142 Offset, Pred, PredReg, TII);
1144 // Update the original instruction to use the scratch register.
1145 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);