1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMFeatures.h"
19 #include "ARMHazardRecognizer.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "MCTargetDesc/ARMAddressingModes.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineJumpTableInfo.h"
28 #include "llvm/CodeGen/MachineMemOperand.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAGNodes.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/GlobalValue.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCExpr.h"
36 #include "llvm/Support/BranchProbability.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/ErrorHandling.h"
43 #define DEBUG_TYPE "arm-instrinfo"
45 #define GET_INSTRINFO_CTOR_DTOR
46 #include "ARMGenInstrInfo.inc"
49 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
50 cl::desc("Enable ARM 2-addr to 3-addr conv"));
53 WidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true),
54 cl::desc("Widen ARM vmovs to vmovd when possible"));
56 static cl::opt<unsigned>
57 SwiftPartialUpdateClearance("swift-partial-update-clearance",
58 cl::Hidden, cl::init(12),
59 cl::desc("Clearance before partial register updates"));
61 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
63 uint16_t MLxOpc; // MLA / MLS opcode
64 uint16_t MulOpc; // Expanded multiplication opcode
65 uint16_t AddSubOpc; // Expanded add / sub opcode
66 bool NegAcc; // True if the acc is negated before the add / sub.
67 bool HasLane; // True if instruction has an extra "lane" operand.
70 static const ARM_MLxEntry ARM_MLxTable[] = {
71 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
73 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
74 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
75 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
76 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
77 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
78 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
79 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
80 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
83 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
84 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
85 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
86 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
87 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
88 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
89 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
90 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
93 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
94 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
96 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
97 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
98 assert(false && "Duplicated entries?");
99 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
100 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
104 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
105 // currently defaults to no prepass hazard recognizer.
106 ScheduleHazardRecognizer *
107 ARMBaseInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
108 const ScheduleDAG *DAG) const {
109 if (usePreRAHazardRecognizer()) {
110 const InstrItineraryData *II =
111 static_cast<const ARMSubtarget *>(STI)->getInstrItineraryData();
112 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
114 return TargetInstrInfo::CreateTargetHazardRecognizer(STI, DAG);
117 ScheduleHazardRecognizer *ARMBaseInstrInfo::
118 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
119 const ScheduleDAG *DAG) const {
120 if (Subtarget.isThumb2() || Subtarget.hasVFP2())
121 return (ScheduleHazardRecognizer *)new ARMHazardRecognizer(II, DAG);
122 return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG);
126 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
127 MachineBasicBlock::iterator &MBBI,
128 LiveVariables *LV) const {
129 // FIXME: Thumb2 support.
134 MachineInstr *MI = MBBI;
135 MachineFunction &MF = *MI->getParent()->getParent();
136 uint64_t TSFlags = MI->getDesc().TSFlags;
138 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
139 default: return nullptr;
140 case ARMII::IndexModePre:
143 case ARMII::IndexModePost:
147 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
149 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
153 MachineInstr *UpdateMI = nullptr;
154 MachineInstr *MemMI = nullptr;
155 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
156 const MCInstrDesc &MCID = MI->getDesc();
157 unsigned NumOps = MCID.getNumOperands();
158 bool isLoad = !MI->mayStore();
159 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
160 const MachineOperand &Base = MI->getOperand(2);
161 const MachineOperand &Offset = MI->getOperand(NumOps-3);
162 unsigned WBReg = WB.getReg();
163 unsigned BaseReg = Base.getReg();
164 unsigned OffReg = Offset.getReg();
165 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
166 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
168 default: llvm_unreachable("Unknown indexed op!");
169 case ARMII::AddrMode2: {
170 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
171 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
173 if (ARM_AM::getSOImmVal(Amt) == -1)
174 // Can't encode it in a so_imm operand. This transformation will
175 // add more than 1 instruction. Abandon!
177 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
178 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
179 .addReg(BaseReg).addImm(Amt)
180 .addImm(Pred).addReg(0).addReg(0);
181 } else if (Amt != 0) {
182 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
183 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
184 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
185 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
186 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
187 .addImm(Pred).addReg(0).addReg(0);
189 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
190 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
191 .addReg(BaseReg).addReg(OffReg)
192 .addImm(Pred).addReg(0).addReg(0);
195 case ARMII::AddrMode3 : {
196 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
197 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
199 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
200 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
201 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
202 .addReg(BaseReg).addImm(Amt)
203 .addImm(Pred).addReg(0).addReg(0);
205 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
206 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
207 .addReg(BaseReg).addReg(OffReg)
208 .addImm(Pred).addReg(0).addReg(0);
213 std::vector<MachineInstr*> NewMIs;
216 MemMI = BuildMI(MF, MI->getDebugLoc(),
217 get(MemOpc), MI->getOperand(0).getReg())
218 .addReg(WBReg).addImm(0).addImm(Pred);
220 MemMI = BuildMI(MF, MI->getDebugLoc(),
221 get(MemOpc)).addReg(MI->getOperand(1).getReg())
222 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
223 NewMIs.push_back(MemMI);
224 NewMIs.push_back(UpdateMI);
227 MemMI = BuildMI(MF, MI->getDebugLoc(),
228 get(MemOpc), MI->getOperand(0).getReg())
229 .addReg(BaseReg).addImm(0).addImm(Pred);
231 MemMI = BuildMI(MF, MI->getDebugLoc(),
232 get(MemOpc)).addReg(MI->getOperand(1).getReg())
233 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
235 UpdateMI->getOperand(0).setIsDead();
236 NewMIs.push_back(UpdateMI);
237 NewMIs.push_back(MemMI);
240 // Transfer LiveVariables states, kill / dead info.
242 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
243 MachineOperand &MO = MI->getOperand(i);
244 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
245 unsigned Reg = MO.getReg();
247 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
249 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
251 LV->addVirtualRegisterDead(Reg, NewMI);
253 if (MO.isUse() && MO.isKill()) {
254 for (unsigned j = 0; j < 2; ++j) {
255 // Look at the two new MI's in reverse order.
256 MachineInstr *NewMI = NewMIs[j];
257 if (!NewMI->readsRegister(Reg))
259 LV->addVirtualRegisterKilled(Reg, NewMI);
260 if (VI.removeKill(MI))
261 VI.Kills.push_back(NewMI);
269 MFI->insert(MBBI, NewMIs[1]);
270 MFI->insert(MBBI, NewMIs[0]);
276 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
277 MachineBasicBlock *&FBB,
278 SmallVectorImpl<MachineOperand> &Cond,
279 bool AllowModify) const {
283 MachineBasicBlock::iterator I = MBB.end();
284 if (I == MBB.begin())
285 return false; // Empty blocks are easy.
288 // Walk backwards from the end of the basic block until the branch is
289 // analyzed or we give up.
290 while (isPredicated(I) || I->isTerminator() || I->isDebugValue()) {
292 // Flag to be raised on unanalyzeable instructions. This is useful in cases
293 // where we want to clean up on the end of the basic block before we bail
295 bool CantAnalyze = false;
297 // Skip over DEBUG values and predicated nonterminators.
298 while (I->isDebugValue() || !I->isTerminator()) {
299 if (I == MBB.begin())
304 if (isIndirectBranchOpcode(I->getOpcode()) ||
305 isJumpTableBranchOpcode(I->getOpcode())) {
306 // Indirect branches and jump tables can't be analyzed, but we still want
307 // to clean up any instructions at the tail of the basic block.
309 } else if (isUncondBranchOpcode(I->getOpcode())) {
310 TBB = I->getOperand(0).getMBB();
311 } else if (isCondBranchOpcode(I->getOpcode())) {
312 // Bail out if we encounter multiple conditional branches.
316 assert(!FBB && "FBB should have been null.");
318 TBB = I->getOperand(0).getMBB();
319 Cond.push_back(I->getOperand(1));
320 Cond.push_back(I->getOperand(2));
321 } else if (I->isReturn()) {
322 // Returns can't be analyzed, but we should run cleanup.
323 CantAnalyze = !isPredicated(I);
325 // We encountered other unrecognized terminator. Bail out immediately.
329 // Cleanup code - to be run for unpredicated unconditional branches and
331 if (!isPredicated(I) &&
332 (isUncondBranchOpcode(I->getOpcode()) ||
333 isIndirectBranchOpcode(I->getOpcode()) ||
334 isJumpTableBranchOpcode(I->getOpcode()) ||
336 // Forget any previous condition branch information - it no longer applies.
340 // If we can modify the function, delete everything below this
341 // unconditional branch.
343 MachineBasicBlock::iterator DI = std::next(I);
344 while (DI != MBB.end()) {
345 MachineInstr *InstToDelete = DI;
347 InstToDelete->eraseFromParent();
355 if (I == MBB.begin())
361 // We made it past the terminators without bailing out - we must have
362 // analyzed this branch successfully.
367 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
368 MachineBasicBlock::iterator I = MBB.end();
369 if (I == MBB.begin()) return 0;
371 while (I->isDebugValue()) {
372 if (I == MBB.begin())
376 if (!isUncondBranchOpcode(I->getOpcode()) &&
377 !isCondBranchOpcode(I->getOpcode()))
380 // Remove the branch.
381 I->eraseFromParent();
385 if (I == MBB.begin()) return 1;
387 if (!isCondBranchOpcode(I->getOpcode()))
390 // Remove the branch.
391 I->eraseFromParent();
396 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
397 MachineBasicBlock *FBB,
398 const SmallVectorImpl<MachineOperand> &Cond,
400 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
401 int BOpc = !AFI->isThumbFunction()
402 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
403 int BccOpc = !AFI->isThumbFunction()
404 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
405 bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function();
407 // Shouldn't be a fall through.
408 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
409 assert((Cond.size() == 2 || Cond.size() == 0) &&
410 "ARM branch conditions have two components!");
413 if (Cond.empty()) { // Unconditional branch?
415 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
417 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
419 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
420 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
424 // Two-way conditional branch.
425 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
426 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
428 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0);
430 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
434 bool ARMBaseInstrInfo::
435 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
436 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
437 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
441 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
442 if (MI->isBundle()) {
443 MachineBasicBlock::const_instr_iterator I = MI;
444 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
445 while (++I != E && I->isInsideBundle()) {
446 int PIdx = I->findFirstPredOperandIdx();
447 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
453 int PIdx = MI->findFirstPredOperandIdx();
454 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
457 bool ARMBaseInstrInfo::
458 PredicateInstruction(MachineInstr *MI,
459 const SmallVectorImpl<MachineOperand> &Pred) const {
460 unsigned Opc = MI->getOpcode();
461 if (isUncondBranchOpcode(Opc)) {
462 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
463 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
464 .addImm(Pred[0].getImm())
465 .addReg(Pred[1].getReg());
469 int PIdx = MI->findFirstPredOperandIdx();
471 MachineOperand &PMO = MI->getOperand(PIdx);
472 PMO.setImm(Pred[0].getImm());
473 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
479 bool ARMBaseInstrInfo::
480 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
481 const SmallVectorImpl<MachineOperand> &Pred2) const {
482 if (Pred1.size() > 2 || Pred2.size() > 2)
485 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
486 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
496 return CC2 == ARMCC::HI;
498 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
500 return CC2 == ARMCC::GT;
502 return CC2 == ARMCC::LT;
506 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
507 std::vector<MachineOperand> &Pred) const {
509 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
510 const MachineOperand &MO = MI->getOperand(i);
511 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
512 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
521 static bool isCPSRDefined(const MachineInstr *MI) {
522 for (const auto &MO : MI->operands())
523 if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef())
528 static bool isEligibleForITBlock(const MachineInstr *MI) {
529 switch (MI->getOpcode()) {
530 default: return true;
531 case ARM::tADC: // ADC (register) T1
532 case ARM::tADDi3: // ADD (immediate) T1
533 case ARM::tADDi8: // ADD (immediate) T2
534 case ARM::tADDrr: // ADD (register) T1
535 case ARM::tAND: // AND (register) T1
536 case ARM::tASRri: // ASR (immediate) T1
537 case ARM::tASRrr: // ASR (register) T1
538 case ARM::tBIC: // BIC (register) T1
539 case ARM::tEOR: // EOR (register) T1
540 case ARM::tLSLri: // LSL (immediate) T1
541 case ARM::tLSLrr: // LSL (register) T1
542 case ARM::tLSRri: // LSR (immediate) T1
543 case ARM::tLSRrr: // LSR (register) T1
544 case ARM::tMUL: // MUL T1
545 case ARM::tMVN: // MVN (register) T1
546 case ARM::tORR: // ORR (register) T1
547 case ARM::tROR: // ROR (register) T1
548 case ARM::tRSB: // RSB (immediate) T1
549 case ARM::tSBC: // SBC (register) T1
550 case ARM::tSUBi3: // SUB (immediate) T1
551 case ARM::tSUBi8: // SUB (immediate) T2
552 case ARM::tSUBrr: // SUB (register) T1
553 return !isCPSRDefined(MI);
557 /// isPredicable - Return true if the specified instruction can be predicated.
558 /// By default, this returns true for every instruction with a
559 /// PredicateOperand.
560 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
561 if (!MI->isPredicable())
564 if (!isEligibleForITBlock(MI))
567 ARMFunctionInfo *AFI =
568 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
570 if (AFI->isThumb2Function()) {
571 if (getSubtarget().restrictIT())
572 return isV8EligibleForIT(MI);
573 } else { // non-Thumb
574 if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON)
582 template <> bool IsCPSRDead<MachineInstr>(MachineInstr *MI) {
583 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
584 const MachineOperand &MO = MI->getOperand(i);
585 if (!MO.isReg() || MO.isUndef() || MO.isUse())
587 if (MO.getReg() != ARM::CPSR)
592 // all definitions of CPSR are dead
597 /// GetInstSize - Return the size of the specified MachineInstr.
599 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
600 const MachineBasicBlock &MBB = *MI->getParent();
601 const MachineFunction *MF = MBB.getParent();
602 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
604 const MCInstrDesc &MCID = MI->getDesc();
606 return MCID.getSize();
608 // If this machine instr is an inline asm, measure it.
609 if (MI->getOpcode() == ARM::INLINEASM)
610 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
611 unsigned Opc = MI->getOpcode();
614 // pseudo-instruction sizes are zero.
616 case TargetOpcode::BUNDLE:
617 return getInstBundleLength(MI);
618 case ARM::MOVi16_ga_pcrel:
619 case ARM::MOVTi16_ga_pcrel:
620 case ARM::t2MOVi16_ga_pcrel:
621 case ARM::t2MOVTi16_ga_pcrel:
624 case ARM::t2MOVi32imm:
626 case ARM::CONSTPOOL_ENTRY:
627 // If this machine instr is a constant pool entry, its size is recorded as
629 return MI->getOperand(2).getImm();
630 case ARM::Int_eh_sjlj_longjmp:
632 case ARM::tInt_eh_sjlj_longjmp:
634 case ARM::Int_eh_sjlj_setjmp:
635 case ARM::Int_eh_sjlj_setjmp_nofp:
637 case ARM::tInt_eh_sjlj_setjmp:
638 case ARM::t2Int_eh_sjlj_setjmp:
639 case ARM::t2Int_eh_sjlj_setjmp_nofp:
647 case ARM::t2TBH_JT: {
648 // These are jumptable branches, i.e. a branch followed by an inlined
649 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
650 // entry is one byte; TBH two byte each.
651 unsigned EntrySize = (Opc == ARM::t2TBB_JT)
652 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
653 unsigned NumOps = MCID.getNumOperands();
654 MachineOperand JTOP =
655 MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2));
656 unsigned JTI = JTOP.getIndex();
657 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
658 assert(MJTI != nullptr);
659 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
660 assert(JTI < JT.size());
661 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
662 // 4 aligned. The assembler / linker may add 2 byte padding just before
663 // the JT entries. The size does not include this padding; the
664 // constant islands pass does separate bookkeeping for it.
665 // FIXME: If we know the size of the function is less than (1 << 16) *2
666 // bytes, we can use 16-bit entries instead. Then there won't be an
668 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
669 unsigned NumEntries = JT[JTI].MBBs.size();
670 if (Opc == ARM::t2TBB_JT && (NumEntries & 1))
671 // Make sure the instruction that follows TBB is 2-byte aligned.
672 // FIXME: Constant island pass should insert an "ALIGN" instruction
675 return NumEntries * EntrySize + InstSize;
680 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const {
682 MachineBasicBlock::const_instr_iterator I = MI;
683 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
684 while (++I != E && I->isInsideBundle()) {
685 assert(!I->isBundle() && "No nested bundle!");
686 Size += GetInstSizeInBytes(&*I);
691 void ARMBaseInstrInfo::copyFromCPSR(MachineBasicBlock &MBB,
692 MachineBasicBlock::iterator I,
693 unsigned DestReg, bool KillSrc,
694 const ARMSubtarget &Subtarget) const {
695 unsigned Opc = Subtarget.isThumb()
696 ? (Subtarget.isMClass() ? ARM::t2MRS_M : ARM::t2MRS_AR)
699 MachineInstrBuilder MIB =
700 BuildMI(MBB, I, I->getDebugLoc(), get(Opc), DestReg);
702 // There is only 1 A/R class MRS instruction, and it always refers to
703 // APSR. However, there are lots of other possibilities on M-class cores.
704 if (Subtarget.isMClass())
709 MIB.addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc));
712 void ARMBaseInstrInfo::copyToCPSR(MachineBasicBlock &MBB,
713 MachineBasicBlock::iterator I,
714 unsigned SrcReg, bool KillSrc,
715 const ARMSubtarget &Subtarget) const {
716 unsigned Opc = Subtarget.isThumb()
717 ? (Subtarget.isMClass() ? ARM::t2MSR_M : ARM::t2MSR_AR)
720 MachineInstrBuilder MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
722 if (Subtarget.isMClass())
727 MIB.addReg(SrcReg, getKillRegState(KillSrc));
731 MIB.addReg(ARM::CPSR, RegState::Implicit | RegState::Define);
734 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
735 MachineBasicBlock::iterator I, DebugLoc DL,
736 unsigned DestReg, unsigned SrcReg,
737 bool KillSrc) const {
738 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
739 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
741 if (GPRDest && GPRSrc) {
742 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
743 .addReg(SrcReg, getKillRegState(KillSrc))));
747 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
748 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
751 if (SPRDest && SPRSrc)
753 else if (GPRDest && SPRSrc)
755 else if (SPRDest && GPRSrc)
757 else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && !Subtarget.isFPOnlySP())
759 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
763 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
764 MIB.addReg(SrcReg, getKillRegState(KillSrc));
765 if (Opc == ARM::VORRq)
766 MIB.addReg(SrcReg, getKillRegState(KillSrc));
771 // Handle register classes that require multiple instructions.
772 unsigned BeginIdx = 0;
773 unsigned SubRegs = 0;
776 // Use VORRq when possible.
777 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) {
779 BeginIdx = ARM::qsub_0;
781 } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) {
783 BeginIdx = ARM::qsub_0;
785 // Fall back to VMOVD.
786 } else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) {
788 BeginIdx = ARM::dsub_0;
790 } else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) {
792 BeginIdx = ARM::dsub_0;
794 } else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) {
796 BeginIdx = ARM::dsub_0;
798 } else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) {
799 Opc = Subtarget.isThumb2() ? ARM::tMOVr : ARM::MOVr;
800 BeginIdx = ARM::gsub_0;
802 } else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) {
804 BeginIdx = ARM::dsub_0;
807 } else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) {
809 BeginIdx = ARM::dsub_0;
812 } else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) {
814 BeginIdx = ARM::dsub_0;
817 } else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && Subtarget.isFPOnlySP()) {
819 BeginIdx = ARM::ssub_0;
821 } else if (SrcReg == ARM::CPSR) {
822 copyFromCPSR(MBB, I, DestReg, KillSrc, Subtarget);
824 } else if (DestReg == ARM::CPSR) {
825 copyToCPSR(MBB, I, SrcReg, KillSrc, Subtarget);
829 assert(Opc && "Impossible reg-to-reg copy");
831 const TargetRegisterInfo *TRI = &getRegisterInfo();
832 MachineInstrBuilder Mov;
834 // Copy register tuples backward when the first Dest reg overlaps with SrcReg.
835 if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) {
836 BeginIdx = BeginIdx + ((SubRegs - 1) * Spacing);
840 SmallSet<unsigned, 4> DstRegs;
842 for (unsigned i = 0; i != SubRegs; ++i) {
843 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing);
844 unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i * Spacing);
845 assert(Dst && Src && "Bad sub-register");
847 assert(!DstRegs.count(Src) && "destructive vector copy");
850 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src);
851 // VORR takes two source operands.
852 if (Opc == ARM::VORRq)
854 Mov = AddDefaultPred(Mov);
856 if (Opc == ARM::MOVr)
857 Mov = AddDefaultCC(Mov);
859 // Add implicit super-register defs and kills to the last instruction.
860 Mov->addRegisterDefined(DestReg, TRI);
862 Mov->addRegisterKilled(SrcReg, TRI);
865 const MachineInstrBuilder &
866 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
867 unsigned SubIdx, unsigned State,
868 const TargetRegisterInfo *TRI) const {
870 return MIB.addReg(Reg, State);
872 if (TargetRegisterInfo::isPhysicalRegister(Reg))
873 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
874 return MIB.addReg(Reg, State, SubIdx);
877 void ARMBaseInstrInfo::
878 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
879 unsigned SrcReg, bool isKill, int FI,
880 const TargetRegisterClass *RC,
881 const TargetRegisterInfo *TRI) const {
883 if (I != MBB.end()) DL = I->getDebugLoc();
884 MachineFunction &MF = *MBB.getParent();
885 MachineFrameInfo &MFI = *MF.getFrameInfo();
886 unsigned Align = MFI.getObjectAlignment(FI);
888 MachineMemOperand *MMO =
889 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
890 MachineMemOperand::MOStore,
891 MFI.getObjectSize(FI),
894 switch (RC->getSize()) {
896 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
897 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
898 .addReg(SrcReg, getKillRegState(isKill))
899 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
900 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
901 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
902 .addReg(SrcReg, getKillRegState(isKill))
903 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
905 llvm_unreachable("Unknown reg class!");
908 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
909 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
910 .addReg(SrcReg, getKillRegState(isKill))
911 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
912 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
913 if (Subtarget.hasV5TEOps()) {
914 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD));
915 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
916 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
917 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO);
921 // Fallback to STM instruction, which has existed since the dawn of
923 MachineInstrBuilder MIB =
924 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STMIA))
925 .addFrameIndex(FI).addMemOperand(MMO));
926 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
927 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
930 llvm_unreachable("Unknown reg class!");
933 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
934 // Use aligned spills if the stack can be realigned.
935 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
936 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64))
937 .addFrameIndex(FI).addImm(16)
938 .addReg(SrcReg, getKillRegState(isKill))
939 .addMemOperand(MMO));
941 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
942 .addReg(SrcReg, getKillRegState(isKill))
944 .addMemOperand(MMO));
947 llvm_unreachable("Unknown reg class!");
950 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
951 // Use aligned spills if the stack can be realigned.
952 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
953 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo))
954 .addFrameIndex(FI).addImm(16)
955 .addReg(SrcReg, getKillRegState(isKill))
956 .addMemOperand(MMO));
958 MachineInstrBuilder MIB =
959 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
962 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
963 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
964 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
967 llvm_unreachable("Unknown reg class!");
970 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
971 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
972 // FIXME: It's possible to only store part of the QQ register if the
973 // spilled def has a sub-register index.
974 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
975 .addFrameIndex(FI).addImm(16)
976 .addReg(SrcReg, getKillRegState(isKill))
977 .addMemOperand(MMO));
979 MachineInstrBuilder MIB =
980 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
983 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
984 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
985 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
986 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
989 llvm_unreachable("Unknown reg class!");
992 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
993 MachineInstrBuilder MIB =
994 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
997 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
998 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
999 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
1000 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
1001 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
1002 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
1003 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
1004 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
1006 llvm_unreachable("Unknown reg class!");
1009 llvm_unreachable("Unknown reg class!");
1014 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
1015 int &FrameIndex) const {
1016 switch (MI->getOpcode()) {
1019 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
1020 if (MI->getOperand(1).isFI() &&
1021 MI->getOperand(2).isReg() &&
1022 MI->getOperand(3).isImm() &&
1023 MI->getOperand(2).getReg() == 0 &&
1024 MI->getOperand(3).getImm() == 0) {
1025 FrameIndex = MI->getOperand(1).getIndex();
1026 return MI->getOperand(0).getReg();
1034 if (MI->getOperand(1).isFI() &&
1035 MI->getOperand(2).isImm() &&
1036 MI->getOperand(2).getImm() == 0) {
1037 FrameIndex = MI->getOperand(1).getIndex();
1038 return MI->getOperand(0).getReg();
1042 case ARM::VST1d64TPseudo:
1043 case ARM::VST1d64QPseudo:
1044 if (MI->getOperand(0).isFI() &&
1045 MI->getOperand(2).getSubReg() == 0) {
1046 FrameIndex = MI->getOperand(0).getIndex();
1047 return MI->getOperand(2).getReg();
1051 if (MI->getOperand(1).isFI() &&
1052 MI->getOperand(0).getSubReg() == 0) {
1053 FrameIndex = MI->getOperand(1).getIndex();
1054 return MI->getOperand(0).getReg();
1062 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1063 int &FrameIndex) const {
1064 const MachineMemOperand *Dummy;
1065 return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex);
1068 void ARMBaseInstrInfo::
1069 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
1070 unsigned DestReg, int FI,
1071 const TargetRegisterClass *RC,
1072 const TargetRegisterInfo *TRI) const {
1074 if (I != MBB.end()) DL = I->getDebugLoc();
1075 MachineFunction &MF = *MBB.getParent();
1076 MachineFrameInfo &MFI = *MF.getFrameInfo();
1077 unsigned Align = MFI.getObjectAlignment(FI);
1078 MachineMemOperand *MMO =
1079 MF.getMachineMemOperand(
1080 MachinePointerInfo::getFixedStack(FI),
1081 MachineMemOperand::MOLoad,
1082 MFI.getObjectSize(FI),
1085 switch (RC->getSize()) {
1087 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
1088 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
1089 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1091 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
1092 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
1093 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1095 llvm_unreachable("Unknown reg class!");
1098 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
1099 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
1100 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1101 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
1102 MachineInstrBuilder MIB;
1104 if (Subtarget.hasV5TEOps()) {
1105 MIB = BuildMI(MBB, I, DL, get(ARM::LDRD));
1106 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1107 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1108 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO);
1110 AddDefaultPred(MIB);
1112 // Fallback to LDM instruction, which has existed since the dawn of
1114 MIB = AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDMIA))
1115 .addFrameIndex(FI).addMemOperand(MMO));
1116 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1117 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1120 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1121 MIB.addReg(DestReg, RegState::ImplicitDefine);
1123 llvm_unreachable("Unknown reg class!");
1126 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
1127 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1128 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
1129 .addFrameIndex(FI).addImm(16)
1130 .addMemOperand(MMO));
1132 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
1134 .addMemOperand(MMO));
1137 llvm_unreachable("Unknown reg class!");
1140 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
1141 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1142 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg)
1143 .addFrameIndex(FI).addImm(16)
1144 .addMemOperand(MMO));
1146 MachineInstrBuilder MIB =
1147 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1149 .addMemOperand(MMO));
1150 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1151 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1152 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1153 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1154 MIB.addReg(DestReg, RegState::ImplicitDefine);
1157 llvm_unreachable("Unknown reg class!");
1160 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
1161 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1162 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
1163 .addFrameIndex(FI).addImm(16)
1164 .addMemOperand(MMO));
1166 MachineInstrBuilder MIB =
1167 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1169 .addMemOperand(MMO);
1170 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1171 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1172 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1173 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1174 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1175 MIB.addReg(DestReg, RegState::ImplicitDefine);
1178 llvm_unreachable("Unknown reg class!");
1181 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
1182 MachineInstrBuilder MIB =
1183 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1185 .addMemOperand(MMO);
1186 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1187 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1188 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1189 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1190 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
1191 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
1192 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
1193 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
1194 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1195 MIB.addReg(DestReg, RegState::ImplicitDefine);
1197 llvm_unreachable("Unknown reg class!");
1200 llvm_unreachable("Unknown regclass!");
1205 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1206 int &FrameIndex) const {
1207 switch (MI->getOpcode()) {
1210 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
1211 if (MI->getOperand(1).isFI() &&
1212 MI->getOperand(2).isReg() &&
1213 MI->getOperand(3).isImm() &&
1214 MI->getOperand(2).getReg() == 0 &&
1215 MI->getOperand(3).getImm() == 0) {
1216 FrameIndex = MI->getOperand(1).getIndex();
1217 return MI->getOperand(0).getReg();
1225 if (MI->getOperand(1).isFI() &&
1226 MI->getOperand(2).isImm() &&
1227 MI->getOperand(2).getImm() == 0) {
1228 FrameIndex = MI->getOperand(1).getIndex();
1229 return MI->getOperand(0).getReg();
1233 case ARM::VLD1d64TPseudo:
1234 case ARM::VLD1d64QPseudo:
1235 if (MI->getOperand(1).isFI() &&
1236 MI->getOperand(0).getSubReg() == 0) {
1237 FrameIndex = MI->getOperand(1).getIndex();
1238 return MI->getOperand(0).getReg();
1242 if (MI->getOperand(1).isFI() &&
1243 MI->getOperand(0).getSubReg() == 0) {
1244 FrameIndex = MI->getOperand(1).getIndex();
1245 return MI->getOperand(0).getReg();
1253 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1254 int &FrameIndex) const {
1255 const MachineMemOperand *Dummy;
1256 return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1260 ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
1261 MachineFunction &MF = *MI->getParent()->getParent();
1262 Reloc::Model RM = MF.getTarget().getRelocationModel();
1264 if (MI->getOpcode() == TargetOpcode::LOAD_STACK_GUARD) {
1265 assert(getSubtarget().getTargetTriple().getObjectFormat() ==
1267 "LOAD_STACK_GUARD currently supported only for MachO.");
1268 expandLoadStackGuard(MI, RM);
1269 MI->getParent()->erase(MI);
1273 // This hook gets to expand COPY instructions before they become
1274 // copyPhysReg() calls. Look for VMOVS instructions that can legally be
1275 // widened to VMOVD. We prefer the VMOVD when possible because it may be
1276 // changed into a VORR that can go down the NEON pipeline.
1277 if (!WidenVMOVS || !MI->isCopy() || Subtarget.isCortexA15() ||
1278 Subtarget.isFPOnlySP())
1281 // Look for a copy between even S-registers. That is where we keep floats
1282 // when using NEON v2f32 instructions for f32 arithmetic.
1283 unsigned DstRegS = MI->getOperand(0).getReg();
1284 unsigned SrcRegS = MI->getOperand(1).getReg();
1285 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS))
1288 const TargetRegisterInfo *TRI = &getRegisterInfo();
1289 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
1291 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
1293 if (!DstRegD || !SrcRegD)
1296 // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only
1297 // legal if the COPY already defines the full DstRegD, and it isn't a
1298 // sub-register insertion.
1299 if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI))
1302 // A dead copy shouldn't show up here, but reject it just in case.
1303 if (MI->getOperand(0).isDead())
1306 // All clear, widen the COPY.
1307 DEBUG(dbgs() << "widening: " << *MI);
1308 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
1310 // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg
1311 // or some other super-register.
1312 int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD);
1313 if (ImpDefIdx != -1)
1314 MI->RemoveOperand(ImpDefIdx);
1316 // Change the opcode and operands.
1317 MI->setDesc(get(ARM::VMOVD));
1318 MI->getOperand(0).setReg(DstRegD);
1319 MI->getOperand(1).setReg(SrcRegD);
1320 AddDefaultPred(MIB);
1322 // We are now reading SrcRegD instead of SrcRegS. This may upset the
1323 // register scavenger and machine verifier, so we need to indicate that we
1324 // are reading an undefined value from SrcRegD, but a proper value from
1326 MI->getOperand(1).setIsUndef();
1327 MIB.addReg(SrcRegS, RegState::Implicit);
1329 // SrcRegD may actually contain an unrelated value in the ssub_1
1330 // sub-register. Don't kill it. Only kill the ssub_0 sub-register.
1331 if (MI->getOperand(1).isKill()) {
1332 MI->getOperand(1).setIsKill(false);
1333 MI->addRegisterKilled(SrcRegS, TRI, true);
1336 DEBUG(dbgs() << "replaced by: " << *MI);
1340 /// Create a copy of a const pool value. Update CPI to the new index and return
1342 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1343 MachineConstantPool *MCP = MF.getConstantPool();
1344 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1346 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1347 assert(MCPE.isMachineConstantPoolEntry() &&
1348 "Expecting a machine constantpool entry!");
1349 ARMConstantPoolValue *ACPV =
1350 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1352 unsigned PCLabelId = AFI->createPICLabelUId();
1353 ARMConstantPoolValue *NewCPV = nullptr;
1355 // FIXME: The below assumes PIC relocation model and that the function
1356 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
1357 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
1358 // instructions, so that's probably OK, but is PIC always correct when
1360 if (ACPV->isGlobalValue())
1361 NewCPV = ARMConstantPoolConstant::
1362 Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId,
1364 else if (ACPV->isExtSymbol())
1365 NewCPV = ARMConstantPoolSymbol::
1366 Create(MF.getFunction()->getContext(),
1367 cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4);
1368 else if (ACPV->isBlockAddress())
1369 NewCPV = ARMConstantPoolConstant::
1370 Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId,
1371 ARMCP::CPBlockAddress, 4);
1372 else if (ACPV->isLSDA())
1373 NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId,
1375 else if (ACPV->isMachineBasicBlock())
1376 NewCPV = ARMConstantPoolMBB::
1377 Create(MF.getFunction()->getContext(),
1378 cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4);
1380 llvm_unreachable("Unexpected ARM constantpool value type!!");
1381 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1385 void ARMBaseInstrInfo::
1386 reMaterialize(MachineBasicBlock &MBB,
1387 MachineBasicBlock::iterator I,
1388 unsigned DestReg, unsigned SubIdx,
1389 const MachineInstr *Orig,
1390 const TargetRegisterInfo &TRI) const {
1391 unsigned Opcode = Orig->getOpcode();
1394 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1395 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1399 case ARM::tLDRpci_pic:
1400 case ARM::t2LDRpci_pic: {
1401 MachineFunction &MF = *MBB.getParent();
1402 unsigned CPI = Orig->getOperand(1).getIndex();
1403 unsigned PCLabelId = duplicateCPV(MF, CPI);
1404 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1406 .addConstantPoolIndex(CPI).addImm(PCLabelId);
1407 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1414 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1415 MachineInstr *MI = TargetInstrInfo::duplicate(Orig, MF);
1416 switch(Orig->getOpcode()) {
1417 case ARM::tLDRpci_pic:
1418 case ARM::t2LDRpci_pic: {
1419 unsigned CPI = Orig->getOperand(1).getIndex();
1420 unsigned PCLabelId = duplicateCPV(MF, CPI);
1421 Orig->getOperand(1).setIndex(CPI);
1422 Orig->getOperand(2).setImm(PCLabelId);
1429 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1430 const MachineInstr *MI1,
1431 const MachineRegisterInfo *MRI) const {
1432 int Opcode = MI0->getOpcode();
1433 if (Opcode == ARM::t2LDRpci ||
1434 Opcode == ARM::t2LDRpci_pic ||
1435 Opcode == ARM::tLDRpci ||
1436 Opcode == ARM::tLDRpci_pic ||
1437 Opcode == ARM::LDRLIT_ga_pcrel ||
1438 Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
1439 Opcode == ARM::tLDRLIT_ga_pcrel ||
1440 Opcode == ARM::MOV_ga_pcrel ||
1441 Opcode == ARM::MOV_ga_pcrel_ldr ||
1442 Opcode == ARM::t2MOV_ga_pcrel) {
1443 if (MI1->getOpcode() != Opcode)
1445 if (MI0->getNumOperands() != MI1->getNumOperands())
1448 const MachineOperand &MO0 = MI0->getOperand(1);
1449 const MachineOperand &MO1 = MI1->getOperand(1);
1450 if (MO0.getOffset() != MO1.getOffset())
1453 if (Opcode == ARM::LDRLIT_ga_pcrel ||
1454 Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
1455 Opcode == ARM::tLDRLIT_ga_pcrel ||
1456 Opcode == ARM::MOV_ga_pcrel ||
1457 Opcode == ARM::MOV_ga_pcrel_ldr ||
1458 Opcode == ARM::t2MOV_ga_pcrel)
1459 // Ignore the PC labels.
1460 return MO0.getGlobal() == MO1.getGlobal();
1462 const MachineFunction *MF = MI0->getParent()->getParent();
1463 const MachineConstantPool *MCP = MF->getConstantPool();
1464 int CPI0 = MO0.getIndex();
1465 int CPI1 = MO1.getIndex();
1466 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1467 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1468 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1469 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1470 if (isARMCP0 && isARMCP1) {
1471 ARMConstantPoolValue *ACPV0 =
1472 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1473 ARMConstantPoolValue *ACPV1 =
1474 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1475 return ACPV0->hasSameValue(ACPV1);
1476 } else if (!isARMCP0 && !isARMCP1) {
1477 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1480 } else if (Opcode == ARM::PICLDR) {
1481 if (MI1->getOpcode() != Opcode)
1483 if (MI0->getNumOperands() != MI1->getNumOperands())
1486 unsigned Addr0 = MI0->getOperand(1).getReg();
1487 unsigned Addr1 = MI1->getOperand(1).getReg();
1488 if (Addr0 != Addr1) {
1490 !TargetRegisterInfo::isVirtualRegister(Addr0) ||
1491 !TargetRegisterInfo::isVirtualRegister(Addr1))
1494 // This assumes SSA form.
1495 MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1496 MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1497 // Check if the loaded value, e.g. a constantpool of a global address, are
1499 if (!produceSameValue(Def0, Def1, MRI))
1503 for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) {
1504 // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg
1505 const MachineOperand &MO0 = MI0->getOperand(i);
1506 const MachineOperand &MO1 = MI1->getOperand(i);
1507 if (!MO0.isIdenticalTo(MO1))
1513 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1516 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1517 /// determine if two loads are loading from the same base address. It should
1518 /// only return true if the base pointers are the same and the only differences
1519 /// between the two addresses is the offset. It also returns the offsets by
1522 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1523 /// is permanently disabled.
1524 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1526 int64_t &Offset2) const {
1527 // Don't worry about Thumb: just ARM and Thumb2.
1528 if (Subtarget.isThumb1Only()) return false;
1530 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1533 switch (Load1->getMachineOpcode()) {
1547 case ARM::t2LDRSHi8:
1549 case ARM::t2LDRBi12:
1550 case ARM::t2LDRSHi12:
1554 switch (Load2->getMachineOpcode()) {
1567 case ARM::t2LDRSHi8:
1569 case ARM::t2LDRBi12:
1570 case ARM::t2LDRSHi12:
1574 // Check if base addresses and chain operands match.
1575 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1576 Load1->getOperand(4) != Load2->getOperand(4))
1579 // Index should be Reg0.
1580 if (Load1->getOperand(3) != Load2->getOperand(3))
1583 // Determine the offsets.
1584 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1585 isa<ConstantSDNode>(Load2->getOperand(1))) {
1586 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1587 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1594 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1595 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
1596 /// be scheduled togther. On some targets if two loads are loading from
1597 /// addresses in the same cache line, it's better if they are scheduled
1598 /// together. This function takes two integers that represent the load offsets
1599 /// from the common base address. It returns true if it decides it's desirable
1600 /// to schedule the two loads together. "NumLoads" is the number of loads that
1601 /// have already been scheduled after Load1.
1603 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1604 /// is permanently disabled.
1605 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1606 int64_t Offset1, int64_t Offset2,
1607 unsigned NumLoads) const {
1608 // Don't worry about Thumb: just ARM and Thumb2.
1609 if (Subtarget.isThumb1Only()) return false;
1611 assert(Offset2 > Offset1);
1613 if ((Offset2 - Offset1) / 8 > 64)
1616 // Check if the machine opcodes are different. If they are different
1617 // then we consider them to not be of the same base address,
1618 // EXCEPT in the case of Thumb2 byte loads where one is LDRBi8 and the other LDRBi12.
1619 // In this case, they are considered to be the same because they are different
1620 // encoding forms of the same basic instruction.
1621 if ((Load1->getMachineOpcode() != Load2->getMachineOpcode()) &&
1622 !((Load1->getMachineOpcode() == ARM::t2LDRBi8 &&
1623 Load2->getMachineOpcode() == ARM::t2LDRBi12) ||
1624 (Load1->getMachineOpcode() == ARM::t2LDRBi12 &&
1625 Load2->getMachineOpcode() == ARM::t2LDRBi8)))
1626 return false; // FIXME: overly conservative?
1628 // Four loads in a row should be sufficient.
1635 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1636 const MachineBasicBlock *MBB,
1637 const MachineFunction &MF) const {
1638 // Debug info is never a scheduling boundary. It's necessary to be explicit
1639 // due to the special treatment of IT instructions below, otherwise a
1640 // dbg_value followed by an IT will result in the IT instruction being
1641 // considered a scheduling hazard, which is wrong. It should be the actual
1642 // instruction preceding the dbg_value instruction(s), just like it is
1643 // when debug info is not present.
1644 if (MI->isDebugValue())
1647 // Terminators and labels can't be scheduled around.
1648 if (MI->isTerminator() || MI->isPosition())
1651 // Treat the start of the IT block as a scheduling boundary, but schedule
1652 // t2IT along with all instructions following it.
1653 // FIXME: This is a big hammer. But the alternative is to add all potential
1654 // true and anti dependencies to IT block instructions as implicit operands
1655 // to the t2IT instruction. The added compile time and complexity does not
1657 MachineBasicBlock::const_iterator I = MI;
1658 // Make sure to skip any dbg_value instructions
1659 while (++I != MBB->end() && I->isDebugValue())
1661 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1664 // Don't attempt to schedule around any instruction that defines
1665 // a stack-oriented pointer, as it's unlikely to be profitable. This
1666 // saves compile time, because it doesn't require every single
1667 // stack slot reference to depend on the instruction that does the
1669 // Calls don't actually change the stack pointer, even if they have imp-defs.
1670 // No ARM calling conventions change the stack pointer. (X86 calling
1671 // conventions sometimes do).
1672 if (!MI->isCall() && MI->definesRegister(ARM::SP))
1678 bool ARMBaseInstrInfo::
1679 isProfitableToIfCvt(MachineBasicBlock &MBB,
1680 unsigned NumCycles, unsigned ExtraPredCycles,
1681 const BranchProbability &Probability) const {
1685 // Attempt to estimate the relative costs of predication versus branching.
1686 unsigned UnpredCost = Probability.getNumerator() * NumCycles;
1687 UnpredCost /= Probability.getDenominator();
1688 UnpredCost += 1; // The branch itself
1689 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1691 return (NumCycles + ExtraPredCycles) <= UnpredCost;
1694 bool ARMBaseInstrInfo::
1695 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1696 unsigned TCycles, unsigned TExtra,
1697 MachineBasicBlock &FMBB,
1698 unsigned FCycles, unsigned FExtra,
1699 const BranchProbability &Probability) const {
1700 if (!TCycles || !FCycles)
1703 // Attempt to estimate the relative costs of predication versus branching.
1704 unsigned TUnpredCost = Probability.getNumerator() * TCycles;
1705 TUnpredCost /= Probability.getDenominator();
1707 uint32_t Comp = Probability.getDenominator() - Probability.getNumerator();
1708 unsigned FUnpredCost = Comp * FCycles;
1709 FUnpredCost /= Probability.getDenominator();
1711 unsigned UnpredCost = TUnpredCost + FUnpredCost;
1712 UnpredCost += 1; // The branch itself
1713 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1715 return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost;
1719 ARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
1720 MachineBasicBlock &FMBB) const {
1721 // Reduce false anti-dependencies to let Swift's out-of-order execution
1722 // engine do its thing.
1723 return Subtarget.isSwift();
1726 /// getInstrPredicate - If instruction is predicated, returns its predicate
1727 /// condition, otherwise returns AL. It also returns the condition code
1728 /// register by reference.
1730 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1731 int PIdx = MI->findFirstPredOperandIdx();
1737 PredReg = MI->getOperand(PIdx+1).getReg();
1738 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1742 int llvm::getMatchingCondBranchOpcode(int Opc) {
1747 if (Opc == ARM::t2B)
1750 llvm_unreachable("Unknown unconditional branch opcode!");
1753 /// commuteInstruction - Handle commutable instructions.
1755 ARMBaseInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1756 switch (MI->getOpcode()) {
1758 case ARM::t2MOVCCr: {
1759 // MOVCC can be commuted by inverting the condition.
1760 unsigned PredReg = 0;
1761 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg);
1762 // MOVCC AL can't be inverted. Shouldn't happen.
1763 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
1765 MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
1768 // After swapping the MOVCC operands, also invert the condition.
1769 MI->getOperand(MI->findFirstPredOperandIdx())
1770 .setImm(ARMCC::getOppositeCondition(CC));
1774 return TargetInstrInfo::commuteInstruction(MI, NewMI);
1777 /// Identify instructions that can be folded into a MOVCC instruction, and
1778 /// return the defining instruction.
1779 static MachineInstr *canFoldIntoMOVCC(unsigned Reg,
1780 const MachineRegisterInfo &MRI,
1781 const TargetInstrInfo *TII) {
1782 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1784 if (!MRI.hasOneNonDBGUse(Reg))
1786 MachineInstr *MI = MRI.getVRegDef(Reg);
1789 // MI is folded into the MOVCC by predicating it.
1790 if (!MI->isPredicable())
1792 // Check if MI has any non-dead defs or physreg uses. This also detects
1793 // predicated instructions which will be reading CPSR.
1794 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
1795 const MachineOperand &MO = MI->getOperand(i);
1796 // Reject frame index operands, PEI can't handle the predicated pseudos.
1797 if (MO.isFI() || MO.isCPI() || MO.isJTI())
1801 // MI can't have any tied operands, that would conflict with predication.
1804 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
1806 if (MO.isDef() && !MO.isDead())
1809 bool DontMoveAcrossStores = true;
1810 if (!MI->isSafeToMove(TII, /* AliasAnalysis = */ nullptr,
1811 DontMoveAcrossStores))
1816 bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr *MI,
1817 SmallVectorImpl<MachineOperand> &Cond,
1818 unsigned &TrueOp, unsigned &FalseOp,
1819 bool &Optimizable) const {
1820 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1821 "Unknown select instruction");
1826 // 3: Condition code.
1830 Cond.push_back(MI->getOperand(3));
1831 Cond.push_back(MI->getOperand(4));
1832 // We can always fold a def.
1837 MachineInstr *ARMBaseInstrInfo::optimizeSelect(MachineInstr *MI,
1838 bool PreferFalse) const {
1839 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1840 "Unknown select instruction");
1841 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1842 MachineInstr *DefMI = canFoldIntoMOVCC(MI->getOperand(2).getReg(), MRI, this);
1843 bool Invert = !DefMI;
1845 DefMI = canFoldIntoMOVCC(MI->getOperand(1).getReg(), MRI, this);
1849 // Find new register class to use.
1850 MachineOperand FalseReg = MI->getOperand(Invert ? 2 : 1);
1851 unsigned DestReg = MI->getOperand(0).getReg();
1852 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg());
1853 if (!MRI.constrainRegClass(DestReg, PreviousClass))
1856 // Create a new predicated version of DefMI.
1857 // Rfalse is the first use.
1858 MachineInstrBuilder NewMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1859 DefMI->getDesc(), DestReg);
1861 // Copy all the DefMI operands, excluding its (null) predicate.
1862 const MCInstrDesc &DefDesc = DefMI->getDesc();
1863 for (unsigned i = 1, e = DefDesc.getNumOperands();
1864 i != e && !DefDesc.OpInfo[i].isPredicate(); ++i)
1865 NewMI.addOperand(DefMI->getOperand(i));
1867 unsigned CondCode = MI->getOperand(3).getImm();
1869 NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode)));
1871 NewMI.addImm(CondCode);
1872 NewMI.addOperand(MI->getOperand(4));
1874 // DefMI is not the -S version that sets CPSR, so add an optional %noreg.
1875 if (NewMI->hasOptionalDef())
1876 AddDefaultCC(NewMI);
1878 // The output register value when the predicate is false is an implicit
1879 // register operand tied to the first def.
1880 // The tie makes the register allocator ensure the FalseReg is allocated the
1881 // same register as operand 0.
1882 FalseReg.setImplicit();
1883 NewMI.addOperand(FalseReg);
1884 NewMI->tieOperands(0, NewMI->getNumOperands() - 1);
1886 // The caller will erase MI, but not DefMI.
1887 DefMI->eraseFromParent();
1891 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the
1892 /// instruction is encoded with an 'S' bit is determined by the optional CPSR
1895 /// This will go away once we can teach tblgen how to set the optional CPSR def
1897 struct AddSubFlagsOpcodePair {
1899 uint16_t MachineOpc;
1902 static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
1903 {ARM::ADDSri, ARM::ADDri},
1904 {ARM::ADDSrr, ARM::ADDrr},
1905 {ARM::ADDSrsi, ARM::ADDrsi},
1906 {ARM::ADDSrsr, ARM::ADDrsr},
1908 {ARM::SUBSri, ARM::SUBri},
1909 {ARM::SUBSrr, ARM::SUBrr},
1910 {ARM::SUBSrsi, ARM::SUBrsi},
1911 {ARM::SUBSrsr, ARM::SUBrsr},
1913 {ARM::RSBSri, ARM::RSBri},
1914 {ARM::RSBSrsi, ARM::RSBrsi},
1915 {ARM::RSBSrsr, ARM::RSBrsr},
1917 {ARM::t2ADDSri, ARM::t2ADDri},
1918 {ARM::t2ADDSrr, ARM::t2ADDrr},
1919 {ARM::t2ADDSrs, ARM::t2ADDrs},
1921 {ARM::t2SUBSri, ARM::t2SUBri},
1922 {ARM::t2SUBSrr, ARM::t2SUBrr},
1923 {ARM::t2SUBSrs, ARM::t2SUBrs},
1925 {ARM::t2RSBSri, ARM::t2RSBri},
1926 {ARM::t2RSBSrs, ARM::t2RSBrs},
1929 unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) {
1930 for (unsigned i = 0, e = array_lengthof(AddSubFlagsOpcodeMap); i != e; ++i)
1931 if (OldOpc == AddSubFlagsOpcodeMap[i].PseudoOpc)
1932 return AddSubFlagsOpcodeMap[i].MachineOpc;
1936 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1937 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1938 unsigned DestReg, unsigned BaseReg, int NumBytes,
1939 ARMCC::CondCodes Pred, unsigned PredReg,
1940 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
1941 if (NumBytes == 0 && DestReg != BaseReg) {
1942 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg)
1943 .addReg(BaseReg, RegState::Kill)
1944 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1945 .setMIFlags(MIFlags);
1949 bool isSub = NumBytes < 0;
1950 if (isSub) NumBytes = -NumBytes;
1953 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1954 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1955 assert(ThisVal && "Didn't extract field correctly");
1957 // We will handle these bits from offset, clear them.
1958 NumBytes &= ~ThisVal;
1960 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1962 // Build the new ADD / SUB.
1963 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1964 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1965 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1966 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1967 .setMIFlags(MIFlags);
1972 static bool isAnySubRegLive(unsigned Reg, const TargetRegisterInfo *TRI,
1974 for (MCSubRegIterator Subreg(Reg, TRI, /* IncludeSelf */ true);
1975 Subreg.isValid(); ++Subreg)
1976 if (MI->getParent()->computeRegisterLiveness(TRI, *Subreg, MI) !=
1977 MachineBasicBlock::LQR_Dead)
1981 bool llvm::tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
1982 MachineFunction &MF, MachineInstr *MI,
1983 unsigned NumBytes) {
1984 // This optimisation potentially adds lots of load and store
1985 // micro-operations, it's only really a great benefit to code-size.
1986 if (!MF.getFunction()->getAttributes().hasAttribute(
1987 AttributeSet::FunctionIndex, Attribute::MinSize))
1990 // If only one register is pushed/popped, LLVM can use an LDR/STR
1991 // instead. We can't modify those so make sure we're dealing with an
1992 // instruction we understand.
1993 bool IsPop = isPopOpcode(MI->getOpcode());
1994 bool IsPush = isPushOpcode(MI->getOpcode());
1995 if (!IsPush && !IsPop)
1998 bool IsVFPPushPop = MI->getOpcode() == ARM::VSTMDDB_UPD ||
1999 MI->getOpcode() == ARM::VLDMDIA_UPD;
2000 bool IsT1PushPop = MI->getOpcode() == ARM::tPUSH ||
2001 MI->getOpcode() == ARM::tPOP ||
2002 MI->getOpcode() == ARM::tPOP_RET;
2004 assert((IsT1PushPop || (MI->getOperand(0).getReg() == ARM::SP &&
2005 MI->getOperand(1).getReg() == ARM::SP)) &&
2006 "trying to fold sp update into non-sp-updating push/pop");
2008 // The VFP push & pop act on D-registers, so we can only fold an adjustment
2009 // by a multiple of 8 bytes in correctly. Similarly rN is 4-bytes. Don't try
2010 // if this is violated.
2011 if (NumBytes % (IsVFPPushPop ? 8 : 4) != 0)
2014 // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+
2015 // pred) so the list starts at 4. Thumb1 starts after the predicate.
2016 int RegListIdx = IsT1PushPop ? 2 : 4;
2018 // Calculate the space we'll need in terms of registers.
2019 unsigned FirstReg = MI->getOperand(RegListIdx).getReg();
2020 unsigned RD0Reg, RegsNeeded;
2023 RegsNeeded = NumBytes / 8;
2026 RegsNeeded = NumBytes / 4;
2029 // We're going to have to strip all list operands off before
2030 // re-adding them since the order matters, so save the existing ones
2032 SmallVector<MachineOperand, 4> RegList;
2033 for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i)
2034 RegList.push_back(MI->getOperand(i));
2036 const TargetRegisterInfo *TRI = MF.getRegInfo().getTargetRegisterInfo();
2037 const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
2039 // Now try to find enough space in the reglist to allocate NumBytes.
2040 for (unsigned CurReg = FirstReg - 1; CurReg >= RD0Reg && RegsNeeded;
2043 // Pushing any register is completely harmless, mark the
2044 // register involved as undef since we don't care about it in
2046 RegList.push_back(MachineOperand::CreateReg(CurReg, false, false,
2047 false, false, true));
2052 // However, we can only pop an extra register if it's not live. For
2053 // registers live within the function we might clobber a return value
2054 // register; the other way a register can be live here is if it's
2056 // TODO: Currently, computeRegisterLiveness() does not report "live" if a
2057 // sub reg is live. When computeRegisterLiveness() works for sub reg, it
2058 // can replace isAnySubRegLive().
2059 if (isCalleeSavedRegister(CurReg, CSRegs) ||
2060 isAnySubRegLive(CurReg, TRI, MI)) {
2061 // VFP pops don't allow holes in the register list, so any skip is fatal
2062 // for our transformation. GPR pops do, so we should just keep looking.
2069 // Mark the unimportant registers as <def,dead> in the POP.
2070 RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, false,
2078 // Finally we know we can profitably perform the optimisation so go
2079 // ahead: strip all existing registers off and add them back again
2080 // in the right order.
2081 for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i)
2082 MI->RemoveOperand(i);
2084 // Add the complete list back in.
2085 MachineInstrBuilder MIB(MF, &*MI);
2086 for (int i = RegList.size() - 1; i >= 0; --i)
2087 MIB.addOperand(RegList[i]);
2092 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
2093 unsigned FrameReg, int &Offset,
2094 const ARMBaseInstrInfo &TII) {
2095 unsigned Opcode = MI.getOpcode();
2096 const MCInstrDesc &Desc = MI.getDesc();
2097 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
2100 // Memory operands in inline assembly always use AddrMode2.
2101 if (Opcode == ARM::INLINEASM)
2102 AddrMode = ARMII::AddrMode2;
2104 if (Opcode == ARM::ADDri) {
2105 Offset += MI.getOperand(FrameRegIdx+1).getImm();
2107 // Turn it into a move.
2108 MI.setDesc(TII.get(ARM::MOVr));
2109 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2110 MI.RemoveOperand(FrameRegIdx+1);
2113 } else if (Offset < 0) {
2116 MI.setDesc(TII.get(ARM::SUBri));
2119 // Common case: small offset, fits into instruction.
2120 if (ARM_AM::getSOImmVal(Offset) != -1) {
2121 // Replace the FrameIndex with sp / fp
2122 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2123 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
2128 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
2130 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
2131 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
2133 // We will handle these bits from offset, clear them.
2134 Offset &= ~ThisImmVal;
2136 // Get the properly encoded SOImmVal field.
2137 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
2138 "Bit extraction didn't work?");
2139 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
2141 unsigned ImmIdx = 0;
2143 unsigned NumBits = 0;
2146 case ARMII::AddrMode_i12: {
2147 ImmIdx = FrameRegIdx + 1;
2148 InstrOffs = MI.getOperand(ImmIdx).getImm();
2152 case ARMII::AddrMode2: {
2153 ImmIdx = FrameRegIdx+2;
2154 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
2155 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2160 case ARMII::AddrMode3: {
2161 ImmIdx = FrameRegIdx+2;
2162 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
2163 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2168 case ARMII::AddrMode4:
2169 case ARMII::AddrMode6:
2170 // Can't fold any offset even if it's zero.
2172 case ARMII::AddrMode5: {
2173 ImmIdx = FrameRegIdx+1;
2174 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
2175 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2182 llvm_unreachable("Unsupported addressing mode!");
2185 Offset += InstrOffs * Scale;
2186 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
2192 // Attempt to fold address comp. if opcode has offset bits
2194 // Common case: small offset, fits into instruction.
2195 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
2196 int ImmedOffset = Offset / Scale;
2197 unsigned Mask = (1 << NumBits) - 1;
2198 if ((unsigned)Offset <= Mask * Scale) {
2199 // Replace the FrameIndex with sp
2200 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2201 // FIXME: When addrmode2 goes away, this will simplify (like the
2202 // T2 version), as the LDR.i12 versions don't need the encoding
2203 // tricks for the offset value.
2205 if (AddrMode == ARMII::AddrMode_i12)
2206 ImmedOffset = -ImmedOffset;
2208 ImmedOffset |= 1 << NumBits;
2210 ImmOp.ChangeToImmediate(ImmedOffset);
2215 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
2216 ImmedOffset = ImmedOffset & Mask;
2218 if (AddrMode == ARMII::AddrMode_i12)
2219 ImmedOffset = -ImmedOffset;
2221 ImmedOffset |= 1 << NumBits;
2223 ImmOp.ChangeToImmediate(ImmedOffset);
2224 Offset &= ~(Mask*Scale);
2228 Offset = (isSub) ? -Offset : Offset;
2232 /// analyzeCompare - For a comparison instruction, return the source registers
2233 /// in SrcReg and SrcReg2 if having two register operands, and the value it
2234 /// compares against in CmpValue. Return true if the comparison instruction
2235 /// can be analyzed.
2236 bool ARMBaseInstrInfo::
2237 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
2238 int &CmpMask, int &CmpValue) const {
2239 switch (MI->getOpcode()) {
2243 SrcReg = MI->getOperand(0).getReg();
2246 CmpValue = MI->getOperand(1).getImm();
2250 SrcReg = MI->getOperand(0).getReg();
2251 SrcReg2 = MI->getOperand(1).getReg();
2257 SrcReg = MI->getOperand(0).getReg();
2259 CmpMask = MI->getOperand(1).getImm();
2267 /// isSuitableForMask - Identify a suitable 'and' instruction that
2268 /// operates on the given source register and applies the same mask
2269 /// as a 'tst' instruction. Provide a limited look-through for copies.
2270 /// When successful, MI will hold the found instruction.
2271 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
2272 int CmpMask, bool CommonUse) {
2273 switch (MI->getOpcode()) {
2276 if (CmpMask != MI->getOperand(2).getImm())
2278 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
2282 // Walk down one instruction which is potentially an 'and'.
2283 const MachineInstr &Copy = *MI;
2284 MachineBasicBlock::iterator AND(
2285 std::next(MachineBasicBlock::iterator(MI)));
2286 if (AND == MI->getParent()->end()) return false;
2288 return isSuitableForMask(MI, Copy.getOperand(0).getReg(),
2296 /// getSwappedCondition - assume the flags are set by MI(a,b), return
2297 /// the condition code if we modify the instructions such that flags are
2299 inline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) {
2301 default: return ARMCC::AL;
2302 case ARMCC::EQ: return ARMCC::EQ;
2303 case ARMCC::NE: return ARMCC::NE;
2304 case ARMCC::HS: return ARMCC::LS;
2305 case ARMCC::LO: return ARMCC::HI;
2306 case ARMCC::HI: return ARMCC::LO;
2307 case ARMCC::LS: return ARMCC::HS;
2308 case ARMCC::GE: return ARMCC::LE;
2309 case ARMCC::LT: return ARMCC::GT;
2310 case ARMCC::GT: return ARMCC::LT;
2311 case ARMCC::LE: return ARMCC::GE;
2315 /// isRedundantFlagInstr - check whether the first instruction, whose only
2316 /// purpose is to update flags, can be made redundant.
2317 /// CMPrr can be made redundant by SUBrr if the operands are the same.
2318 /// CMPri can be made redundant by SUBri if the operands are the same.
2319 /// This function can be extended later on.
2320 inline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg,
2321 unsigned SrcReg2, int ImmValue,
2323 if ((CmpI->getOpcode() == ARM::CMPrr ||
2324 CmpI->getOpcode() == ARM::t2CMPrr) &&
2325 (OI->getOpcode() == ARM::SUBrr ||
2326 OI->getOpcode() == ARM::t2SUBrr) &&
2327 ((OI->getOperand(1).getReg() == SrcReg &&
2328 OI->getOperand(2).getReg() == SrcReg2) ||
2329 (OI->getOperand(1).getReg() == SrcReg2 &&
2330 OI->getOperand(2).getReg() == SrcReg)))
2333 if ((CmpI->getOpcode() == ARM::CMPri ||
2334 CmpI->getOpcode() == ARM::t2CMPri) &&
2335 (OI->getOpcode() == ARM::SUBri ||
2336 OI->getOpcode() == ARM::t2SUBri) &&
2337 OI->getOperand(1).getReg() == SrcReg &&
2338 OI->getOperand(2).getImm() == ImmValue)
2343 /// optimizeCompareInstr - Convert the instruction supplying the argument to the
2344 /// comparison into one that sets the zero bit in the flags register;
2345 /// Remove a redundant Compare instruction if an earlier instruction can set the
2346 /// flags in the same way as Compare.
2347 /// E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two
2348 /// operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the
2349 /// condition code of instructions which use the flags.
2350 bool ARMBaseInstrInfo::
2351 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
2352 int CmpMask, int CmpValue,
2353 const MachineRegisterInfo *MRI) const {
2354 // Get the unique definition of SrcReg.
2355 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
2356 if (!MI) return false;
2358 // Masked compares sometimes use the same register as the corresponding 'and'.
2359 if (CmpMask != ~0) {
2360 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(MI)) {
2362 for (MachineRegisterInfo::use_instr_iterator
2363 UI = MRI->use_instr_begin(SrcReg), UE = MRI->use_instr_end();
2365 if (UI->getParent() != CmpInstr->getParent()) continue;
2366 MachineInstr *PotentialAND = &*UI;
2367 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true) ||
2368 isPredicated(PotentialAND))
2373 if (!MI) return false;
2377 // Get ready to iterate backward from CmpInstr.
2378 MachineBasicBlock::iterator I = CmpInstr, E = MI,
2379 B = CmpInstr->getParent()->begin();
2381 // Early exit if CmpInstr is at the beginning of the BB.
2382 if (I == B) return false;
2384 // There are two possible candidates which can be changed to set CPSR:
2385 // One is MI, the other is a SUB instruction.
2386 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
2387 // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue).
2388 MachineInstr *Sub = nullptr;
2390 // MI is not a candidate for CMPrr.
2392 else if (MI->getParent() != CmpInstr->getParent() || CmpValue != 0) {
2393 // Conservatively refuse to convert an instruction which isn't in the same
2394 // BB as the comparison.
2395 // For CMPri, we need to check Sub, thus we can't return here.
2396 if (CmpInstr->getOpcode() == ARM::CMPri ||
2397 CmpInstr->getOpcode() == ARM::t2CMPri)
2403 // Check that CPSR isn't set between the comparison instruction and the one we
2404 // want to change. At the same time, search for Sub.
2405 const TargetRegisterInfo *TRI = &getRegisterInfo();
2407 for (; I != E; --I) {
2408 const MachineInstr &Instr = *I;
2410 if (Instr.modifiesRegister(ARM::CPSR, TRI) ||
2411 Instr.readsRegister(ARM::CPSR, TRI))
2412 // This instruction modifies or uses CPSR after the one we want to
2413 // change. We can't do this transformation.
2416 // Check whether CmpInstr can be made redundant by the current instruction.
2417 if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) {
2423 // The 'and' is below the comparison instruction.
2427 // Return false if no candidates exist.
2431 // The single candidate is called MI.
2434 // We can't use a predicated instruction - it doesn't always write the flags.
2435 if (isPredicated(MI))
2438 switch (MI->getOpcode()) {
2472 case ARM::t2EORri: {
2473 // Scan forward for the use of CPSR
2474 // When checking against MI: if it's a conditional code requires
2475 // checking of V bit, then this is not safe to do.
2476 // It is safe to remove CmpInstr if CPSR is redefined or killed.
2477 // If we are done with the basic block, we need to check whether CPSR is
2479 SmallVector<std::pair<MachineOperand*, ARMCC::CondCodes>, 4>
2481 bool isSafe = false;
2483 E = CmpInstr->getParent()->end();
2484 while (!isSafe && ++I != E) {
2485 const MachineInstr &Instr = *I;
2486 for (unsigned IO = 0, EO = Instr.getNumOperands();
2487 !isSafe && IO != EO; ++IO) {
2488 const MachineOperand &MO = Instr.getOperand(IO);
2489 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) {
2493 if (!MO.isReg() || MO.getReg() != ARM::CPSR)
2499 // Condition code is after the operand before CPSR except for VSELs.
2500 ARMCC::CondCodes CC;
2501 bool IsInstrVSel = true;
2502 switch (Instr.getOpcode()) {
2504 IsInstrVSel = false;
2505 CC = (ARMCC::CondCodes)Instr.getOperand(IO - 1).getImm();
2526 ARMCC::CondCodes NewCC = getSwappedCondition(CC);
2527 if (NewCC == ARMCC::AL)
2529 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based
2530 // on CMP needs to be updated to be based on SUB.
2531 // Push the condition code operands to OperandsToUpdate.
2532 // If it is safe to remove CmpInstr, the condition code of these
2533 // operands will be modified.
2534 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
2535 Sub->getOperand(2).getReg() == SrcReg) {
2536 // VSel doesn't support condition code update.
2539 OperandsToUpdate.push_back(
2540 std::make_pair(&((*I).getOperand(IO - 1)), NewCC));
2545 // CPSR can be used multiple times, we should continue.
2558 // If CPSR is not killed nor re-defined, we should check whether it is
2559 // live-out. If it is live-out, do not optimize.
2561 MachineBasicBlock *MBB = CmpInstr->getParent();
2562 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
2563 SE = MBB->succ_end(); SI != SE; ++SI)
2564 if ((*SI)->isLiveIn(ARM::CPSR))
2568 // Toggle the optional operand to CPSR.
2569 MI->getOperand(5).setReg(ARM::CPSR);
2570 MI->getOperand(5).setIsDef(true);
2571 assert(!isPredicated(MI) && "Can't use flags from predicated instruction");
2572 CmpInstr->eraseFromParent();
2574 // Modify the condition code of operands in OperandsToUpdate.
2575 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
2576 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
2577 for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++)
2578 OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second);
2586 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
2587 MachineInstr *DefMI, unsigned Reg,
2588 MachineRegisterInfo *MRI) const {
2589 // Fold large immediates into add, sub, or, xor.
2590 unsigned DefOpc = DefMI->getOpcode();
2591 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
2593 if (!DefMI->getOperand(1).isImm())
2594 // Could be t2MOVi32imm <ga:xx>
2597 if (!MRI->hasOneNonDBGUse(Reg))
2600 const MCInstrDesc &DefMCID = DefMI->getDesc();
2601 if (DefMCID.hasOptionalDef()) {
2602 unsigned NumOps = DefMCID.getNumOperands();
2603 const MachineOperand &MO = DefMI->getOperand(NumOps-1);
2604 if (MO.getReg() == ARM::CPSR && !MO.isDead())
2605 // If DefMI defines CPSR and it is not dead, it's obviously not safe
2610 const MCInstrDesc &UseMCID = UseMI->getDesc();
2611 if (UseMCID.hasOptionalDef()) {
2612 unsigned NumOps = UseMCID.getNumOperands();
2613 if (UseMI->getOperand(NumOps-1).getReg() == ARM::CPSR)
2614 // If the instruction sets the flag, do not attempt this optimization
2615 // since it may change the semantics of the code.
2619 unsigned UseOpc = UseMI->getOpcode();
2620 unsigned NewUseOpc = 0;
2621 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm();
2622 uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
2623 bool Commute = false;
2625 default: return false;
2633 case ARM::t2EORrr: {
2634 Commute = UseMI->getOperand(2).getReg() != Reg;
2641 NewUseOpc = ARM::SUBri;
2647 if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
2649 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
2650 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
2653 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break;
2654 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
2655 case ARM::EORrr: NewUseOpc = ARM::EORri; break;
2659 case ARM::t2SUBrr: {
2663 NewUseOpc = ARM::t2SUBri;
2668 case ARM::t2EORrr: {
2669 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
2671 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
2672 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
2675 case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break;
2676 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
2677 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
2685 unsigned OpIdx = Commute ? 2 : 1;
2686 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg();
2687 bool isKill = UseMI->getOperand(OpIdx).isKill();
2688 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
2689 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(),
2690 UseMI, UseMI->getDebugLoc(),
2691 get(NewUseOpc), NewReg)
2692 .addReg(Reg1, getKillRegState(isKill))
2693 .addImm(SOImmValV1)));
2694 UseMI->setDesc(get(NewUseOpc));
2695 UseMI->getOperand(1).setReg(NewReg);
2696 UseMI->getOperand(1).setIsKill();
2697 UseMI->getOperand(2).ChangeToImmediate(SOImmValV2);
2698 DefMI->eraseFromParent();
2702 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData,
2703 const MachineInstr *MI) {
2704 switch (MI->getOpcode()) {
2706 const MCInstrDesc &Desc = MI->getDesc();
2707 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass());
2708 assert(UOps >= 0 && "bad # UOps");
2716 unsigned ShOpVal = MI->getOperand(3).getImm();
2717 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2718 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2721 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2722 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2729 if (!MI->getOperand(2).getReg())
2732 unsigned ShOpVal = MI->getOperand(3).getImm();
2733 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2734 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2737 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2738 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2745 return (ARM_AM::getAM3Op(MI->getOperand(3).getImm()) == ARM_AM::sub) ? 3:2;
2747 case ARM::LDRSB_POST:
2748 case ARM::LDRSH_POST: {
2749 unsigned Rt = MI->getOperand(0).getReg();
2750 unsigned Rm = MI->getOperand(3).getReg();
2751 return (Rt == Rm) ? 4 : 3;
2754 case ARM::LDR_PRE_REG:
2755 case ARM::LDRB_PRE_REG: {
2756 unsigned Rt = MI->getOperand(0).getReg();
2757 unsigned Rm = MI->getOperand(3).getReg();
2760 unsigned ShOpVal = MI->getOperand(4).getImm();
2761 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2762 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2765 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2766 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2771 case ARM::STR_PRE_REG:
2772 case ARM::STRB_PRE_REG: {
2773 unsigned ShOpVal = MI->getOperand(4).getImm();
2774 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2775 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2778 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2779 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2785 case ARM::STRH_PRE: {
2786 unsigned Rt = MI->getOperand(0).getReg();
2787 unsigned Rm = MI->getOperand(3).getReg();
2792 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub)
2796 case ARM::LDR_POST_REG:
2797 case ARM::LDRB_POST_REG:
2798 case ARM::LDRH_POST: {
2799 unsigned Rt = MI->getOperand(0).getReg();
2800 unsigned Rm = MI->getOperand(3).getReg();
2801 return (Rt == Rm) ? 3 : 2;
2804 case ARM::LDR_PRE_IMM:
2805 case ARM::LDRB_PRE_IMM:
2806 case ARM::LDR_POST_IMM:
2807 case ARM::LDRB_POST_IMM:
2808 case ARM::STRB_POST_IMM:
2809 case ARM::STRB_POST_REG:
2810 case ARM::STRB_PRE_IMM:
2811 case ARM::STRH_POST:
2812 case ARM::STR_POST_IMM:
2813 case ARM::STR_POST_REG:
2814 case ARM::STR_PRE_IMM:
2817 case ARM::LDRSB_PRE:
2818 case ARM::LDRSH_PRE: {
2819 unsigned Rm = MI->getOperand(3).getReg();
2822 unsigned Rt = MI->getOperand(0).getReg();
2825 unsigned ShOpVal = MI->getOperand(4).getImm();
2826 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2827 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2830 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2831 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2837 unsigned Rt = MI->getOperand(0).getReg();
2838 unsigned Rn = MI->getOperand(2).getReg();
2839 unsigned Rm = MI->getOperand(3).getReg();
2841 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3;
2842 return (Rt == Rn) ? 3 : 2;
2846 unsigned Rm = MI->getOperand(3).getReg();
2848 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3;
2852 case ARM::LDRD_POST:
2853 case ARM::t2LDRD_POST:
2856 case ARM::STRD_POST:
2857 case ARM::t2STRD_POST:
2860 case ARM::LDRD_PRE: {
2861 unsigned Rt = MI->getOperand(0).getReg();
2862 unsigned Rn = MI->getOperand(3).getReg();
2863 unsigned Rm = MI->getOperand(4).getReg();
2865 return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4;
2866 return (Rt == Rn) ? 4 : 3;
2869 case ARM::t2LDRD_PRE: {
2870 unsigned Rt = MI->getOperand(0).getReg();
2871 unsigned Rn = MI->getOperand(3).getReg();
2872 return (Rt == Rn) ? 4 : 3;
2875 case ARM::STRD_PRE: {
2876 unsigned Rm = MI->getOperand(4).getReg();
2878 return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4;
2882 case ARM::t2STRD_PRE:
2885 case ARM::t2LDR_POST:
2886 case ARM::t2LDRB_POST:
2887 case ARM::t2LDRB_PRE:
2888 case ARM::t2LDRSBi12:
2889 case ARM::t2LDRSBi8:
2890 case ARM::t2LDRSBpci:
2892 case ARM::t2LDRH_POST:
2893 case ARM::t2LDRH_PRE:
2895 case ARM::t2LDRSB_POST:
2896 case ARM::t2LDRSB_PRE:
2897 case ARM::t2LDRSH_POST:
2898 case ARM::t2LDRSH_PRE:
2899 case ARM::t2LDRSHi12:
2900 case ARM::t2LDRSHi8:
2901 case ARM::t2LDRSHpci:
2905 case ARM::t2LDRDi8: {
2906 unsigned Rt = MI->getOperand(0).getReg();
2907 unsigned Rn = MI->getOperand(2).getReg();
2908 return (Rt == Rn) ? 3 : 2;
2911 case ARM::t2STRB_POST:
2912 case ARM::t2STRB_PRE:
2915 case ARM::t2STRH_POST:
2916 case ARM::t2STRH_PRE:
2918 case ARM::t2STR_POST:
2919 case ARM::t2STR_PRE:
2925 // Return the number of 32-bit words loaded by LDM or stored by STM. If this
2926 // can't be easily determined return 0 (missing MachineMemOperand).
2928 // FIXME: The current MachineInstr design does not support relying on machine
2929 // mem operands to determine the width of a memory access. Instead, we expect
2930 // the target to provide this information based on the instruction opcode and
2931 // operands. However, using MachineMemOperand is the best solution now for
2934 // 1) getNumMicroOps tries to infer LDM memory width from the total number of MI
2935 // operands. This is much more dangerous than using the MachineMemOperand
2936 // sizes because CodeGen passes can insert/remove optional machine operands. In
2937 // fact, it's totally incorrect for preRA passes and appears to be wrong for
2938 // postRA passes as well.
2940 // 2) getNumLDMAddresses is only used by the scheduling machine model and any
2941 // machine model that calls this should handle the unknown (zero size) case.
2943 // Long term, we should require a target hook that verifies MachineMemOperand
2944 // sizes during MC lowering. That target hook should be local to MC lowering
2945 // because we can't ensure that it is aware of other MI forms. Doing this will
2946 // ensure that MachineMemOperands are correctly propagated through all passes.
2947 unsigned ARMBaseInstrInfo::getNumLDMAddresses(const MachineInstr *MI) const {
2949 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
2950 E = MI->memoperands_end(); I != E; ++I) {
2951 Size += (*I)->getSize();
2957 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
2958 const MachineInstr *MI) const {
2959 if (!ItinData || ItinData->isEmpty())
2962 const MCInstrDesc &Desc = MI->getDesc();
2963 unsigned Class = Desc.getSchedClass();
2964 int ItinUOps = ItinData->getNumMicroOps(Class);
2965 if (ItinUOps >= 0) {
2966 if (Subtarget.isSwift() && (Desc.mayLoad() || Desc.mayStore()))
2967 return getNumMicroOpsSwiftLdSt(ItinData, MI);
2972 unsigned Opc = MI->getOpcode();
2975 llvm_unreachable("Unexpected multi-uops instruction!");
2980 // The number of uOps for load / store multiple are determined by the number
2983 // On Cortex-A8, each pair of register loads / stores can be scheduled on the
2984 // same cycle. The scheduling for the first load / store must be done
2985 // separately by assuming the address is not 64-bit aligned.
2987 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
2988 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
2989 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
2991 case ARM::VLDMDIA_UPD:
2992 case ARM::VLDMDDB_UPD:
2994 case ARM::VLDMSIA_UPD:
2995 case ARM::VLDMSDB_UPD:
2997 case ARM::VSTMDIA_UPD:
2998 case ARM::VSTMDDB_UPD:
3000 case ARM::VSTMSIA_UPD:
3001 case ARM::VSTMSDB_UPD: {
3002 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
3003 return (NumRegs / 2) + (NumRegs % 2) + 1;
3006 case ARM::LDMIA_RET:
3011 case ARM::LDMIA_UPD:
3012 case ARM::LDMDA_UPD:
3013 case ARM::LDMDB_UPD:
3014 case ARM::LDMIB_UPD:
3019 case ARM::STMIA_UPD:
3020 case ARM::STMDA_UPD:
3021 case ARM::STMDB_UPD:
3022 case ARM::STMIB_UPD:
3024 case ARM::tLDMIA_UPD:
3025 case ARM::tSTMIA_UPD:
3029 case ARM::t2LDMIA_RET:
3032 case ARM::t2LDMIA_UPD:
3033 case ARM::t2LDMDB_UPD:
3036 case ARM::t2STMIA_UPD:
3037 case ARM::t2STMDB_UPD: {
3038 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
3039 if (Subtarget.isSwift()) {
3040 int UOps = 1 + NumRegs; // One for address computation, one for each ld / st.
3043 case ARM::VLDMDIA_UPD:
3044 case ARM::VLDMDDB_UPD:
3045 case ARM::VLDMSIA_UPD:
3046 case ARM::VLDMSDB_UPD:
3047 case ARM::VSTMDIA_UPD:
3048 case ARM::VSTMDDB_UPD:
3049 case ARM::VSTMSIA_UPD:
3050 case ARM::VSTMSDB_UPD:
3051 case ARM::LDMIA_UPD:
3052 case ARM::LDMDA_UPD:
3053 case ARM::LDMDB_UPD:
3054 case ARM::LDMIB_UPD:
3055 case ARM::STMIA_UPD:
3056 case ARM::STMDA_UPD:
3057 case ARM::STMDB_UPD:
3058 case ARM::STMIB_UPD:
3059 case ARM::tLDMIA_UPD:
3060 case ARM::tSTMIA_UPD:
3061 case ARM::t2LDMIA_UPD:
3062 case ARM::t2LDMDB_UPD:
3063 case ARM::t2STMIA_UPD:
3064 case ARM::t2STMDB_UPD:
3065 ++UOps; // One for base register writeback.
3067 case ARM::LDMIA_RET:
3069 case ARM::t2LDMIA_RET:
3070 UOps += 2; // One for base reg wb, one for write to pc.
3074 } else if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3077 // 4 registers would be issued: 2, 2.
3078 // 5 registers would be issued: 2, 2, 1.
3079 int A8UOps = (NumRegs / 2);
3083 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3084 int A9UOps = (NumRegs / 2);
3085 // If there are odd number of registers or if it's not 64-bit aligned,
3086 // then it takes an extra AGU (Address Generation Unit) cycle.
3087 if ((NumRegs % 2) ||
3088 !MI->hasOneMemOperand() ||
3089 (*MI->memoperands_begin())->getAlignment() < 8)
3093 // Assume the worst.
3101 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
3102 const MCInstrDesc &DefMCID,
3104 unsigned DefIdx, unsigned DefAlign) const {
3105 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3107 // Def is the address writeback.
3108 return ItinData->getOperandCycle(DefClass, DefIdx);
3111 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3112 // (regno / 2) + (regno % 2) + 1
3113 DefCycle = RegNo / 2 + 1;
3116 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3118 bool isSLoad = false;
3120 switch (DefMCID.getOpcode()) {
3123 case ARM::VLDMSIA_UPD:
3124 case ARM::VLDMSDB_UPD:
3129 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3130 // then it takes an extra cycle.
3131 if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
3134 // Assume the worst.
3135 DefCycle = RegNo + 2;
3142 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
3143 const MCInstrDesc &DefMCID,
3145 unsigned DefIdx, unsigned DefAlign) const {
3146 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3148 // Def is the address writeback.
3149 return ItinData->getOperandCycle(DefClass, DefIdx);
3152 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3153 // 4 registers would be issued: 1, 2, 1.
3154 // 5 registers would be issued: 1, 2, 2.
3155 DefCycle = RegNo / 2;
3158 // Result latency is issue cycle + 2: E2.
3160 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3161 DefCycle = (RegNo / 2);
3162 // If there are odd number of registers or if it's not 64-bit aligned,
3163 // then it takes an extra AGU (Address Generation Unit) cycle.
3164 if ((RegNo % 2) || DefAlign < 8)
3166 // Result latency is AGU cycles + 2.
3169 // Assume the worst.
3170 DefCycle = RegNo + 2;
3177 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
3178 const MCInstrDesc &UseMCID,
3180 unsigned UseIdx, unsigned UseAlign) const {
3181 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3183 return ItinData->getOperandCycle(UseClass, UseIdx);
3186 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3187 // (regno / 2) + (regno % 2) + 1
3188 UseCycle = RegNo / 2 + 1;
3191 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3193 bool isSStore = false;
3195 switch (UseMCID.getOpcode()) {
3198 case ARM::VSTMSIA_UPD:
3199 case ARM::VSTMSDB_UPD:
3204 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3205 // then it takes an extra cycle.
3206 if ((isSStore && (RegNo % 2)) || UseAlign < 8)
3209 // Assume the worst.
3210 UseCycle = RegNo + 2;
3217 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
3218 const MCInstrDesc &UseMCID,
3220 unsigned UseIdx, unsigned UseAlign) const {
3221 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3223 return ItinData->getOperandCycle(UseClass, UseIdx);
3226 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3227 UseCycle = RegNo / 2;
3232 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3233 UseCycle = (RegNo / 2);
3234 // If there are odd number of registers or if it's not 64-bit aligned,
3235 // then it takes an extra AGU (Address Generation Unit) cycle.
3236 if ((RegNo % 2) || UseAlign < 8)
3239 // Assume the worst.
3246 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3247 const MCInstrDesc &DefMCID,
3248 unsigned DefIdx, unsigned DefAlign,
3249 const MCInstrDesc &UseMCID,
3250 unsigned UseIdx, unsigned UseAlign) const {
3251 unsigned DefClass = DefMCID.getSchedClass();
3252 unsigned UseClass = UseMCID.getSchedClass();
3254 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
3255 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
3257 // This may be a def / use of a variable_ops instruction, the operand
3258 // latency might be determinable dynamically. Let the target try to
3261 bool LdmBypass = false;
3262 switch (DefMCID.getOpcode()) {
3264 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
3268 case ARM::VLDMDIA_UPD:
3269 case ARM::VLDMDDB_UPD:
3271 case ARM::VLDMSIA_UPD:
3272 case ARM::VLDMSDB_UPD:
3273 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3276 case ARM::LDMIA_RET:
3281 case ARM::LDMIA_UPD:
3282 case ARM::LDMDA_UPD:
3283 case ARM::LDMDB_UPD:
3284 case ARM::LDMIB_UPD:
3286 case ARM::tLDMIA_UPD:
3288 case ARM::t2LDMIA_RET:
3291 case ARM::t2LDMIA_UPD:
3292 case ARM::t2LDMDB_UPD:
3294 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3299 // We can't seem to determine the result latency of the def, assume it's 2.
3303 switch (UseMCID.getOpcode()) {
3305 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
3309 case ARM::VSTMDIA_UPD:
3310 case ARM::VSTMDDB_UPD:
3312 case ARM::VSTMSIA_UPD:
3313 case ARM::VSTMSDB_UPD:
3314 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3321 case ARM::STMIA_UPD:
3322 case ARM::STMDA_UPD:
3323 case ARM::STMDB_UPD:
3324 case ARM::STMIB_UPD:
3325 case ARM::tSTMIA_UPD:
3330 case ARM::t2STMIA_UPD:
3331 case ARM::t2STMDB_UPD:
3332 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3337 // Assume it's read in the first stage.
3340 UseCycle = DefCycle - UseCycle + 1;
3343 // It's a variable_ops instruction so we can't use DefIdx here. Just use
3344 // first def operand.
3345 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
3348 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
3349 UseClass, UseIdx)) {
3357 static const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI,
3358 const MachineInstr *MI, unsigned Reg,
3359 unsigned &DefIdx, unsigned &Dist) {
3362 MachineBasicBlock::const_iterator I = MI; ++I;
3363 MachineBasicBlock::const_instr_iterator II = std::prev(I.getInstrIterator());
3364 assert(II->isInsideBundle() && "Empty bundle?");
3367 while (II->isInsideBundle()) {
3368 Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI);
3375 assert(Idx != -1 && "Cannot find bundled definition!");
3380 static const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI,
3381 const MachineInstr *MI, unsigned Reg,
3382 unsigned &UseIdx, unsigned &Dist) {
3385 MachineBasicBlock::const_instr_iterator II = MI; ++II;
3386 assert(II->isInsideBundle() && "Empty bundle?");
3387 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
3389 // FIXME: This doesn't properly handle multiple uses.
3391 while (II != E && II->isInsideBundle()) {
3392 Idx = II->findRegisterUseOperandIdx(Reg, false, TRI);
3395 if (II->getOpcode() != ARM::t2IT)
3409 /// Return the number of cycles to add to (or subtract from) the static
3410 /// itinerary based on the def opcode and alignment. The caller will ensure that
3411 /// adjusted latency is at least one cycle.
3412 static int adjustDefLatency(const ARMSubtarget &Subtarget,
3413 const MachineInstr *DefMI,
3414 const MCInstrDesc *DefMCID, unsigned DefAlign) {
3416 if (Subtarget.isCortexA8() || Subtarget.isLikeA9() || Subtarget.isCortexA7()) {
3417 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3418 // variants are one cycle cheaper.
3419 switch (DefMCID->getOpcode()) {
3423 unsigned ShOpVal = DefMI->getOperand(3).getImm();
3424 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3426 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3433 case ARM::t2LDRSHs: {
3434 // Thumb2 mode: lsl only.
3435 unsigned ShAmt = DefMI->getOperand(3).getImm();
3436 if (ShAmt == 0 || ShAmt == 2)
3441 } else if (Subtarget.isSwift()) {
3442 // FIXME: Properly handle all of the latency adjustments for address
3444 switch (DefMCID->getOpcode()) {
3448 unsigned ShOpVal = DefMI->getOperand(3).getImm();
3449 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3450 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3453 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3454 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3457 ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
3464 case ARM::t2LDRSHs: {
3465 // Thumb2 mode: lsl only.
3466 unsigned ShAmt = DefMI->getOperand(3).getImm();
3467 if (ShAmt == 0 || ShAmt == 1 || ShAmt == 2 || ShAmt == 3)
3474 if (DefAlign < 8 && Subtarget.isLikeA9()) {
3475 switch (DefMCID->getOpcode()) {
3481 case ARM::VLD1q8wb_fixed:
3482 case ARM::VLD1q16wb_fixed:
3483 case ARM::VLD1q32wb_fixed:
3484 case ARM::VLD1q64wb_fixed:
3485 case ARM::VLD1q8wb_register:
3486 case ARM::VLD1q16wb_register:
3487 case ARM::VLD1q32wb_register:
3488 case ARM::VLD1q64wb_register:
3495 case ARM::VLD2d8wb_fixed:
3496 case ARM::VLD2d16wb_fixed:
3497 case ARM::VLD2d32wb_fixed:
3498 case ARM::VLD2q8wb_fixed:
3499 case ARM::VLD2q16wb_fixed:
3500 case ARM::VLD2q32wb_fixed:
3501 case ARM::VLD2d8wb_register:
3502 case ARM::VLD2d16wb_register:
3503 case ARM::VLD2d32wb_register:
3504 case ARM::VLD2q8wb_register:
3505 case ARM::VLD2q16wb_register:
3506 case ARM::VLD2q32wb_register:
3511 case ARM::VLD3d8_UPD:
3512 case ARM::VLD3d16_UPD:
3513 case ARM::VLD3d32_UPD:
3514 case ARM::VLD1d64Twb_fixed:
3515 case ARM::VLD1d64Twb_register:
3516 case ARM::VLD3q8_UPD:
3517 case ARM::VLD3q16_UPD:
3518 case ARM::VLD3q32_UPD:
3523 case ARM::VLD4d8_UPD:
3524 case ARM::VLD4d16_UPD:
3525 case ARM::VLD4d32_UPD:
3526 case ARM::VLD1d64Qwb_fixed:
3527 case ARM::VLD1d64Qwb_register:
3528 case ARM::VLD4q8_UPD:
3529 case ARM::VLD4q16_UPD:
3530 case ARM::VLD4q32_UPD:
3531 case ARM::VLD1DUPq8:
3532 case ARM::VLD1DUPq16:
3533 case ARM::VLD1DUPq32:
3534 case ARM::VLD1DUPq8wb_fixed:
3535 case ARM::VLD1DUPq16wb_fixed:
3536 case ARM::VLD1DUPq32wb_fixed:
3537 case ARM::VLD1DUPq8wb_register:
3538 case ARM::VLD1DUPq16wb_register:
3539 case ARM::VLD1DUPq32wb_register:
3540 case ARM::VLD2DUPd8:
3541 case ARM::VLD2DUPd16:
3542 case ARM::VLD2DUPd32:
3543 case ARM::VLD2DUPd8wb_fixed:
3544 case ARM::VLD2DUPd16wb_fixed:
3545 case ARM::VLD2DUPd32wb_fixed:
3546 case ARM::VLD2DUPd8wb_register:
3547 case ARM::VLD2DUPd16wb_register:
3548 case ARM::VLD2DUPd32wb_register:
3549 case ARM::VLD4DUPd8:
3550 case ARM::VLD4DUPd16:
3551 case ARM::VLD4DUPd32:
3552 case ARM::VLD4DUPd8_UPD:
3553 case ARM::VLD4DUPd16_UPD:
3554 case ARM::VLD4DUPd32_UPD:
3556 case ARM::VLD1LNd16:
3557 case ARM::VLD1LNd32:
3558 case ARM::VLD1LNd8_UPD:
3559 case ARM::VLD1LNd16_UPD:
3560 case ARM::VLD1LNd32_UPD:
3562 case ARM::VLD2LNd16:
3563 case ARM::VLD2LNd32:
3564 case ARM::VLD2LNq16:
3565 case ARM::VLD2LNq32:
3566 case ARM::VLD2LNd8_UPD:
3567 case ARM::VLD2LNd16_UPD:
3568 case ARM::VLD2LNd32_UPD:
3569 case ARM::VLD2LNq16_UPD:
3570 case ARM::VLD2LNq32_UPD:
3572 case ARM::VLD4LNd16:
3573 case ARM::VLD4LNd32:
3574 case ARM::VLD4LNq16:
3575 case ARM::VLD4LNq32:
3576 case ARM::VLD4LNd8_UPD:
3577 case ARM::VLD4LNd16_UPD:
3578 case ARM::VLD4LNd32_UPD:
3579 case ARM::VLD4LNq16_UPD:
3580 case ARM::VLD4LNq32_UPD:
3581 // If the address is not 64-bit aligned, the latencies of these
3582 // instructions increases by one.
3593 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3594 const MachineInstr *DefMI, unsigned DefIdx,
3595 const MachineInstr *UseMI,
3596 unsigned UseIdx) const {
3597 // No operand latency. The caller may fall back to getInstrLatency.
3598 if (!ItinData || ItinData->isEmpty())
3601 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
3602 unsigned Reg = DefMO.getReg();
3603 const MCInstrDesc *DefMCID = &DefMI->getDesc();
3604 const MCInstrDesc *UseMCID = &UseMI->getDesc();
3606 unsigned DefAdj = 0;
3607 if (DefMI->isBundle()) {
3608 DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj);
3609 DefMCID = &DefMI->getDesc();
3611 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
3612 DefMI->isRegSequence() || DefMI->isImplicitDef()) {
3616 unsigned UseAdj = 0;
3617 if (UseMI->isBundle()) {
3619 const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI,
3620 Reg, NewUseIdx, UseAdj);
3626 UseMCID = &UseMI->getDesc();
3629 if (Reg == ARM::CPSR) {
3630 if (DefMI->getOpcode() == ARM::FMSTAT) {
3631 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
3632 return Subtarget.isLikeA9() ? 1 : 20;
3635 // CPSR set and branch can be paired in the same cycle.
3636 if (UseMI->isBranch())
3639 // Otherwise it takes the instruction latency (generally one).
3640 unsigned Latency = getInstrLatency(ItinData, DefMI);
3642 // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to
3643 // its uses. Instructions which are otherwise scheduled between them may
3644 // incur a code size penalty (not able to use the CPSR setting 16-bit
3646 if (Latency > 0 && Subtarget.isThumb2()) {
3647 const MachineFunction *MF = DefMI->getParent()->getParent();
3648 if (MF->getFunction()->getAttributes().
3649 hasAttribute(AttributeSet::FunctionIndex,
3650 Attribute::OptimizeForSize))
3656 if (DefMO.isImplicit() || UseMI->getOperand(UseIdx).isImplicit())
3659 unsigned DefAlign = DefMI->hasOneMemOperand()
3660 ? (*DefMI->memoperands_begin())->getAlignment() : 0;
3661 unsigned UseAlign = UseMI->hasOneMemOperand()
3662 ? (*UseMI->memoperands_begin())->getAlignment() : 0;
3664 // Get the itinerary's latency if possible, and handle variable_ops.
3665 int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign,
3666 *UseMCID, UseIdx, UseAlign);
3667 // Unable to find operand latency. The caller may resort to getInstrLatency.
3671 // Adjust for IT block position.
3672 int Adj = DefAdj + UseAdj;
3674 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3675 Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign);
3676 if (Adj >= 0 || (int)Latency > -Adj) {
3677 return Latency + Adj;
3679 // Return the itinerary latency, which may be zero but not less than zero.
3684 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3685 SDNode *DefNode, unsigned DefIdx,
3686 SDNode *UseNode, unsigned UseIdx) const {
3687 if (!DefNode->isMachineOpcode())
3690 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
3692 if (isZeroCost(DefMCID.Opcode))
3695 if (!ItinData || ItinData->isEmpty())
3696 return DefMCID.mayLoad() ? 3 : 1;
3698 if (!UseNode->isMachineOpcode()) {
3699 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
3700 if (Subtarget.isLikeA9() || Subtarget.isSwift())
3701 return Latency <= 2 ? 1 : Latency - 1;
3703 return Latency <= 3 ? 1 : Latency - 2;
3706 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
3707 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
3708 unsigned DefAlign = !DefMN->memoperands_empty()
3709 ? (*DefMN->memoperands_begin())->getAlignment() : 0;
3710 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
3711 unsigned UseAlign = !UseMN->memoperands_empty()
3712 ? (*UseMN->memoperands_begin())->getAlignment() : 0;
3713 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
3714 UseMCID, UseIdx, UseAlign);
3717 (Subtarget.isCortexA8() || Subtarget.isLikeA9() ||
3718 Subtarget.isCortexA7())) {
3719 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3720 // variants are one cycle cheaper.
3721 switch (DefMCID.getOpcode()) {
3726 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3727 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3729 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3736 case ARM::t2LDRSHs: {
3737 // Thumb2 mode: lsl only.
3739 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3740 if (ShAmt == 0 || ShAmt == 2)
3745 } else if (DefIdx == 0 && Latency > 2 && Subtarget.isSwift()) {
3746 // FIXME: Properly handle all of the latency adjustments for address
3748 switch (DefMCID.getOpcode()) {
3753 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3754 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3756 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3757 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3759 else if (ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
3766 case ARM::t2LDRSHs: {
3767 // Thumb2 mode: lsl 0-3 only.
3774 if (DefAlign < 8 && Subtarget.isLikeA9())
3775 switch (DefMCID.getOpcode()) {
3781 case ARM::VLD1q8wb_register:
3782 case ARM::VLD1q16wb_register:
3783 case ARM::VLD1q32wb_register:
3784 case ARM::VLD1q64wb_register:
3785 case ARM::VLD1q8wb_fixed:
3786 case ARM::VLD1q16wb_fixed:
3787 case ARM::VLD1q32wb_fixed:
3788 case ARM::VLD1q64wb_fixed:
3792 case ARM::VLD2q8Pseudo:
3793 case ARM::VLD2q16Pseudo:
3794 case ARM::VLD2q32Pseudo:
3795 case ARM::VLD2d8wb_fixed:
3796 case ARM::VLD2d16wb_fixed:
3797 case ARM::VLD2d32wb_fixed:
3798 case ARM::VLD2q8PseudoWB_fixed:
3799 case ARM::VLD2q16PseudoWB_fixed:
3800 case ARM::VLD2q32PseudoWB_fixed:
3801 case ARM::VLD2d8wb_register:
3802 case ARM::VLD2d16wb_register:
3803 case ARM::VLD2d32wb_register:
3804 case ARM::VLD2q8PseudoWB_register:
3805 case ARM::VLD2q16PseudoWB_register:
3806 case ARM::VLD2q32PseudoWB_register:
3807 case ARM::VLD3d8Pseudo:
3808 case ARM::VLD3d16Pseudo:
3809 case ARM::VLD3d32Pseudo:
3810 case ARM::VLD1d64TPseudo:
3811 case ARM::VLD1d64TPseudoWB_fixed:
3812 case ARM::VLD3d8Pseudo_UPD:
3813 case ARM::VLD3d16Pseudo_UPD:
3814 case ARM::VLD3d32Pseudo_UPD:
3815 case ARM::VLD3q8Pseudo_UPD:
3816 case ARM::VLD3q16Pseudo_UPD:
3817 case ARM::VLD3q32Pseudo_UPD:
3818 case ARM::VLD3q8oddPseudo:
3819 case ARM::VLD3q16oddPseudo:
3820 case ARM::VLD3q32oddPseudo:
3821 case ARM::VLD3q8oddPseudo_UPD:
3822 case ARM::VLD3q16oddPseudo_UPD:
3823 case ARM::VLD3q32oddPseudo_UPD:
3824 case ARM::VLD4d8Pseudo:
3825 case ARM::VLD4d16Pseudo:
3826 case ARM::VLD4d32Pseudo:
3827 case ARM::VLD1d64QPseudo:
3828 case ARM::VLD1d64QPseudoWB_fixed:
3829 case ARM::VLD4d8Pseudo_UPD:
3830 case ARM::VLD4d16Pseudo_UPD:
3831 case ARM::VLD4d32Pseudo_UPD:
3832 case ARM::VLD4q8Pseudo_UPD:
3833 case ARM::VLD4q16Pseudo_UPD:
3834 case ARM::VLD4q32Pseudo_UPD:
3835 case ARM::VLD4q8oddPseudo:
3836 case ARM::VLD4q16oddPseudo:
3837 case ARM::VLD4q32oddPseudo:
3838 case ARM::VLD4q8oddPseudo_UPD:
3839 case ARM::VLD4q16oddPseudo_UPD:
3840 case ARM::VLD4q32oddPseudo_UPD:
3841 case ARM::VLD1DUPq8:
3842 case ARM::VLD1DUPq16:
3843 case ARM::VLD1DUPq32:
3844 case ARM::VLD1DUPq8wb_fixed:
3845 case ARM::VLD1DUPq16wb_fixed:
3846 case ARM::VLD1DUPq32wb_fixed:
3847 case ARM::VLD1DUPq8wb_register:
3848 case ARM::VLD1DUPq16wb_register:
3849 case ARM::VLD1DUPq32wb_register:
3850 case ARM::VLD2DUPd8:
3851 case ARM::VLD2DUPd16:
3852 case ARM::VLD2DUPd32:
3853 case ARM::VLD2DUPd8wb_fixed:
3854 case ARM::VLD2DUPd16wb_fixed:
3855 case ARM::VLD2DUPd32wb_fixed:
3856 case ARM::VLD2DUPd8wb_register:
3857 case ARM::VLD2DUPd16wb_register:
3858 case ARM::VLD2DUPd32wb_register:
3859 case ARM::VLD4DUPd8Pseudo:
3860 case ARM::VLD4DUPd16Pseudo:
3861 case ARM::VLD4DUPd32Pseudo:
3862 case ARM::VLD4DUPd8Pseudo_UPD:
3863 case ARM::VLD4DUPd16Pseudo_UPD:
3864 case ARM::VLD4DUPd32Pseudo_UPD:
3865 case ARM::VLD1LNq8Pseudo:
3866 case ARM::VLD1LNq16Pseudo:
3867 case ARM::VLD1LNq32Pseudo:
3868 case ARM::VLD1LNq8Pseudo_UPD:
3869 case ARM::VLD1LNq16Pseudo_UPD:
3870 case ARM::VLD1LNq32Pseudo_UPD:
3871 case ARM::VLD2LNd8Pseudo:
3872 case ARM::VLD2LNd16Pseudo:
3873 case ARM::VLD2LNd32Pseudo:
3874 case ARM::VLD2LNq16Pseudo:
3875 case ARM::VLD2LNq32Pseudo:
3876 case ARM::VLD2LNd8Pseudo_UPD:
3877 case ARM::VLD2LNd16Pseudo_UPD:
3878 case ARM::VLD2LNd32Pseudo_UPD:
3879 case ARM::VLD2LNq16Pseudo_UPD:
3880 case ARM::VLD2LNq32Pseudo_UPD:
3881 case ARM::VLD4LNd8Pseudo:
3882 case ARM::VLD4LNd16Pseudo:
3883 case ARM::VLD4LNd32Pseudo:
3884 case ARM::VLD4LNq16Pseudo:
3885 case ARM::VLD4LNq32Pseudo:
3886 case ARM::VLD4LNd8Pseudo_UPD:
3887 case ARM::VLD4LNd16Pseudo_UPD:
3888 case ARM::VLD4LNd32Pseudo_UPD:
3889 case ARM::VLD4LNq16Pseudo_UPD:
3890 case ARM::VLD4LNq32Pseudo_UPD:
3891 // If the address is not 64-bit aligned, the latencies of these
3892 // instructions increases by one.
3900 unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr *MI) const {
3901 if (MI->isCopyLike() || MI->isInsertSubreg() ||
3902 MI->isRegSequence() || MI->isImplicitDef())
3908 const MCInstrDesc &MCID = MI->getDesc();
3910 if (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR)) {
3911 // When predicated, CPSR is an additional source operand for CPSR updating
3912 // instructions, this apparently increases their latencies.
3918 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3919 const MachineInstr *MI,
3920 unsigned *PredCost) const {
3921 if (MI->isCopyLike() || MI->isInsertSubreg() ||
3922 MI->isRegSequence() || MI->isImplicitDef())
3925 // An instruction scheduler typically runs on unbundled instructions, however
3926 // other passes may query the latency of a bundled instruction.
3927 if (MI->isBundle()) {
3928 unsigned Latency = 0;
3929 MachineBasicBlock::const_instr_iterator I = MI;
3930 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
3931 while (++I != E && I->isInsideBundle()) {
3932 if (I->getOpcode() != ARM::t2IT)
3933 Latency += getInstrLatency(ItinData, I, PredCost);
3938 const MCInstrDesc &MCID = MI->getDesc();
3939 if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) {
3940 // When predicated, CPSR is an additional source operand for CPSR updating
3941 // instructions, this apparently increases their latencies.
3944 // Be sure to call getStageLatency for an empty itinerary in case it has a
3945 // valid MinLatency property.
3947 return MI->mayLoad() ? 3 : 1;
3949 unsigned Class = MCID.getSchedClass();
3951 // For instructions with variable uops, use uops as latency.
3952 if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)
3953 return getNumMicroOps(ItinData, MI);
3955 // For the common case, fall back on the itinerary's latency.
3956 unsigned Latency = ItinData->getStageLatency(Class);
3958 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3959 unsigned DefAlign = MI->hasOneMemOperand()
3960 ? (*MI->memoperands_begin())->getAlignment() : 0;
3961 int Adj = adjustDefLatency(Subtarget, MI, &MCID, DefAlign);
3962 if (Adj >= 0 || (int)Latency > -Adj) {
3963 return Latency + Adj;
3968 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3969 SDNode *Node) const {
3970 if (!Node->isMachineOpcode())
3973 if (!ItinData || ItinData->isEmpty())
3976 unsigned Opcode = Node->getMachineOpcode();
3979 return ItinData->getStageLatency(get(Opcode).getSchedClass());
3986 bool ARMBaseInstrInfo::
3987 hasHighOperandLatency(const InstrItineraryData *ItinData,
3988 const MachineRegisterInfo *MRI,
3989 const MachineInstr *DefMI, unsigned DefIdx,
3990 const MachineInstr *UseMI, unsigned UseIdx) const {
3991 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
3992 unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask;
3993 if (Subtarget.isCortexA8() &&
3994 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
3995 // CortexA8 VFP instructions are not pipelined.
3998 // Hoist VFP / NEON instructions with 4 or higher latency.
3999 int Latency = computeOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
4001 Latency = getInstrLatency(ItinData, DefMI);
4004 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
4005 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
4008 bool ARMBaseInstrInfo::
4009 hasLowDefLatency(const InstrItineraryData *ItinData,
4010 const MachineInstr *DefMI, unsigned DefIdx) const {
4011 if (!ItinData || ItinData->isEmpty())
4014 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
4015 if (DDomain == ARMII::DomainGeneral) {
4016 unsigned DefClass = DefMI->getDesc().getSchedClass();
4017 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
4018 return (DefCycle != -1 && DefCycle <= 2);
4023 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI,
4024 StringRef &ErrInfo) const {
4025 if (convertAddSubFlagsOpcode(MI->getOpcode())) {
4026 ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";
4032 // LoadStackGuard has so far only been implemented for MachO. Different code
4033 // sequence is needed for other targets.
4034 void ARMBaseInstrInfo::expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
4035 unsigned LoadImmOpc,
4037 Reloc::Model RM) const {
4038 MachineBasicBlock &MBB = *MI->getParent();
4039 DebugLoc DL = MI->getDebugLoc();
4040 unsigned Reg = MI->getOperand(0).getReg();
4041 const GlobalValue *GV =
4042 cast<GlobalValue>((*MI->memoperands_begin())->getValue());
4043 MachineInstrBuilder MIB;
4045 BuildMI(MBB, MI, DL, get(LoadImmOpc), Reg)
4046 .addGlobalAddress(GV, 0, ARMII::MO_NONLAZY);
4048 if (Subtarget.GVIsIndirectSymbol(GV, RM)) {
4049 MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4050 MIB.addReg(Reg, RegState::Kill).addImm(0);
4051 unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
4052 MachineMemOperand *MMO = MBB.getParent()->
4053 getMachineMemOperand(MachinePointerInfo::getGOT(), Flag, 4, 4);
4054 MIB.addMemOperand(MMO);
4055 AddDefaultPred(MIB);
4058 MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4059 MIB.addReg(Reg, RegState::Kill).addImm(0);
4060 MIB.setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
4061 AddDefaultPred(MIB);
4065 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
4066 unsigned &AddSubOpc,
4067 bool &NegAcc, bool &HasLane) const {
4068 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
4069 if (I == MLxEntryMap.end())
4072 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
4073 MulOpc = Entry.MulOpc;
4074 AddSubOpc = Entry.AddSubOpc;
4075 NegAcc = Entry.NegAcc;
4076 HasLane = Entry.HasLane;
4080 //===----------------------------------------------------------------------===//
4081 // Execution domains.
4082 //===----------------------------------------------------------------------===//
4084 // Some instructions go down the NEON pipeline, some go down the VFP pipeline,
4085 // and some can go down both. The vmov instructions go down the VFP pipeline,
4086 // but they can be changed to vorr equivalents that are executed by the NEON
4089 // We use the following execution domain numbering:
4097 // Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h
4099 std::pair<uint16_t, uint16_t>
4100 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const {
4101 // VMOVD, VMOVRS and VMOVSR are VFP instructions, but can be changed to NEON
4102 // if they are not predicated.
4103 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI))
4104 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON));
4106 // CortexA9 is particularly picky about mixing the two and wants these
4108 if (Subtarget.isCortexA9() && !isPredicated(MI) &&
4109 (MI->getOpcode() == ARM::VMOVRS ||
4110 MI->getOpcode() == ARM::VMOVSR ||
4111 MI->getOpcode() == ARM::VMOVS))
4112 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON));
4114 // No other instructions can be swizzled, so just determine their domain.
4115 unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask;
4117 if (Domain & ARMII::DomainNEON)
4118 return std::make_pair(ExeNEON, 0);
4120 // Certain instructions can go either way on Cortex-A8.
4121 // Treat them as NEON instructions.
4122 if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8())
4123 return std::make_pair(ExeNEON, 0);
4125 if (Domain & ARMII::DomainVFP)
4126 return std::make_pair(ExeVFP, 0);
4128 return std::make_pair(ExeGeneric, 0);
4131 static unsigned getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI,
4132 unsigned SReg, unsigned &Lane) {
4133 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass);
4136 if (DReg != ARM::NoRegister)
4140 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass);
4142 assert(DReg && "S-register with no D super-register?");
4146 /// getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane,
4147 /// set ImplicitSReg to a register number that must be marked as implicit-use or
4148 /// zero if no register needs to be defined as implicit-use.
4150 /// If the function cannot determine if an SPR should be marked implicit use or
4151 /// not, it returns false.
4153 /// This function handles cases where an instruction is being modified from taking
4154 /// an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict
4155 /// with an earlier def of an SPR corresponding to DPR[Lane^1] (i.e. the other
4156 /// lane of the DPR).
4158 /// If the other SPR is defined, an implicit-use of it should be added. Else,
4159 /// (including the case where the DPR itself is defined), it should not.
4161 static bool getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI,
4163 unsigned DReg, unsigned Lane,
4164 unsigned &ImplicitSReg) {
4165 // If the DPR is defined or used already, the other SPR lane will be chained
4166 // correctly, so there is nothing to be done.
4167 if (MI->definesRegister(DReg, TRI) || MI->readsRegister(DReg, TRI)) {
4172 // Otherwise we need to go searching to see if the SPR is set explicitly.
4173 ImplicitSReg = TRI->getSubReg(DReg,
4174 (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1);
4175 MachineBasicBlock::LivenessQueryResult LQR =
4176 MI->getParent()->computeRegisterLiveness(TRI, ImplicitSReg, MI);
4178 if (LQR == MachineBasicBlock::LQR_Live)
4180 else if (LQR == MachineBasicBlock::LQR_Unknown)
4183 // If the register is known not to be live, there is no need to add an
4190 ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
4191 unsigned DstReg, SrcReg, DReg;
4193 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
4194 const TargetRegisterInfo *TRI = &getRegisterInfo();
4195 switch (MI->getOpcode()) {
4197 llvm_unreachable("cannot handle opcode!");
4200 if (Domain != ExeNEON)
4203 // Zap the predicate operands.
4204 assert(!isPredicated(MI) && "Cannot predicate a VORRd");
4206 // Source instruction is %DDst = VMOVD %DSrc, 14, %noreg (; implicits)
4207 DstReg = MI->getOperand(0).getReg();
4208 SrcReg = MI->getOperand(1).getReg();
4210 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4211 MI->RemoveOperand(i-1);
4213 // Change to a %DDst = VORRd %DSrc, %DSrc, 14, %noreg (; implicits)
4214 MI->setDesc(get(ARM::VORRd));
4215 AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
4220 if (Domain != ExeNEON)
4222 assert(!isPredicated(MI) && "Cannot predicate a VGETLN");
4224 // Source instruction is %RDst = VMOVRS %SSrc, 14, %noreg (; implicits)
4225 DstReg = MI->getOperand(0).getReg();
4226 SrcReg = MI->getOperand(1).getReg();
4228 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4229 MI->RemoveOperand(i-1);
4231 DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane);
4233 // Convert to %RDst = VGETLNi32 %DSrc, Lane, 14, %noreg (; imps)
4234 // Note that DSrc has been widened and the other lane may be undef, which
4235 // contaminates the entire register.
4236 MI->setDesc(get(ARM::VGETLNi32));
4237 AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
4238 .addReg(DReg, RegState::Undef)
4241 // The old source should be an implicit use, otherwise we might think it
4242 // was dead before here.
4243 MIB.addReg(SrcReg, RegState::Implicit);
4246 if (Domain != ExeNEON)
4248 assert(!isPredicated(MI) && "Cannot predicate a VSETLN");
4250 // Source instruction is %SDst = VMOVSR %RSrc, 14, %noreg (; implicits)
4251 DstReg = MI->getOperand(0).getReg();
4252 SrcReg = MI->getOperand(1).getReg();
4254 DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane);
4256 unsigned ImplicitSReg;
4257 if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg))
4260 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4261 MI->RemoveOperand(i-1);
4263 // Convert to %DDst = VSETLNi32 %DDst, %RSrc, Lane, 14, %noreg (; imps)
4264 // Again DDst may be undefined at the beginning of this instruction.
4265 MI->setDesc(get(ARM::VSETLNi32));
4266 MIB.addReg(DReg, RegState::Define)
4267 .addReg(DReg, getUndefRegState(!MI->readsRegister(DReg, TRI)))
4270 AddDefaultPred(MIB);
4272 // The narrower destination must be marked as set to keep previous chains
4274 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4275 if (ImplicitSReg != 0)
4276 MIB.addReg(ImplicitSReg, RegState::Implicit);
4280 if (Domain != ExeNEON)
4283 // Source instruction is %SDst = VMOVS %SSrc, 14, %noreg (; implicits)
4284 DstReg = MI->getOperand(0).getReg();
4285 SrcReg = MI->getOperand(1).getReg();
4287 unsigned DstLane = 0, SrcLane = 0, DDst, DSrc;
4288 DDst = getCorrespondingDRegAndLane(TRI, DstReg, DstLane);
4289 DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane);
4291 unsigned ImplicitSReg;
4292 if (!getImplicitSPRUseForDPRUse(TRI, MI, DSrc, SrcLane, ImplicitSReg))
4295 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4296 MI->RemoveOperand(i-1);
4299 // Destination can be:
4300 // %DDst = VDUPLN32d %DDst, Lane, 14, %noreg (; implicits)
4301 MI->setDesc(get(ARM::VDUPLN32d));
4302 MIB.addReg(DDst, RegState::Define)
4303 .addReg(DDst, getUndefRegState(!MI->readsRegister(DDst, TRI)))
4305 AddDefaultPred(MIB);
4307 // Neither the source or the destination are naturally represented any
4308 // more, so add them in manually.
4309 MIB.addReg(DstReg, RegState::Implicit | RegState::Define);
4310 MIB.addReg(SrcReg, RegState::Implicit);
4311 if (ImplicitSReg != 0)
4312 MIB.addReg(ImplicitSReg, RegState::Implicit);
4316 // In general there's no single instruction that can perform an S <-> S
4317 // move in NEON space, but a pair of VEXT instructions *can* do the
4318 // job. It turns out that the VEXTs needed will only use DSrc once, with
4319 // the position based purely on the combination of lane-0 and lane-1
4320 // involved. For example
4321 // vmov s0, s2 -> vext.32 d0, d0, d1, #1 vext.32 d0, d0, d0, #1
4322 // vmov s1, s3 -> vext.32 d0, d1, d0, #1 vext.32 d0, d0, d0, #1
4323 // vmov s0, s3 -> vext.32 d0, d0, d0, #1 vext.32 d0, d1, d0, #1
4324 // vmov s1, s2 -> vext.32 d0, d0, d0, #1 vext.32 d0, d0, d1, #1
4326 // Pattern of the MachineInstrs is:
4327 // %DDst = VEXTd32 %DSrc1, %DSrc2, Lane, 14, %noreg (;implicits)
4328 MachineInstrBuilder NewMIB;
4329 NewMIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
4330 get(ARM::VEXTd32), DDst);
4332 // On the first instruction, both DSrc and DDst may be <undef> if present.
4333 // Specifically when the original instruction didn't have them as an
4335 unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst;
4336 bool CurUndef = !MI->readsRegister(CurReg, TRI);
4337 NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
4339 CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst;
4340 CurUndef = !MI->readsRegister(CurReg, TRI);
4341 NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
4344 AddDefaultPred(NewMIB);
4346 if (SrcLane == DstLane)
4347 NewMIB.addReg(SrcReg, RegState::Implicit);
4349 MI->setDesc(get(ARM::VEXTd32));
4350 MIB.addReg(DDst, RegState::Define);
4352 // On the second instruction, DDst has definitely been defined above, so
4353 // it is not <undef>. DSrc, if present, can be <undef> as above.
4354 CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst;
4355 CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI);
4356 MIB.addReg(CurReg, getUndefRegState(CurUndef));
4358 CurReg = SrcLane == 0 && DstLane == 1 ? DSrc : DDst;
4359 CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI);
4360 MIB.addReg(CurReg, getUndefRegState(CurUndef));
4363 AddDefaultPred(MIB);
4365 if (SrcLane != DstLane)
4366 MIB.addReg(SrcReg, RegState::Implicit);
4368 // As before, the original destination is no longer represented, add it
4370 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4371 if (ImplicitSReg != 0)
4372 MIB.addReg(ImplicitSReg, RegState::Implicit);
4379 //===----------------------------------------------------------------------===//
4380 // Partial register updates
4381 //===----------------------------------------------------------------------===//
4383 // Swift renames NEON registers with 64-bit granularity. That means any
4384 // instruction writing an S-reg implicitly reads the containing D-reg. The
4385 // problem is mostly avoided by translating f32 operations to v2f32 operations
4386 // on D-registers, but f32 loads are still a problem.
4388 // These instructions can load an f32 into a NEON register:
4390 // VLDRS - Only writes S, partial D update.
4391 // VLD1LNd32 - Writes all D-regs, explicit partial D update, 2 uops.
4392 // VLD1DUPd32 - Writes all D-regs, no partial reg update, 2 uops.
4394 // FCONSTD can be used as a dependency-breaking instruction.
4395 unsigned ARMBaseInstrInfo::
4396 getPartialRegUpdateClearance(const MachineInstr *MI,
4398 const TargetRegisterInfo *TRI) const {
4399 if (!SwiftPartialUpdateClearance ||
4400 !(Subtarget.isSwift() || Subtarget.isCortexA15()))
4403 assert(TRI && "Need TRI instance");
4405 const MachineOperand &MO = MI->getOperand(OpNum);
4408 unsigned Reg = MO.getReg();
4411 switch(MI->getOpcode()) {
4412 // Normal instructions writing only an S-register.
4417 case ARM::VMOVv4i16:
4418 case ARM::VMOVv2i32:
4419 case ARM::VMOVv2f32:
4420 case ARM::VMOVv1i64:
4421 UseOp = MI->findRegisterUseOperandIdx(Reg, false, TRI);
4424 // Explicitly reads the dependency.
4425 case ARM::VLD1LNd32:
4432 // If this instruction actually reads a value from Reg, there is no unwanted
4434 if (UseOp != -1 && MI->getOperand(UseOp).readsReg())
4437 // We must be able to clobber the whole D-reg.
4438 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4439 // Virtual register must be a foo:ssub_0<def,undef> operand.
4440 if (!MO.getSubReg() || MI->readsVirtualRegister(Reg))
4442 } else if (ARM::SPRRegClass.contains(Reg)) {
4443 // Physical register: MI must define the full D-reg.
4444 unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0,
4446 if (!DReg || !MI->definesRegister(DReg, TRI))
4450 // MI has an unwanted D-register dependency.
4451 // Avoid defs in the previous N instructrions.
4452 return SwiftPartialUpdateClearance;
4455 // Break a partial register dependency after getPartialRegUpdateClearance
4456 // returned non-zero.
4457 void ARMBaseInstrInfo::
4458 breakPartialRegDependency(MachineBasicBlock::iterator MI,
4460 const TargetRegisterInfo *TRI) const {
4461 assert(MI && OpNum < MI->getDesc().getNumDefs() && "OpNum is not a def");
4462 assert(TRI && "Need TRI instance");
4464 const MachineOperand &MO = MI->getOperand(OpNum);
4465 unsigned Reg = MO.getReg();
4466 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
4467 "Can't break virtual register dependencies.");
4468 unsigned DReg = Reg;
4470 // If MI defines an S-reg, find the corresponding D super-register.
4471 if (ARM::SPRRegClass.contains(Reg)) {
4472 DReg = ARM::D0 + (Reg - ARM::S0) / 2;
4473 assert(TRI->isSuperRegister(Reg, DReg) && "Register enums broken");
4476 assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps");
4477 assert(MI->definesRegister(DReg, TRI) && "MI doesn't clobber full D-reg");
4479 // FIXME: In some cases, VLDRS can be changed to a VLD1DUPd32 which defines
4480 // the full D-register by loading the same value to both lanes. The
4481 // instruction is micro-coded with 2 uops, so don't do this until we can
4482 // properly schedule micro-coded instructions. The dispatcher stalls cause
4483 // too big regressions.
4485 // Insert the dependency-breaking FCONSTD before MI.
4486 // 96 is the encoding of 0.5, but the actual value doesn't matter here.
4487 AddDefaultPred(BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
4488 get(ARM::FCONSTD), DReg).addImm(96));
4489 MI->addRegisterKilled(DReg, TRI, true);
4492 bool ARMBaseInstrInfo::hasNOP() const {
4493 return (Subtarget.getFeatureBits() & ARM::HasV6T2Ops) != 0;
4496 bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {
4497 if (MI->getNumOperands() < 4)
4499 unsigned ShOpVal = MI->getOperand(3).getImm();
4500 unsigned ShImm = ARM_AM::getSORegOffset(ShOpVal);
4501 // Swift supports faster shifts for: lsl 2, lsl 1, and lsr 1.
4502 if ((ShImm == 1 && ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsr) ||
4503 ((ShImm == 1 || ShImm == 2) &&
4504 ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsl))
4510 bool ARMBaseInstrInfo::getRegSequenceLikeInputs(
4511 const MachineInstr &MI, unsigned DefIdx,
4512 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
4513 assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
4514 assert(MI.isRegSequenceLike() && "Invalid kind of instruction");
4516 switch (MI.getOpcode()) {
4518 // dX = VMOVDRR rY, rZ
4520 // dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1
4521 // Populate the InputRegs accordingly.
4523 const MachineOperand *MOReg = &MI.getOperand(1);
4524 InputRegs.push_back(
4525 RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_0));
4527 MOReg = &MI.getOperand(2);
4528 InputRegs.push_back(
4529 RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_1));
4532 llvm_unreachable("Target dependent opcode missing");
4535 bool ARMBaseInstrInfo::getExtractSubregLikeInputs(
4536 const MachineInstr &MI, unsigned DefIdx,
4537 RegSubRegPairAndIdx &InputReg) const {
4538 assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
4539 assert(MI.isExtractSubregLike() && "Invalid kind of instruction");
4541 switch (MI.getOpcode()) {
4543 // rX, rY = VMOVRRD dZ
4545 // rX = EXTRACT_SUBREG dZ, ssub_0
4546 // rY = EXTRACT_SUBREG dZ, ssub_1
4547 const MachineOperand &MOReg = MI.getOperand(2);
4548 InputReg.Reg = MOReg.getReg();
4549 InputReg.SubReg = MOReg.getSubReg();
4550 InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1;
4553 llvm_unreachable("Target dependent opcode missing");
4556 bool ARMBaseInstrInfo::getInsertSubregLikeInputs(
4557 const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg,
4558 RegSubRegPairAndIdx &InsertedReg) const {
4559 assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
4560 assert(MI.isInsertSubregLike() && "Invalid kind of instruction");
4562 switch (MI.getOpcode()) {
4563 case ARM::VSETLNi32:
4564 // dX = VSETLNi32 dY, rZ, imm
4565 const MachineOperand &MOBaseReg = MI.getOperand(1);
4566 const MachineOperand &MOInsertedReg = MI.getOperand(2);
4567 const MachineOperand &MOIndex = MI.getOperand(3);
4568 BaseReg.Reg = MOBaseReg.getReg();
4569 BaseReg.SubReg = MOBaseReg.getSubReg();
4571 InsertedReg.Reg = MOInsertedReg.getReg();
4572 InsertedReg.SubReg = MOInsertedReg.getSubReg();
4573 InsertedReg.SubIdx = MOIndex.getImm() == 0 ? ARM::ssub_0 : ARM::ssub_1;
4576 llvm_unreachable("Target dependent opcode missing");