1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
16 #include "ARMAsmPrinter.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMFPUName.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMTargetMachine.h"
22 #include "ARMTargetObjectFile.h"
23 #include "InstPrinter/ARMInstPrinter.h"
24 #include "MCTargetDesc/ARMAddressingModes.h"
25 #include "MCTargetDesc/ARMMCExpr.h"
26 #include "llvm/ADT/SetVector.h"
27 #include "llvm/ADT/SmallString.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineJumpTableInfo.h"
30 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
31 #include "llvm/DebugInfo.h"
32 #include "llvm/IR/Constants.h"
33 #include "llvm/IR/DataLayout.h"
34 #include "llvm/IR/Mangler.h"
35 #include "llvm/IR/Module.h"
36 #include "llvm/IR/Type.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/MC/MCAssembler.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCELFStreamer.h"
41 #include "llvm/MC/MCInst.h"
42 #include "llvm/MC/MCInstBuilder.h"
43 #include "llvm/MC/MCObjectStreamer.h"
44 #include "llvm/MC/MCSectionMachO.h"
45 #include "llvm/MC/MCStreamer.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/ARMBuildAttributes.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ELF.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/TargetRegistry.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetMachine.h"
58 /// EmitDwarfRegOp - Emit dwarf register operation.
59 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc,
60 bool Indirect) const {
61 const TargetRegisterInfo *RI = TM.getRegisterInfo();
62 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1) {
63 AsmPrinter::EmitDwarfRegOp(MLoc, Indirect);
66 assert(MLoc.isReg() && !Indirect &&
67 "This doesn't support offset/indirection - implement it if needed");
68 unsigned Reg = MLoc.getReg();
69 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
70 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
71 // S registers are described as bit-pieces of a register
72 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
73 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
75 unsigned SReg = Reg - ARM::S0;
76 bool odd = SReg & 0x1;
77 unsigned Rx = 256 + (SReg >> 1);
79 OutStreamer.AddComment("DW_OP_regx for S register");
80 EmitInt8(dwarf::DW_OP_regx);
82 OutStreamer.AddComment(Twine(SReg));
86 OutStreamer.AddComment("DW_OP_bit_piece 32 32");
87 EmitInt8(dwarf::DW_OP_bit_piece);
91 OutStreamer.AddComment("DW_OP_bit_piece 32 0");
92 EmitInt8(dwarf::DW_OP_bit_piece);
96 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
97 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
98 // Q registers Q0-Q15 are described by composing two D registers together.
99 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1)
102 unsigned QReg = Reg - ARM::Q0;
103 unsigned D1 = 256 + 2 * QReg;
104 unsigned D2 = D1 + 1;
106 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
107 EmitInt8(dwarf::DW_OP_regx);
109 OutStreamer.AddComment("DW_OP_piece 8");
110 EmitInt8(dwarf::DW_OP_piece);
113 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
114 EmitInt8(dwarf::DW_OP_regx);
116 OutStreamer.AddComment("DW_OP_piece 8");
117 EmitInt8(dwarf::DW_OP_piece);
122 void ARMAsmPrinter::EmitFunctionBodyEnd() {
123 // Make sure to terminate any constant pools that were at the end
127 InConstantPool = false;
128 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
131 void ARMAsmPrinter::EmitFunctionEntryLabel() {
132 if (AFI->isThumbFunction()) {
133 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
134 OutStreamer.EmitThumbFunc(CurrentFnSym);
137 OutStreamer.EmitLabel(CurrentFnSym);
140 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
141 uint64_t Size = TM.getDataLayout()->getTypeAllocSize(CV->getType());
142 assert(Size && "C++ constructor pointer had zero size!");
144 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
145 assert(GV && "C++ constructor pointer was not a GlobalValue!");
147 const MCExpr *E = MCSymbolRefExpr::Create(getSymbol(GV),
148 (Subtarget->isTargetELF()
149 ? MCSymbolRefExpr::VK_ARM_TARGET1
150 : MCSymbolRefExpr::VK_None),
153 OutStreamer.EmitValue(E, Size);
156 /// runOnMachineFunction - This uses the EmitInstruction()
157 /// method to print assembly for each instruction.
159 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
160 AFI = MF.getInfo<ARMFunctionInfo>();
161 MCP = MF.getConstantPool();
163 return AsmPrinter::runOnMachineFunction(MF);
166 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
167 raw_ostream &O, const char *Modifier) {
168 const MachineOperand &MO = MI->getOperand(OpNum);
169 unsigned TF = MO.getTargetFlags();
171 switch (MO.getType()) {
172 default: llvm_unreachable("<unknown operand type>");
173 case MachineOperand::MO_Register: {
174 unsigned Reg = MO.getReg();
175 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
176 assert(!MO.getSubReg() && "Subregs should be eliminated!");
177 if(ARM::GPRPairRegClass.contains(Reg)) {
178 const MachineFunction &MF = *MI->getParent()->getParent();
179 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
180 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
182 O << ARMInstPrinter::getRegisterName(Reg);
185 case MachineOperand::MO_Immediate: {
186 int64_t Imm = MO.getImm();
188 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
189 (TF == ARMII::MO_LO16))
191 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
192 (TF == ARMII::MO_HI16))
197 case MachineOperand::MO_MachineBasicBlock:
198 O << *MO.getMBB()->getSymbol();
200 case MachineOperand::MO_GlobalAddress: {
201 const GlobalValue *GV = MO.getGlobal();
202 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
203 (TF & ARMII::MO_LO16))
205 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
206 (TF & ARMII::MO_HI16))
210 printOffset(MO.getOffset(), O);
211 if (TF == ARMII::MO_PLT)
215 case MachineOperand::MO_ConstantPoolIndex:
216 O << *GetCPISymbol(MO.getIndex());
221 //===--------------------------------------------------------------------===//
223 MCSymbol *ARMAsmPrinter::
224 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
225 const DataLayout *DL = TM.getDataLayout();
226 SmallString<60> Name;
227 raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "JTI"
228 << getFunctionNumber() << '_' << uid << '_' << uid2;
229 return OutContext.GetOrCreateSymbol(Name.str());
233 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const {
234 const DataLayout *DL = TM.getDataLayout();
235 SmallString<60> Name;
236 raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "SJLJEH"
237 << getFunctionNumber();
238 return OutContext.GetOrCreateSymbol(Name.str());
241 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
242 unsigned AsmVariant, const char *ExtraCode,
244 // Does this asm operand have a single letter operand modifier?
245 if (ExtraCode && ExtraCode[0]) {
246 if (ExtraCode[1] != 0) return true; // Unknown modifier.
248 switch (ExtraCode[0]) {
250 // See if this is a generic print operand
251 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
252 case 'a': // Print as a memory address.
253 if (MI->getOperand(OpNum).isReg()) {
255 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
260 case 'c': // Don't print "#" before an immediate operand.
261 if (!MI->getOperand(OpNum).isImm())
263 O << MI->getOperand(OpNum).getImm();
265 case 'P': // Print a VFP double precision register.
266 case 'q': // Print a NEON quad precision register.
267 printOperand(MI, OpNum, O);
269 case 'y': // Print a VFP single precision register as indexed double.
270 if (MI->getOperand(OpNum).isReg()) {
271 unsigned Reg = MI->getOperand(OpNum).getReg();
272 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
273 // Find the 'd' register that has this 's' register as a sub-register,
274 // and determine the lane number.
275 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
276 if (!ARM::DPRRegClass.contains(*SR))
278 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
279 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
284 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
285 if (!MI->getOperand(OpNum).isImm())
287 O << ~(MI->getOperand(OpNum).getImm());
289 case 'L': // The low 16 bits of an immediate constant.
290 if (!MI->getOperand(OpNum).isImm())
292 O << (MI->getOperand(OpNum).getImm() & 0xffff);
294 case 'M': { // A register range suitable for LDM/STM.
295 if (!MI->getOperand(OpNum).isReg())
297 const MachineOperand &MO = MI->getOperand(OpNum);
298 unsigned RegBegin = MO.getReg();
299 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
300 // already got the operands in registers that are operands to the
301 // inline asm statement.
303 if (ARM::GPRPairRegClass.contains(RegBegin)) {
304 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
305 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
306 O << ARMInstPrinter::getRegisterName(Reg0) << ", ";;
307 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
309 O << ARMInstPrinter::getRegisterName(RegBegin);
311 // FIXME: The register allocator not only may not have given us the
312 // registers in sequence, but may not be in ascending registers. This
313 // will require changes in the register allocator that'll need to be
314 // propagated down here if the operands change.
315 unsigned RegOps = OpNum + 1;
316 while (MI->getOperand(RegOps).isReg()) {
318 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
326 case 'R': // The most significant register of a pair.
327 case 'Q': { // The least significant register of a pair.
330 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
331 if (!FlagsOP.isImm())
333 unsigned Flags = FlagsOP.getImm();
335 // This operand may not be the one that actually provides the register. If
336 // it's tied to a previous one then we should refer instead to that one
337 // for registers and their classes.
339 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
340 for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
341 unsigned OpFlags = MI->getOperand(OpNum).getImm();
342 OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
344 Flags = MI->getOperand(OpNum).getImm();
346 // Later code expects OpNum to be pointing at the register rather than
351 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
353 InlineAsm::hasRegClassConstraint(Flags, RC);
354 if (RC == ARM::GPRPairRegClassID) {
357 const MachineOperand &MO = MI->getOperand(OpNum);
360 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
361 unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
362 ARM::gsub_0 : ARM::gsub_1);
363 O << ARMInstPrinter::getRegisterName(Reg);
368 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
369 if (RegOp >= MI->getNumOperands())
371 const MachineOperand &MO = MI->getOperand(RegOp);
374 unsigned Reg = MO.getReg();
375 O << ARMInstPrinter::getRegisterName(Reg);
379 case 'e': // The low doubleword register of a NEON quad register.
380 case 'f': { // The high doubleword register of a NEON quad register.
381 if (!MI->getOperand(OpNum).isReg())
383 unsigned Reg = MI->getOperand(OpNum).getReg();
384 if (!ARM::QPRRegClass.contains(Reg))
386 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
387 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
388 ARM::dsub_0 : ARM::dsub_1);
389 O << ARMInstPrinter::getRegisterName(SubReg);
393 // This modifier is not yet supported.
394 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
396 case 'H': { // The highest-numbered register of a pair.
397 const MachineOperand &MO = MI->getOperand(OpNum);
400 const MachineFunction &MF = *MI->getParent()->getParent();
401 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
402 unsigned Reg = MO.getReg();
403 if(!ARM::GPRPairRegClass.contains(Reg))
405 Reg = TRI->getSubReg(Reg, ARM::gsub_1);
406 O << ARMInstPrinter::getRegisterName(Reg);
412 printOperand(MI, OpNum, O);
416 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
417 unsigned OpNum, unsigned AsmVariant,
418 const char *ExtraCode,
420 // Does this asm operand have a single letter operand modifier?
421 if (ExtraCode && ExtraCode[0]) {
422 if (ExtraCode[1] != 0) return true; // Unknown modifier.
424 switch (ExtraCode[0]) {
425 case 'A': // A memory operand for a VLD1/VST1 instruction.
426 default: return true; // Unknown modifier.
427 case 'm': // The base register of a memory operand.
428 if (!MI->getOperand(OpNum).isReg())
430 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
435 const MachineOperand &MO = MI->getOperand(OpNum);
436 assert(MO.isReg() && "unexpected inline asm memory operand");
437 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
441 static bool isThumb(const MCSubtargetInfo& STI) {
442 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
445 void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
446 const MCSubtargetInfo *EndInfo) const {
447 // If either end mode is unknown (EndInfo == NULL) or different than
448 // the start mode, then restore the start mode.
449 const bool WasThumb = isThumb(StartInfo);
450 if (EndInfo == NULL || WasThumb != isThumb(*EndInfo)) {
451 OutStreamer.EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
455 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
456 if (Subtarget->isTargetMachO()) {
457 Reloc::Model RelocM = TM.getRelocationModel();
458 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
459 // Declare all the text sections up front (before the DWARF sections
460 // emitted by AsmPrinter::doInitialization) so the assembler will keep
461 // them together at the beginning of the object file. This helps
462 // avoid out-of-range branches that are due a fundamental limitation of
463 // the way symbol offsets are encoded with the current Darwin ARM
465 const TargetLoweringObjectFileMachO &TLOFMacho =
466 static_cast<const TargetLoweringObjectFileMachO &>(
467 getObjFileLowering());
469 // Collect the set of sections our functions will go into.
470 SetVector<const MCSection *, SmallVector<const MCSection *, 8>,
471 SmallPtrSet<const MCSection *, 8> > TextSections;
472 // Default text section comes first.
473 TextSections.insert(TLOFMacho.getTextSection());
474 // Now any user defined text sections from function attributes.
475 for (Module::iterator F = M.begin(), e = M.end(); F != e; ++F)
476 if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage())
477 TextSections.insert(TLOFMacho.SectionForGlobal(F, *Mang, TM));
478 // Now the coalescable sections.
479 TextSections.insert(TLOFMacho.getTextCoalSection());
480 TextSections.insert(TLOFMacho.getConstTextCoalSection());
482 // Emit the sections in the .s file header to fix the order.
483 for (unsigned i = 0, e = TextSections.size(); i != e; ++i)
484 OutStreamer.SwitchSection(TextSections[i]);
486 if (RelocM == Reloc::DynamicNoPIC) {
487 const MCSection *sect =
488 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
489 MCSectionMachO::S_SYMBOL_STUBS,
490 12, SectionKind::getText());
491 OutStreamer.SwitchSection(sect);
493 const MCSection *sect =
494 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
495 MCSectionMachO::S_SYMBOL_STUBS,
496 16, SectionKind::getText());
497 OutStreamer.SwitchSection(sect);
499 const MCSection *StaticInitSect =
500 OutContext.getMachOSection("__TEXT", "__StaticInit",
501 MCSectionMachO::S_REGULAR |
502 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
503 SectionKind::getText());
504 OutStreamer.SwitchSection(StaticInitSect);
507 // Compiling with debug info should not affect the code
508 // generation. Ensure the cstring section comes before the
509 // optional __DWARF secion. Otherwise, PC-relative loads would
510 // have to use different instruction sequences at "-g" in order to
511 // reach global data in the same object file.
512 OutStreamer.SwitchSection(getObjFileLowering().getCStringSection());
515 // Use unified assembler syntax.
516 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
518 // Emit ARM Build Attributes
519 if (Subtarget->isTargetELF())
524 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
525 if (Subtarget->isTargetMachO()) {
526 // All darwin targets use mach-o.
527 const TargetLoweringObjectFileMachO &TLOFMacho =
528 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
529 MachineModuleInfoMachO &MMIMacho =
530 MMI->getObjFileInfo<MachineModuleInfoMachO>();
532 // Output non-lazy-pointers for external and common global variables.
533 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
535 if (!Stubs.empty()) {
536 // Switch with ".non_lazy_symbol_pointer" directive.
537 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
539 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
541 OutStreamer.EmitLabel(Stubs[i].first);
542 // .indirect_symbol _foo
543 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
544 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
547 // External to current translation unit.
548 OutStreamer.EmitIntValue(0, 4/*size*/);
550 // Internal to current translation unit.
552 // When we place the LSDA into the TEXT section, the type info
553 // pointers need to be indirect and pc-rel. We accomplish this by
554 // using NLPs; however, sometimes the types are local to the file.
555 // We need to fill in the value for the NLP in those cases.
556 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
562 OutStreamer.AddBlankLine();
565 Stubs = MMIMacho.GetHiddenGVStubList();
566 if (!Stubs.empty()) {
567 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
569 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
571 OutStreamer.EmitLabel(Stubs[i].first);
573 OutStreamer.EmitValue(MCSymbolRefExpr::
574 Create(Stubs[i].second.getPointer(),
580 OutStreamer.AddBlankLine();
583 // Funny Darwin hack: This flag tells the linker that no global symbols
584 // contain code that falls through to other global symbols (e.g. the obvious
585 // implementation of multiple entry points). If this doesn't occur, the
586 // linker can safely perform dead code stripping. Since LLVM never
587 // generates code that does this, it is always safe to set.
588 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
592 //===----------------------------------------------------------------------===//
593 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
595 // The following seem like one-off assembler flags, but they actually need
596 // to appear in the .ARM.attributes section in ELF.
597 // Instead of subclassing the MCELFStreamer, we do the work here.
599 static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
600 const ARMSubtarget *Subtarget) {
602 return ARMBuildAttrs::v5TEJ;
604 if (Subtarget->hasV8Ops())
605 return ARMBuildAttrs::v8;
606 else if (Subtarget->hasV7Ops()) {
607 if (Subtarget->isMClass() && Subtarget->hasThumb2DSP())
608 return ARMBuildAttrs::v7E_M;
609 return ARMBuildAttrs::v7;
610 } else if (Subtarget->hasV6T2Ops())
611 return ARMBuildAttrs::v6T2;
612 else if (Subtarget->hasV6MOps())
613 return ARMBuildAttrs::v6S_M;
614 else if (Subtarget->hasV6Ops())
615 return ARMBuildAttrs::v6;
616 else if (Subtarget->hasV5TEOps())
617 return ARMBuildAttrs::v5TE;
618 else if (Subtarget->hasV5TOps())
619 return ARMBuildAttrs::v5T;
620 else if (Subtarget->hasV4TOps())
621 return ARMBuildAttrs::v4T;
623 return ARMBuildAttrs::v4;
626 void ARMAsmPrinter::emitAttributes() {
627 MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
628 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
630 ATS.switchVendor("aeabi");
632 std::string CPUString = Subtarget->getCPUString();
634 // FIXME: remove krait check when GNU tools support krait cpu
635 if (CPUString != "generic" && CPUString != "krait")
636 ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
638 ATS.emitAttribute(ARMBuildAttrs::CPU_arch,
639 getArchForCPU(CPUString, Subtarget));
641 // Tag_CPU_arch_profile must have the default value of 0 when "Architecture
642 // profile is not applicable (e.g. pre v7, or cross-profile code)".
643 if (Subtarget->hasV7Ops()) {
644 if (Subtarget->isAClass()) {
645 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
646 ARMBuildAttrs::ApplicationProfile);
647 } else if (Subtarget->isRClass()) {
648 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
649 ARMBuildAttrs::RealTimeProfile);
650 } else if (Subtarget->isMClass()) {
651 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
652 ARMBuildAttrs::MicroControllerProfile);
656 ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use, Subtarget->hasARMOps() ?
657 ARMBuildAttrs::Allowed : ARMBuildAttrs::Not_Allowed);
658 if (Subtarget->isThumb1Only()) {
659 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
660 ARMBuildAttrs::Allowed);
661 } else if (Subtarget->hasThumb2()) {
662 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
663 ARMBuildAttrs::AllowThumb32);
666 if (Subtarget->hasNEON()) {
667 /* NEON is not exactly a VFP architecture, but GAS emit one of
668 * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
669 if (Subtarget->hasFPARMv8()) {
670 if (Subtarget->hasCrypto())
671 ATS.emitFPU(ARM::CRYPTO_NEON_FP_ARMV8);
673 ATS.emitFPU(ARM::NEON_FP_ARMV8);
675 else if (Subtarget->hasVFP4())
676 ATS.emitFPU(ARM::NEON_VFPV4);
678 ATS.emitFPU(ARM::NEON);
679 // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
680 if (Subtarget->hasV8Ops())
681 ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
682 ARMBuildAttrs::AllowNeonARMv8);
684 if (Subtarget->hasFPARMv8())
685 ATS.emitFPU(ARM::FP_ARMV8);
686 else if (Subtarget->hasVFP4())
687 ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV4_D16 : ARM::VFPV4);
688 else if (Subtarget->hasVFP3())
689 ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV3_D16 : ARM::VFPV3);
690 else if (Subtarget->hasVFP2())
691 ATS.emitFPU(ARM::VFPV2);
694 // Signal various FP modes.
695 if (!TM.Options.UnsafeFPMath) {
696 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal, ARMBuildAttrs::Allowed);
697 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
698 ARMBuildAttrs::Allowed);
701 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
702 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
703 ARMBuildAttrs::Allowed);
705 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
706 ARMBuildAttrs::AllowIEE754);
708 // FIXME: add more flags to ARMBuildAttributes.h
709 // 8-bytes alignment stuff.
710 ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
711 ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
713 // ABI_HardFP_use attribute to indicate single precision FP.
714 if (Subtarget->isFPOnlySP())
715 ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
716 ARMBuildAttrs::HardFPSinglePrecision);
718 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
719 if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
720 ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
722 // FIXME: Should we signal R9 usage?
724 if (Subtarget->hasFP16())
725 ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
727 if (Subtarget->hasMPExtension())
728 ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
730 // Hardware divide in ARM mode is part of base arch, starting from ARMv8.
731 // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
732 // It is not possible to produce DisallowDIV: if hwdiv is present in the base
733 // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
734 // AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
735 // otherwise, the default value (AllowDIVIfExists) applies.
736 if (Subtarget->hasDivideInARMMode() && !Subtarget->hasV8Ops())
737 ATS.emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
739 if (Subtarget->hasTrustZone() && Subtarget->hasVirtualization())
740 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
741 ARMBuildAttrs::AllowTZVirtualization);
742 else if (Subtarget->hasTrustZone())
743 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
744 ARMBuildAttrs::AllowTZ);
745 else if (Subtarget->hasVirtualization())
746 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
747 ARMBuildAttrs::AllowVirtualization);
749 ATS.finishAttributeSection();
752 //===----------------------------------------------------------------------===//
754 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
755 unsigned LabelId, MCContext &Ctx) {
757 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
758 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
762 static MCSymbolRefExpr::VariantKind
763 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
765 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
766 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_TLSGD;
767 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_TPOFF;
768 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_GOTTPOFF;
769 case ARMCP::GOT: return MCSymbolRefExpr::VK_GOT;
770 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_GOTOFF;
772 llvm_unreachable("Invalid ARMCPModifier!");
775 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
776 unsigned char TargetFlags) {
777 bool isIndirect = Subtarget->isTargetMachO() &&
778 (TargetFlags & ARMII::MO_NONLAZY) &&
779 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
781 return getSymbol(GV);
783 // FIXME: Remove this when Darwin transition to @GOT like syntax.
784 MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
785 MachineModuleInfoMachO &MMIMachO =
786 MMI->getObjFileInfo<MachineModuleInfoMachO>();
787 MachineModuleInfoImpl::StubValueTy &StubSym =
788 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
789 MMIMachO.getGVStubEntry(MCSym);
790 if (StubSym.getPointer() == 0)
791 StubSym = MachineModuleInfoImpl::
792 StubValueTy(getSymbol(GV), !GV->hasInternalLinkage());
797 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
798 const DataLayout *DL = TM.getDataLayout();
799 int Size = TM.getDataLayout()->getTypeAllocSize(MCPV->getType());
801 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
804 if (ACPV->isLSDA()) {
805 SmallString<128> Str;
806 raw_svector_ostream OS(Str);
807 OS << DL->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
808 MCSym = OutContext.GetOrCreateSymbol(OS.str());
809 } else if (ACPV->isBlockAddress()) {
810 const BlockAddress *BA =
811 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
812 MCSym = GetBlockAddressSymbol(BA);
813 } else if (ACPV->isGlobalValue()) {
814 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
816 // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
817 // flag the global as MO_NONLAZY.
818 unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
819 MCSym = GetARMGVSymbol(GV, TF);
820 } else if (ACPV->isMachineBasicBlock()) {
821 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
822 MCSym = MBB->getSymbol();
824 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
825 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
826 MCSym = GetExternalSymbolSymbol(Sym);
829 // Create an MCSymbol for the reference.
831 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
834 if (ACPV->getPCAdjustment()) {
835 MCSymbol *PCLabel = getPICLabel(DL->getPrivateGlobalPrefix(),
839 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
841 MCBinaryExpr::CreateAdd(PCRelExpr,
842 MCConstantExpr::Create(ACPV->getPCAdjustment(),
845 if (ACPV->mustAddCurrentAddress()) {
846 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
847 // label, so just emit a local label end reference that instead.
848 MCSymbol *DotSym = OutContext.CreateTempSymbol();
849 OutStreamer.EmitLabel(DotSym);
850 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
851 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
853 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
855 OutStreamer.EmitValue(Expr, Size);
858 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
859 unsigned Opcode = MI->getOpcode();
861 if (Opcode == ARM::BR_JTadd)
863 else if (Opcode == ARM::BR_JTm)
866 const MachineOperand &MO1 = MI->getOperand(OpNum);
867 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
868 unsigned JTI = MO1.getIndex();
870 // Emit a label for the jump table.
871 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
872 OutStreamer.EmitLabel(JTISymbol);
874 // Mark the jump table as data-in-code.
875 OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
877 // Emit each entry of the table.
878 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
879 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
880 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
882 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
883 MachineBasicBlock *MBB = JTBBs[i];
884 // Construct an MCExpr for the entry. We want a value of the form:
885 // (BasicBlockAddr - TableBeginAddr)
887 // For example, a table with entries jumping to basic blocks BB0 and BB1
890 // .word (LBB0 - LJTI_0_0)
891 // .word (LBB1 - LJTI_0_0)
892 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
894 if (TM.getRelocationModel() == Reloc::PIC_)
895 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
898 // If we're generating a table of Thumb addresses in static relocation
899 // model, we need to add one to keep interworking correctly.
900 else if (AFI->isThumbFunction())
901 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
903 OutStreamer.EmitValue(Expr, 4);
905 // Mark the end of jump table data-in-code region.
906 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
909 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
910 unsigned Opcode = MI->getOpcode();
911 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
912 const MachineOperand &MO1 = MI->getOperand(OpNum);
913 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
914 unsigned JTI = MO1.getIndex();
916 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
917 OutStreamer.EmitLabel(JTISymbol);
919 // Emit each entry of the table.
920 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
921 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
922 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
923 unsigned OffsetWidth = 4;
924 if (MI->getOpcode() == ARM::t2TBB_JT) {
926 // Mark the jump table as data-in-code.
927 OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
928 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
930 // Mark the jump table as data-in-code.
931 OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
934 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
935 MachineBasicBlock *MBB = JTBBs[i];
936 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
938 // If this isn't a TBB or TBH, the entries are direct branch instructions.
939 if (OffsetWidth == 4) {
940 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2B)
941 .addExpr(MBBSymbolExpr)
946 // Otherwise it's an offset from the dispatch instruction. Construct an
947 // MCExpr for the entry. We want a value of the form:
948 // (BasicBlockAddr - TableBeginAddr) / 2
950 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
953 // .byte (LBB0 - LJTI_0_0) / 2
954 // .byte (LBB1 - LJTI_0_0) / 2
956 MCBinaryExpr::CreateSub(MBBSymbolExpr,
957 MCSymbolRefExpr::Create(JTISymbol, OutContext),
959 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
961 OutStreamer.EmitValue(Expr, OffsetWidth);
963 // Mark the end of jump table data-in-code region. 32-bit offsets use
964 // actual branch instructions here, so we don't mark those as a data-region
966 if (OffsetWidth != 4)
967 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
970 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
971 assert(MI->getFlag(MachineInstr::FrameSetup) &&
972 "Only instruction which are involved into frame setup code are allowed");
974 MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
975 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
976 const MachineFunction &MF = *MI->getParent()->getParent();
977 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
978 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
980 unsigned FramePtr = RegInfo->getFrameRegister(MF);
981 unsigned Opc = MI->getOpcode();
982 unsigned SrcReg, DstReg;
984 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
985 // Two special cases:
986 // 1) tPUSH does not have src/dst regs.
987 // 2) for Thumb1 code we sometimes materialize the constant via constpool
988 // load. Yes, this is pretty fragile, but for now I don't see better
990 SrcReg = DstReg = ARM::SP;
992 SrcReg = MI->getOperand(1).getReg();
993 DstReg = MI->getOperand(0).getReg();
996 // Try to figure out the unwinding opcode out of src / dst regs.
997 if (MI->mayStore()) {
999 assert(DstReg == ARM::SP &&
1000 "Only stack pointer as a destination reg is supported");
1002 SmallVector<unsigned, 4> RegList;
1003 // Skip src & dst reg, and pred ops.
1004 unsigned StartOp = 2 + 2;
1005 // Use all the operands.
1006 unsigned NumOffset = 0;
1011 llvm_unreachable("Unsupported opcode for unwinding information");
1013 // Special case here: no src & dst reg, but two extra imp ops.
1014 StartOp = 2; NumOffset = 2;
1015 case ARM::STMDB_UPD:
1016 case ARM::t2STMDB_UPD:
1017 case ARM::VSTMDDB_UPD:
1018 assert(SrcReg == ARM::SP &&
1019 "Only stack pointer as a source reg is supported");
1020 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1022 const MachineOperand &MO = MI->getOperand(i);
1023 // Actually, there should never be any impdef stuff here. Skip it
1024 // temporary to workaround PR11902.
1025 if (MO.isImplicit())
1027 RegList.push_back(MO.getReg());
1030 case ARM::STR_PRE_IMM:
1031 case ARM::STR_PRE_REG:
1032 case ARM::t2STR_PRE:
1033 assert(MI->getOperand(2).getReg() == ARM::SP &&
1034 "Only stack pointer as a source reg is supported");
1035 RegList.push_back(SrcReg);
1038 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1040 // Changes of stack / frame pointer.
1041 if (SrcReg == ARM::SP) {
1046 llvm_unreachable("Unsupported opcode for unwinding information");
1052 Offset = -MI->getOperand(2).getImm();
1056 Offset = MI->getOperand(2).getImm();
1059 Offset = MI->getOperand(2).getImm()*4;
1063 Offset = -MI->getOperand(2).getImm()*4;
1065 case ARM::tLDRpci: {
1066 // Grab the constpool index and check, whether it corresponds to
1067 // original or cloned constpool entry.
1068 unsigned CPI = MI->getOperand(1).getIndex();
1069 const MachineConstantPool *MCP = MF.getConstantPool();
1070 if (CPI >= MCP->getConstants().size())
1071 CPI = AFI.getOriginalCPIdx(CPI);
1072 assert(CPI != -1U && "Invalid constpool index");
1074 // Derive the actual offset.
1075 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1076 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1077 // FIXME: Check for user, it should be "add" instruction!
1078 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1083 if (DstReg == FramePtr && FramePtr != ARM::SP)
1084 // Set-up of the frame pointer. Positive values correspond to "add"
1086 ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1087 else if (DstReg == ARM::SP) {
1088 // Change of SP by an offset. Positive values correspond to "sub"
1090 ATS.emitPad(Offset);
1092 // Move of SP to a register. Positive values correspond to an "add"
1094 ATS.emitMovSP(DstReg, -Offset);
1096 } else if (DstReg == ARM::SP) {
1098 llvm_unreachable("Unsupported opcode for unwinding information");
1102 llvm_unreachable("Unsupported opcode for unwinding information");
1107 // Simple pseudo-instructions have their lowering (with expansion to real
1108 // instructions) auto-generated.
1109 #include "ARMGenMCPseudoLowering.inc"
1111 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1112 const DataLayout *DL = TM.getDataLayout();
1114 // If we just ended a constant pool, mark it as such.
1115 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1116 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1117 InConstantPool = false;
1120 // Emit unwinding stuff for frame-related instructions
1121 if (Subtarget->isTargetEHABICompatible() &&
1122 MI->getFlag(MachineInstr::FrameSetup))
1123 EmitUnwindingInstruction(MI);
1125 // Do any auto-generated pseudo lowerings.
1126 if (emitPseudoExpansionLowering(OutStreamer, MI))
1129 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1130 "Pseudo flag setting opcode should be expanded early");
1132 // Check for manual lowerings.
1133 unsigned Opc = MI->getOpcode();
1135 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1136 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1138 case ARM::tLEApcrel:
1139 case ARM::t2LEApcrel: {
1140 // FIXME: Need to also handle globals and externals
1141 MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1142 EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
1143 ARM::t2LEApcrel ? ARM::t2ADR
1144 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1146 .addReg(MI->getOperand(0).getReg())
1147 .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
1148 // Add predicate operands.
1149 .addImm(MI->getOperand(2).getImm())
1150 .addReg(MI->getOperand(3).getReg()));
1153 case ARM::LEApcrelJT:
1154 case ARM::tLEApcrelJT:
1155 case ARM::t2LEApcrelJT: {
1156 MCSymbol *JTIPICSymbol =
1157 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1158 MI->getOperand(2).getImm());
1159 EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
1160 ARM::t2LEApcrelJT ? ARM::t2ADR
1161 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1163 .addReg(MI->getOperand(0).getReg())
1164 .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
1165 // Add predicate operands.
1166 .addImm(MI->getOperand(3).getImm())
1167 .addReg(MI->getOperand(4).getReg()));
1170 // Darwin call instructions are just normal call instructions with different
1171 // clobber semantics (they clobber R9).
1172 case ARM::BX_CALL: {
1173 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1176 // Add predicate operands.
1179 // Add 's' bit operand (always reg0 for this)
1182 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
1183 .addReg(MI->getOperand(0).getReg()));
1186 case ARM::tBX_CALL: {
1187 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
1190 // Add predicate operands.
1194 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
1195 .addReg(MI->getOperand(0).getReg())
1196 // Add predicate operands.
1201 case ARM::BMOVPCRX_CALL: {
1202 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1205 // Add predicate operands.
1208 // Add 's' bit operand (always reg0 for this)
1211 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1213 .addReg(MI->getOperand(0).getReg())
1214 // Add predicate operands.
1217 // Add 's' bit operand (always reg0 for this)
1221 case ARM::BMOVPCB_CALL: {
1222 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1225 // Add predicate operands.
1228 // Add 's' bit operand (always reg0 for this)
1231 const GlobalValue *GV = MI->getOperand(0).getGlobal();
1232 MCSymbol *GVSym = getSymbol(GV);
1233 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1234 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::Bcc)
1236 // Add predicate operands.
1241 case ARM::MOVi16_ga_pcrel:
1242 case ARM::t2MOVi16_ga_pcrel: {
1244 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1245 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1247 unsigned TF = MI->getOperand(1).getTargetFlags();
1248 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1249 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1250 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1252 MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
1253 getFunctionNumber(),
1254 MI->getOperand(2).getImm(), OutContext);
1255 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1256 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1257 const MCExpr *PCRelExpr =
1258 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1259 MCBinaryExpr::CreateAdd(LabelSymExpr,
1260 MCConstantExpr::Create(PCAdj, OutContext),
1261 OutContext), OutContext), OutContext);
1262 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1264 // Add predicate operands.
1265 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1266 TmpInst.addOperand(MCOperand::CreateReg(0));
1267 // Add 's' bit operand (always reg0 for this)
1268 TmpInst.addOperand(MCOperand::CreateReg(0));
1269 EmitToStreamer(OutStreamer, TmpInst);
1272 case ARM::MOVTi16_ga_pcrel:
1273 case ARM::t2MOVTi16_ga_pcrel: {
1275 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1276 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1277 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1278 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1280 unsigned TF = MI->getOperand(2).getTargetFlags();
1281 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1282 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1283 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1285 MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
1286 getFunctionNumber(),
1287 MI->getOperand(3).getImm(), OutContext);
1288 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1289 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1290 const MCExpr *PCRelExpr =
1291 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1292 MCBinaryExpr::CreateAdd(LabelSymExpr,
1293 MCConstantExpr::Create(PCAdj, OutContext),
1294 OutContext), OutContext), OutContext);
1295 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1296 // Add predicate operands.
1297 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1298 TmpInst.addOperand(MCOperand::CreateReg(0));
1299 // Add 's' bit operand (always reg0 for this)
1300 TmpInst.addOperand(MCOperand::CreateReg(0));
1301 EmitToStreamer(OutStreamer, TmpInst);
1304 case ARM::tPICADD: {
1305 // This is a pseudo op for a label + instruction sequence, which looks like:
1308 // This adds the address of LPC0 to r0.
1311 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1312 getFunctionNumber(), MI->getOperand(2).getImm(),
1315 // Form and emit the add.
1316 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDhirr)
1317 .addReg(MI->getOperand(0).getReg())
1318 .addReg(MI->getOperand(0).getReg())
1320 // Add predicate operands.
1326 // This is a pseudo op for a label + instruction sequence, which looks like:
1329 // This adds the address of LPC0 to r0.
1332 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1333 getFunctionNumber(), MI->getOperand(2).getImm(),
1336 // Form and emit the add.
1337 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
1338 .addReg(MI->getOperand(0).getReg())
1340 .addReg(MI->getOperand(1).getReg())
1341 // Add predicate operands.
1342 .addImm(MI->getOperand(3).getImm())
1343 .addReg(MI->getOperand(4).getReg())
1344 // Add 's' bit operand (always reg0 for this)
1355 case ARM::PICLDRSH: {
1356 // This is a pseudo op for a label + instruction sequence, which looks like:
1359 // The LCP0 label is referenced by a constant pool entry in order to get
1360 // a PC-relative address at the ldr instruction.
1363 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1364 getFunctionNumber(), MI->getOperand(2).getImm(),
1367 // Form and emit the load
1369 switch (MI->getOpcode()) {
1371 llvm_unreachable("Unexpected opcode!");
1372 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1373 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1374 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1375 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1376 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1377 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1378 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1379 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1381 EmitToStreamer(OutStreamer, MCInstBuilder(Opcode)
1382 .addReg(MI->getOperand(0).getReg())
1384 .addReg(MI->getOperand(1).getReg())
1386 // Add predicate operands.
1387 .addImm(MI->getOperand(3).getImm())
1388 .addReg(MI->getOperand(4).getReg()));
1392 case ARM::CONSTPOOL_ENTRY: {
1393 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1394 /// in the function. The first operand is the ID# for this instruction, the
1395 /// second is the index into the MachineConstantPool that this is, the third
1396 /// is the size in bytes of this constant pool entry.
1397 /// The required alignment is specified on the basic block holding this MI.
1398 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1399 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1401 // If this is the first entry of the pool, mark it.
1402 if (!InConstantPool) {
1403 OutStreamer.EmitDataRegion(MCDR_DataRegion);
1404 InConstantPool = true;
1407 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1409 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1410 if (MCPE.isMachineConstantPoolEntry())
1411 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1413 EmitGlobalConstant(MCPE.Val.ConstVal);
1416 case ARM::t2BR_JT: {
1417 // Lower and emit the instruction itself, then the jump table following it.
1418 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
1420 .addReg(MI->getOperand(0).getReg())
1421 // Add predicate operands.
1425 // Output the data for the jump table itself
1429 case ARM::t2TBB_JT: {
1430 // Lower and emit the instruction itself, then the jump table following it.
1431 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBB)
1433 .addReg(MI->getOperand(0).getReg())
1434 // Add predicate operands.
1438 // Output the data for the jump table itself
1440 // Make sure the next instruction is 2-byte aligned.
1444 case ARM::t2TBH_JT: {
1445 // Lower and emit the instruction itself, then the jump table following it.
1446 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBH)
1448 .addReg(MI->getOperand(0).getReg())
1449 // Add predicate operands.
1453 // Output the data for the jump table itself
1459 // Lower and emit the instruction itself, then the jump table following it.
1462 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1463 ARM::MOVr : ARM::tMOVr;
1464 TmpInst.setOpcode(Opc);
1465 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1466 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1467 // Add predicate operands.
1468 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1469 TmpInst.addOperand(MCOperand::CreateReg(0));
1470 // Add 's' bit operand (always reg0 for this)
1471 if (Opc == ARM::MOVr)
1472 TmpInst.addOperand(MCOperand::CreateReg(0));
1473 EmitToStreamer(OutStreamer, TmpInst);
1475 // Make sure the Thumb jump table is 4-byte aligned.
1476 if (Opc == ARM::tMOVr)
1479 // Output the data for the jump table itself
1484 // Lower and emit the instruction itself, then the jump table following it.
1487 if (MI->getOperand(1).getReg() == 0) {
1489 TmpInst.setOpcode(ARM::LDRi12);
1490 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1491 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1492 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1494 TmpInst.setOpcode(ARM::LDRrs);
1495 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1496 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1497 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1498 TmpInst.addOperand(MCOperand::CreateImm(0));
1500 // Add predicate operands.
1501 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1502 TmpInst.addOperand(MCOperand::CreateReg(0));
1503 EmitToStreamer(OutStreamer, TmpInst);
1505 // Output the data for the jump table itself
1509 case ARM::BR_JTadd: {
1510 // Lower and emit the instruction itself, then the jump table following it.
1511 // add pc, target, idx
1512 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
1514 .addReg(MI->getOperand(0).getReg())
1515 .addReg(MI->getOperand(1).getReg())
1516 // Add predicate operands.
1519 // Add 's' bit operand (always reg0 for this)
1522 // Output the data for the jump table itself
1527 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1528 // FIXME: Remove this special case when they do.
1529 if (!Subtarget->isTargetMachO()) {
1530 //.long 0xe7ffdefe @ trap
1531 uint32_t Val = 0xe7ffdefeUL;
1532 OutStreamer.AddComment("trap");
1533 OutStreamer.EmitIntValue(Val, 4);
1538 case ARM::TRAPNaCl: {
1539 //.long 0xe7fedef0 @ trap
1540 uint32_t Val = 0xe7fedef0UL;
1541 OutStreamer.AddComment("trap");
1542 OutStreamer.EmitIntValue(Val, 4);
1546 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1547 // FIXME: Remove this special case when they do.
1548 if (!Subtarget->isTargetMachO()) {
1549 //.short 57086 @ trap
1550 uint16_t Val = 0xdefe;
1551 OutStreamer.AddComment("trap");
1552 OutStreamer.EmitIntValue(Val, 2);
1557 case ARM::t2Int_eh_sjlj_setjmp:
1558 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1559 case ARM::tInt_eh_sjlj_setjmp: {
1560 // Two incoming args: GPR:$src, GPR:$val
1563 // str $val, [$src, #4]
1568 unsigned SrcReg = MI->getOperand(0).getReg();
1569 unsigned ValReg = MI->getOperand(1).getReg();
1570 MCSymbol *Label = GetARMSJLJEHLabel();
1571 OutStreamer.AddComment("eh_setjmp begin");
1572 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
1579 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDi3)
1589 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tSTRi)
1592 // The offset immediate is #4. The operand value is scaled by 4 for the
1593 // tSTR instruction.
1599 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
1607 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1608 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tB)
1609 .addExpr(SymbolExpr)
1613 OutStreamer.AddComment("eh_setjmp end");
1614 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
1622 OutStreamer.EmitLabel(Label);
1626 case ARM::Int_eh_sjlj_setjmp_nofp:
1627 case ARM::Int_eh_sjlj_setjmp: {
1628 // Two incoming args: GPR:$src, GPR:$val
1630 // str $val, [$src, #+4]
1634 unsigned SrcReg = MI->getOperand(0).getReg();
1635 unsigned ValReg = MI->getOperand(1).getReg();
1637 OutStreamer.AddComment("eh_setjmp begin");
1638 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
1645 // 's' bit operand (always reg0 for this).
1648 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::STRi12)
1656 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
1662 // 's' bit operand (always reg0 for this).
1665 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
1672 // 's' bit operand (always reg0 for this).
1675 OutStreamer.AddComment("eh_setjmp end");
1676 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
1682 // 's' bit operand (always reg0 for this).
1686 case ARM::Int_eh_sjlj_longjmp: {
1687 // ldr sp, [$src, #8]
1688 // ldr $scratch, [$src, #4]
1691 unsigned SrcReg = MI->getOperand(0).getReg();
1692 unsigned ScratchReg = MI->getOperand(1).getReg();
1693 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
1701 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
1709 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
1717 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
1724 case ARM::tInt_eh_sjlj_longjmp: {
1725 // ldr $scratch, [$src, #8]
1727 // ldr $scratch, [$src, #4]
1730 unsigned SrcReg = MI->getOperand(0).getReg();
1731 unsigned ScratchReg = MI->getOperand(1).getReg();
1732 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
1735 // The offset immediate is #8. The operand value is scaled by 4 for the
1736 // tLDR instruction.
1742 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
1749 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
1757 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
1765 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
1775 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1777 EmitToStreamer(OutStreamer, TmpInst);
1780 //===----------------------------------------------------------------------===//
1781 // Target Registry Stuff
1782 //===----------------------------------------------------------------------===//
1784 // Force static initialization.
1785 extern "C" void LLVMInitializeARMAsmPrinter() {
1786 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1787 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);