1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #include "ARMAsmPrinter.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMFPUName.h"
19 #include "ARMArchExtName.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMTargetMachine.h"
22 #include "ARMTargetObjectFile.h"
23 #include "InstPrinter/ARMInstPrinter.h"
24 #include "MCTargetDesc/ARMAddressingModes.h"
25 #include "MCTargetDesc/ARMMCExpr.h"
26 #include "llvm/ADT/SetVector.h"
27 #include "llvm/ADT/SmallString.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineJumpTableInfo.h"
30 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/DataLayout.h"
33 #include "llvm/IR/DebugInfo.h"
34 #include "llvm/IR/Mangler.h"
35 #include "llvm/IR/Module.h"
36 #include "llvm/IR/Type.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/MC/MCAssembler.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCELFStreamer.h"
41 #include "llvm/MC/MCInst.h"
42 #include "llvm/MC/MCInstBuilder.h"
43 #include "llvm/MC/MCObjectStreamer.h"
44 #include "llvm/MC/MCSectionMachO.h"
45 #include "llvm/MC/MCStreamer.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/ARMBuildAttributes.h"
48 #include "llvm/Support/COFF.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ELF.h"
52 #include "llvm/Support/ErrorHandling.h"
53 #include "llvm/Support/TargetRegistry.h"
54 #include "llvm/Support/raw_ostream.h"
55 #include "llvm/Target/TargetMachine.h"
59 #define DEBUG_TYPE "asm-printer"
61 ARMAsmPrinter::ARMAsmPrinter(TargetMachine &TM,
62 std::unique_ptr<MCStreamer> Streamer)
63 : AsmPrinter(TM, std::move(Streamer)), AFI(nullptr), MCP(nullptr),
64 InConstantPool(false) {}
66 void ARMAsmPrinter::EmitFunctionBodyEnd() {
67 // Make sure to terminate any constant pools that were at the end
71 InConstantPool = false;
72 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
75 void ARMAsmPrinter::EmitFunctionEntryLabel() {
76 if (AFI->isThumbFunction()) {
77 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
78 OutStreamer.EmitThumbFunc(CurrentFnSym);
81 OutStreamer.EmitLabel(CurrentFnSym);
84 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
85 uint64_t Size = TM.getDataLayout()->getTypeAllocSize(CV->getType());
86 assert(Size && "C++ constructor pointer had zero size!");
88 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
89 assert(GV && "C++ constructor pointer was not a GlobalValue!");
91 const MCExpr *E = MCSymbolRefExpr::Create(GetARMGVSymbol(GV,
93 (Subtarget->isTargetELF()
94 ? MCSymbolRefExpr::VK_ARM_TARGET1
95 : MCSymbolRefExpr::VK_None),
98 OutStreamer.EmitValue(E, Size);
101 /// runOnMachineFunction - This uses the EmitInstruction()
102 /// method to print assembly for each instruction.
104 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
105 AFI = MF.getInfo<ARMFunctionInfo>();
106 MCP = MF.getConstantPool();
107 Subtarget = &MF.getSubtarget<ARMSubtarget>();
109 SetupMachineFunction(MF);
111 if (Subtarget->isTargetCOFF()) {
112 bool Internal = MF.getFunction()->hasInternalLinkage();
113 COFF::SymbolStorageClass Scl = Internal ? COFF::IMAGE_SYM_CLASS_STATIC
114 : COFF::IMAGE_SYM_CLASS_EXTERNAL;
115 int Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
117 OutStreamer.BeginCOFFSymbolDef(CurrentFnSym);
118 OutStreamer.EmitCOFFSymbolStorageClass(Scl);
119 OutStreamer.EmitCOFFSymbolType(Type);
120 OutStreamer.EndCOFFSymbolDef();
123 // Emit the rest of the function body.
126 // If we need V4T thumb mode Register Indirect Jump pads, emit them.
127 // These are created per function, rather than per TU, since it's
128 // relatively easy to exceed the thumb branch range within a TU.
129 if (! ThumbIndirectPads.empty()) {
130 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
132 for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) {
133 OutStreamer.EmitLabel(ThumbIndirectPads[i].second);
134 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
135 .addReg(ThumbIndirectPads[i].first)
136 // Add predicate operands.
140 ThumbIndirectPads.clear();
143 // We didn't modify anything.
147 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
148 raw_ostream &O, const char *Modifier) {
149 const MachineOperand &MO = MI->getOperand(OpNum);
150 unsigned TF = MO.getTargetFlags();
152 switch (MO.getType()) {
153 default: llvm_unreachable("<unknown operand type>");
154 case MachineOperand::MO_Register: {
155 unsigned Reg = MO.getReg();
156 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
157 assert(!MO.getSubReg() && "Subregs should be eliminated!");
158 if(ARM::GPRPairRegClass.contains(Reg)) {
159 const MachineFunction &MF = *MI->getParent()->getParent();
160 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
161 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
163 O << ARMInstPrinter::getRegisterName(Reg);
166 case MachineOperand::MO_Immediate: {
167 int64_t Imm = MO.getImm();
169 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
170 (TF == ARMII::MO_LO16))
172 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
173 (TF == ARMII::MO_HI16))
178 case MachineOperand::MO_MachineBasicBlock:
179 O << *MO.getMBB()->getSymbol();
181 case MachineOperand::MO_GlobalAddress: {
182 const GlobalValue *GV = MO.getGlobal();
183 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
184 (TF & ARMII::MO_LO16))
186 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
187 (TF & ARMII::MO_HI16))
189 O << *GetARMGVSymbol(GV, TF);
191 printOffset(MO.getOffset(), O);
192 if (TF == ARMII::MO_PLT)
196 case MachineOperand::MO_ConstantPoolIndex:
197 O << *GetCPISymbol(MO.getIndex());
202 //===--------------------------------------------------------------------===//
204 MCSymbol *ARMAsmPrinter::
205 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
206 const DataLayout *DL = TM.getDataLayout();
207 SmallString<60> Name;
208 raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "JTI"
209 << getFunctionNumber() << '_' << uid << '_' << uid2;
210 return OutContext.GetOrCreateSymbol(Name.str());
214 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const {
215 const DataLayout *DL = TM.getDataLayout();
216 SmallString<60> Name;
217 raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "SJLJEH"
218 << getFunctionNumber();
219 return OutContext.GetOrCreateSymbol(Name.str());
222 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
223 unsigned AsmVariant, const char *ExtraCode,
225 // Does this asm operand have a single letter operand modifier?
226 if (ExtraCode && ExtraCode[0]) {
227 if (ExtraCode[1] != 0) return true; // Unknown modifier.
229 switch (ExtraCode[0]) {
231 // See if this is a generic print operand
232 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
233 case 'a': // Print as a memory address.
234 if (MI->getOperand(OpNum).isReg()) {
236 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
241 case 'c': // Don't print "#" before an immediate operand.
242 if (!MI->getOperand(OpNum).isImm())
244 O << MI->getOperand(OpNum).getImm();
246 case 'P': // Print a VFP double precision register.
247 case 'q': // Print a NEON quad precision register.
248 printOperand(MI, OpNum, O);
250 case 'y': // Print a VFP single precision register as indexed double.
251 if (MI->getOperand(OpNum).isReg()) {
252 unsigned Reg = MI->getOperand(OpNum).getReg();
253 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
254 // Find the 'd' register that has this 's' register as a sub-register,
255 // and determine the lane number.
256 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
257 if (!ARM::DPRRegClass.contains(*SR))
259 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
260 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
265 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
266 if (!MI->getOperand(OpNum).isImm())
268 O << ~(MI->getOperand(OpNum).getImm());
270 case 'L': // The low 16 bits of an immediate constant.
271 if (!MI->getOperand(OpNum).isImm())
273 O << (MI->getOperand(OpNum).getImm() & 0xffff);
275 case 'M': { // A register range suitable for LDM/STM.
276 if (!MI->getOperand(OpNum).isReg())
278 const MachineOperand &MO = MI->getOperand(OpNum);
279 unsigned RegBegin = MO.getReg();
280 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
281 // already got the operands in registers that are operands to the
282 // inline asm statement.
284 if (ARM::GPRPairRegClass.contains(RegBegin)) {
285 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
286 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
287 O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
288 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
290 O << ARMInstPrinter::getRegisterName(RegBegin);
292 // FIXME: The register allocator not only may not have given us the
293 // registers in sequence, but may not be in ascending registers. This
294 // will require changes in the register allocator that'll need to be
295 // propagated down here if the operands change.
296 unsigned RegOps = OpNum + 1;
297 while (MI->getOperand(RegOps).isReg()) {
299 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
307 case 'R': // The most significant register of a pair.
308 case 'Q': { // The least significant register of a pair.
311 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
312 if (!FlagsOP.isImm())
314 unsigned Flags = FlagsOP.getImm();
316 // This operand may not be the one that actually provides the register. If
317 // it's tied to a previous one then we should refer instead to that one
318 // for registers and their classes.
320 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
321 for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
322 unsigned OpFlags = MI->getOperand(OpNum).getImm();
323 OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
325 Flags = MI->getOperand(OpNum).getImm();
327 // Later code expects OpNum to be pointing at the register rather than
332 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
334 InlineAsm::hasRegClassConstraint(Flags, RC);
335 if (RC == ARM::GPRPairRegClassID) {
338 const MachineOperand &MO = MI->getOperand(OpNum);
341 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
342 unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
343 ARM::gsub_0 : ARM::gsub_1);
344 O << ARMInstPrinter::getRegisterName(Reg);
349 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
350 if (RegOp >= MI->getNumOperands())
352 const MachineOperand &MO = MI->getOperand(RegOp);
355 unsigned Reg = MO.getReg();
356 O << ARMInstPrinter::getRegisterName(Reg);
360 case 'e': // The low doubleword register of a NEON quad register.
361 case 'f': { // The high doubleword register of a NEON quad register.
362 if (!MI->getOperand(OpNum).isReg())
364 unsigned Reg = MI->getOperand(OpNum).getReg();
365 if (!ARM::QPRRegClass.contains(Reg))
367 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
368 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
369 ARM::dsub_0 : ARM::dsub_1);
370 O << ARMInstPrinter::getRegisterName(SubReg);
374 // This modifier is not yet supported.
375 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
377 case 'H': { // The highest-numbered register of a pair.
378 const MachineOperand &MO = MI->getOperand(OpNum);
381 const MachineFunction &MF = *MI->getParent()->getParent();
382 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
383 unsigned Reg = MO.getReg();
384 if(!ARM::GPRPairRegClass.contains(Reg))
386 Reg = TRI->getSubReg(Reg, ARM::gsub_1);
387 O << ARMInstPrinter::getRegisterName(Reg);
393 printOperand(MI, OpNum, O);
397 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
398 unsigned OpNum, unsigned AsmVariant,
399 const char *ExtraCode,
401 // Does this asm operand have a single letter operand modifier?
402 if (ExtraCode && ExtraCode[0]) {
403 if (ExtraCode[1] != 0) return true; // Unknown modifier.
405 switch (ExtraCode[0]) {
406 case 'A': // A memory operand for a VLD1/VST1 instruction.
407 default: return true; // Unknown modifier.
408 case 'm': // The base register of a memory operand.
409 if (!MI->getOperand(OpNum).isReg())
411 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
416 const MachineOperand &MO = MI->getOperand(OpNum);
417 assert(MO.isReg() && "unexpected inline asm memory operand");
418 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
422 static bool isThumb(const MCSubtargetInfo& STI) {
423 return STI.getFeatureBits()[ARM::ModeThumb];
426 void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
427 const MCSubtargetInfo *EndInfo) const {
428 // If either end mode is unknown (EndInfo == NULL) or different than
429 // the start mode, then restore the start mode.
430 const bool WasThumb = isThumb(StartInfo);
431 if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
432 OutStreamer.EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
436 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
437 Triple TT(TM.getTargetTriple());
438 // Use unified assembler syntax.
439 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
441 // Emit ARM Build Attributes
442 if (TT.isOSBinFormatELF())
445 // Use the triple's architecture and subarchitecture to determine
446 // if we're thumb for the purposes of the top level code16 assembler
448 bool isThumb = TT.getArch() == Triple::thumb ||
449 TT.getArch() == Triple::thumbeb ||
450 TT.getSubArch() == Triple::ARMSubArch_v7m ||
451 TT.getSubArch() == Triple::ARMSubArch_v6m;
452 if (!M.getModuleInlineAsm().empty() && isThumb)
453 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
457 emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel,
458 MachineModuleInfoImpl::StubValueTy &MCSym) {
460 OutStreamer.EmitLabel(StubLabel);
461 // .indirect_symbol _foo
462 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
465 // External to current translation unit.
466 OutStreamer.EmitIntValue(0, 4/*size*/);
468 // Internal to current translation unit.
470 // When we place the LSDA into the TEXT section, the type info
471 // pointers need to be indirect and pc-rel. We accomplish this by
472 // using NLPs; however, sometimes the types are local to the file.
473 // We need to fill in the value for the NLP in those cases.
474 OutStreamer.EmitValue(
475 MCSymbolRefExpr::Create(MCSym.getPointer(), OutStreamer.getContext()),
480 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
481 Triple TT(TM.getTargetTriple());
482 if (TT.isOSBinFormatMachO()) {
483 // All darwin targets use mach-o.
484 const TargetLoweringObjectFileMachO &TLOFMacho =
485 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
486 MachineModuleInfoMachO &MMIMacho =
487 MMI->getObjFileInfo<MachineModuleInfoMachO>();
489 // Output non-lazy-pointers for external and common global variables.
490 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
492 if (!Stubs.empty()) {
493 // Switch with ".non_lazy_symbol_pointer" directive.
494 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
497 for (auto &Stub : Stubs)
498 emitNonLazySymbolPointer(OutStreamer, Stub.first, Stub.second);
501 OutStreamer.AddBlankLine();
504 Stubs = MMIMacho.GetHiddenGVStubList();
505 if (!Stubs.empty()) {
506 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
509 for (auto &Stub : Stubs)
510 emitNonLazySymbolPointer(OutStreamer, Stub.first, Stub.second);
513 OutStreamer.AddBlankLine();
516 // Funny Darwin hack: This flag tells the linker that no global symbols
517 // contain code that falls through to other global symbols (e.g. the obvious
518 // implementation of multiple entry points). If this doesn't occur, the
519 // linker can safely perform dead code stripping. Since LLVM never
520 // generates code that does this, it is always safe to set.
521 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
524 // Emit a .data.rel section containing any stubs that were created.
525 if (TT.isOSBinFormatELF()) {
526 const TargetLoweringObjectFileELF &TLOFELF =
527 static_cast<const TargetLoweringObjectFileELF &>(getObjFileLowering());
529 MachineModuleInfoELF &MMIELF = MMI->getObjFileInfo<MachineModuleInfoELF>();
531 // Output stubs for external and common global variables.
532 MachineModuleInfoELF::SymbolListTy Stubs = MMIELF.GetGVStubList();
533 if (!Stubs.empty()) {
534 OutStreamer.SwitchSection(TLOFELF.getDataRelSection());
535 const DataLayout *TD = TM.getDataLayout();
537 for (auto &stub: Stubs) {
538 OutStreamer.EmitLabel(stub.first);
539 OutStreamer.EmitSymbolValue(stub.second.getPointer(),
540 TD->getPointerSize(0));
547 //===----------------------------------------------------------------------===//
548 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
550 // The following seem like one-off assembler flags, but they actually need
551 // to appear in the .ARM.attributes section in ELF.
552 // Instead of subclassing the MCELFStreamer, we do the work here.
554 static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
555 const ARMSubtarget *Subtarget) {
557 return ARMBuildAttrs::v5TEJ;
559 if (Subtarget->hasV8Ops())
560 return ARMBuildAttrs::v8;
561 else if (Subtarget->hasV7Ops()) {
562 if (Subtarget->isMClass() && Subtarget->hasThumb2DSP())
563 return ARMBuildAttrs::v7E_M;
564 return ARMBuildAttrs::v7;
565 } else if (Subtarget->hasV6T2Ops())
566 return ARMBuildAttrs::v6T2;
567 else if (Subtarget->hasV6MOps())
568 return ARMBuildAttrs::v6S_M;
569 else if (Subtarget->hasV6Ops())
570 return ARMBuildAttrs::v6;
571 else if (Subtarget->hasV5TEOps())
572 return ARMBuildAttrs::v5TE;
573 else if (Subtarget->hasV5TOps())
574 return ARMBuildAttrs::v5T;
575 else if (Subtarget->hasV4TOps())
576 return ARMBuildAttrs::v4T;
578 return ARMBuildAttrs::v4;
581 void ARMAsmPrinter::emitAttributes() {
582 MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
583 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
585 ATS.emitTextAttribute(ARMBuildAttrs::conformance, "2.09");
587 ATS.switchVendor("aeabi");
589 // Compute ARM ELF Attributes based on the default subtarget that
590 // we'd have constructed. The existing ARM behavior isn't LTO clean
592 // FIXME: For ifunc related functions we could iterate over and look
593 // for a feature string that doesn't match the default one.
594 StringRef TT = TM.getTargetTriple();
595 StringRef CPU = TM.getTargetCPU();
596 StringRef FS = TM.getTargetFeatureString();
597 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
600 ArchFS = ArchFS + "," + FS.str();
604 const ARMBaseTargetMachine &ATM =
605 static_cast<const ARMBaseTargetMachine &>(TM);
606 const ARMSubtarget STI(TT, CPU, ArchFS, ATM, ATM.isLittleEndian());
608 std::string CPUString = STI.getCPUString();
610 if (CPUString != "generic") {
611 // FIXME: remove krait check when GNU tools support krait cpu
613 ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a9");
614 // We consider krait as a "cortex-a9" + hwdiv CPU
615 // Enable hwdiv through ".arch_extension idiv"
616 if (STI.hasDivide() || STI.hasDivideInARMMode())
617 ATS.emitArchExtension(ARM::HWDIV);
619 ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
622 ATS.emitAttribute(ARMBuildAttrs::CPU_arch, getArchForCPU(CPUString, &STI));
624 // Tag_CPU_arch_profile must have the default value of 0 when "Architecture
625 // profile is not applicable (e.g. pre v7, or cross-profile code)".
626 if (STI.hasV7Ops()) {
627 if (STI.isAClass()) {
628 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
629 ARMBuildAttrs::ApplicationProfile);
630 } else if (STI.isRClass()) {
631 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
632 ARMBuildAttrs::RealTimeProfile);
633 } else if (STI.isMClass()) {
634 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
635 ARMBuildAttrs::MicroControllerProfile);
639 ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use,
640 STI.hasARMOps() ? ARMBuildAttrs::Allowed
641 : ARMBuildAttrs::Not_Allowed);
642 if (STI.isThumb1Only()) {
643 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use, ARMBuildAttrs::Allowed);
644 } else if (STI.hasThumb2()) {
645 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
646 ARMBuildAttrs::AllowThumb32);
650 /* NEON is not exactly a VFP architecture, but GAS emit one of
651 * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
652 if (STI.hasFPARMv8()) {
654 ATS.emitFPU(ARM::CRYPTO_NEON_FP_ARMV8);
656 ATS.emitFPU(ARM::NEON_FP_ARMV8);
657 } else if (STI.hasVFP4())
658 ATS.emitFPU(ARM::NEON_VFPV4);
660 ATS.emitFPU(ARM::NEON);
661 // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
663 ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
664 ARMBuildAttrs::AllowNeonARMv8);
666 if (STI.hasFPARMv8())
667 // FPv5 and FP-ARMv8 have the same instructions, so are modeled as one
668 // FPU, but there are two different names for it depending on the CPU.
669 ATS.emitFPU(STI.hasD16() ? ARM::FPV5_D16 : ARM::FP_ARMV8);
670 else if (STI.hasVFP4())
671 ATS.emitFPU(STI.hasD16() ? ARM::VFPV4_D16 : ARM::VFPV4);
672 else if (STI.hasVFP3())
673 ATS.emitFPU(STI.hasD16() ? ARM::VFPV3_D16 : ARM::VFPV3);
674 else if (STI.hasVFP2())
675 ATS.emitFPU(ARM::VFPV2);
678 if (TM.getRelocationModel() == Reloc::PIC_) {
679 // PIC specific attributes.
680 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
681 ARMBuildAttrs::AddressRWPCRel);
682 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RO_data,
683 ARMBuildAttrs::AddressROPCRel);
684 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
685 ARMBuildAttrs::AddressGOT);
687 // Allow direct addressing of imported data for all other relocation models.
688 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
689 ARMBuildAttrs::AddressDirect);
692 // Signal various FP modes.
693 if (!TM.Options.UnsafeFPMath) {
694 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
695 ARMBuildAttrs::IEEEDenormals);
696 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions, ARMBuildAttrs::Allowed);
698 // If the user has permitted this code to choose the IEEE 754
699 // rounding at run-time, emit the rounding attribute.
700 if (TM.Options.HonorSignDependentRoundingFPMathOption)
701 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_rounding, ARMBuildAttrs::Allowed);
703 if (!STI.hasVFP2()) {
704 // When the target doesn't have an FPU (by design or
705 // intention), the assumptions made on the software support
706 // mirror that of the equivalent hardware support *if it
707 // existed*. For v7 and better we indicate that denormals are
708 // flushed preserving sign, and for V6 we indicate that
709 // denormals are flushed to positive zero.
711 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
712 ARMBuildAttrs::PreserveFPSign);
713 } else if (STI.hasVFP3()) {
714 // In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is,
715 // the sign bit of the zero matches the sign bit of the input or
716 // result that is being flushed to zero.
717 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
718 ARMBuildAttrs::PreserveFPSign);
720 // For VFPv2 implementations it is implementation defined as
721 // to whether denormals are flushed to positive zero or to
722 // whatever the sign of zero is (ARM v7AR ARM 2.7.5). Historically
723 // LLVM has chosen to flush this to positive zero (most likely for
724 // GCC compatibility), so that's the chosen value here (the
725 // absence of its emission implies zero).
728 // TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath is the
729 // equivalent of GCC's -ffinite-math-only flag.
730 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
731 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
732 ARMBuildAttrs::Allowed);
734 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
735 ARMBuildAttrs::AllowIEE754);
737 if (STI.allowsUnalignedMem())
738 ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
739 ARMBuildAttrs::Allowed);
741 ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
742 ARMBuildAttrs::Not_Allowed);
744 // FIXME: add more flags to ARMBuildAttributes.h
745 // 8-bytes alignment stuff.
746 ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
747 ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
749 // ABI_HardFP_use attribute to indicate single precision FP.
750 if (STI.isFPOnlySP())
751 ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
752 ARMBuildAttrs::HardFPSinglePrecision);
754 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
755 if (STI.isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
756 ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
758 // FIXME: Should we signal R9 usage?
761 ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
763 // FIXME: To support emitting this build attribute as GCC does, the
764 // -mfp16-format option and associated plumbing must be
765 // supported. For now the __fp16 type is exposed by default, so this
766 // attribute should be emitted with value 1.
767 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_16bit_format,
768 ARMBuildAttrs::FP16FormatIEEE);
770 if (STI.hasMPExtension())
771 ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
773 // Hardware divide in ARM mode is part of base arch, starting from ARMv8.
774 // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
775 // It is not possible to produce DisallowDIV: if hwdiv is present in the base
776 // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
777 // AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
778 // otherwise, the default value (AllowDIVIfExists) applies.
779 if (STI.hasDivideInARMMode() && !STI.hasV8Ops())
780 ATS.emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
783 if (const Module *SourceModule = MMI->getModule()) {
784 // ABI_PCS_wchar_t to indicate wchar_t width
785 // FIXME: There is no way to emit value 0 (wchar_t prohibited).
786 if (auto WCharWidthValue = mdconst::extract_or_null<ConstantInt>(
787 SourceModule->getModuleFlag("wchar_size"))) {
788 int WCharWidth = WCharWidthValue->getZExtValue();
789 assert((WCharWidth == 2 || WCharWidth == 4) &&
790 "wchar_t width must be 2 or 4 bytes");
791 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_wchar_t, WCharWidth);
794 // ABI_enum_size to indicate enum width
795 // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
796 // (all enums contain a value needing 32 bits to encode).
797 if (auto EnumWidthValue = mdconst::extract_or_null<ConstantInt>(
798 SourceModule->getModuleFlag("min_enum_size"))) {
799 int EnumWidth = EnumWidthValue->getZExtValue();
800 assert((EnumWidth == 1 || EnumWidth == 4) &&
801 "Minimum enum width must be 1 or 4 bytes");
802 int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
803 ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
808 // TODO: We currently only support either reserving the register, or treating
809 // it as another callee-saved register, but not as SB or a TLS pointer; It
810 // would instead be nicer to push this from the frontend as metadata, as we do
811 // for the wchar and enum size tags
812 if (STI.isR9Reserved())
813 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use, ARMBuildAttrs::R9Reserved);
815 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use, ARMBuildAttrs::R9IsGPR);
817 if (STI.hasTrustZone() && STI.hasVirtualization())
818 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
819 ARMBuildAttrs::AllowTZVirtualization);
820 else if (STI.hasTrustZone())
821 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
822 ARMBuildAttrs::AllowTZ);
823 else if (STI.hasVirtualization())
824 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
825 ARMBuildAttrs::AllowVirtualization);
827 ATS.finishAttributeSection();
830 //===----------------------------------------------------------------------===//
832 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
833 unsigned LabelId, MCContext &Ctx) {
835 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
836 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
840 static MCSymbolRefExpr::VariantKind
841 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
843 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
844 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_TLSGD;
845 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_TPOFF;
846 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_GOTTPOFF;
847 case ARMCP::GOT: return MCSymbolRefExpr::VK_GOT;
848 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_GOTOFF;
850 llvm_unreachable("Invalid ARMCPModifier!");
853 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
854 unsigned char TargetFlags) {
855 if (Subtarget->isTargetMachO()) {
856 bool IsIndirect = (TargetFlags & ARMII::MO_NONLAZY) &&
857 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
860 return getSymbol(GV);
862 // FIXME: Remove this when Darwin transition to @GOT like syntax.
863 MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
864 MachineModuleInfoMachO &MMIMachO =
865 MMI->getObjFileInfo<MachineModuleInfoMachO>();
866 MachineModuleInfoImpl::StubValueTy &StubSym =
867 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym)
868 : MMIMachO.getGVStubEntry(MCSym);
869 if (!StubSym.getPointer())
870 StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV),
871 !GV->hasInternalLinkage());
873 } else if (Subtarget->isTargetCOFF()) {
874 assert(Subtarget->isTargetWindows() &&
875 "Windows is the only supported COFF target");
877 bool IsIndirect = (TargetFlags & ARMII::MO_DLLIMPORT);
879 return getSymbol(GV);
881 SmallString<128> Name;
883 getNameWithPrefix(Name, GV);
885 return OutContext.GetOrCreateSymbol(Name);
886 } else if (Subtarget->isTargetELF()) {
887 return getSymbol(GV);
889 llvm_unreachable("unexpected target");
893 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
894 const DataLayout *DL = TM.getDataLayout();
895 int Size = TM.getDataLayout()->getTypeAllocSize(MCPV->getType());
897 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
900 if (ACPV->isLSDA()) {
901 MCSym = getCurExceptionSym();
902 } else if (ACPV->isBlockAddress()) {
903 const BlockAddress *BA =
904 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
905 MCSym = GetBlockAddressSymbol(BA);
906 } else if (ACPV->isGlobalValue()) {
907 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
909 // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
910 // flag the global as MO_NONLAZY.
911 unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
912 MCSym = GetARMGVSymbol(GV, TF);
913 } else if (ACPV->isMachineBasicBlock()) {
914 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
915 MCSym = MBB->getSymbol();
917 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
918 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
919 MCSym = GetExternalSymbolSymbol(Sym);
922 // Create an MCSymbol for the reference.
924 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
927 if (ACPV->getPCAdjustment()) {
928 MCSymbol *PCLabel = getPICLabel(DL->getPrivateGlobalPrefix(),
932 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
934 MCBinaryExpr::CreateAdd(PCRelExpr,
935 MCConstantExpr::Create(ACPV->getPCAdjustment(),
938 if (ACPV->mustAddCurrentAddress()) {
939 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
940 // label, so just emit a local label end reference that instead.
941 MCSymbol *DotSym = OutContext.CreateTempSymbol();
942 OutStreamer.EmitLabel(DotSym);
943 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
944 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
946 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
948 OutStreamer.EmitValue(Expr, Size);
951 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
952 unsigned Opcode = MI->getOpcode();
954 if (Opcode == ARM::BR_JTadd)
956 else if (Opcode == ARM::BR_JTm)
959 const MachineOperand &MO1 = MI->getOperand(OpNum);
960 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
961 unsigned JTI = MO1.getIndex();
963 // Emit a label for the jump table.
964 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
965 OutStreamer.EmitLabel(JTISymbol);
967 // Mark the jump table as data-in-code.
968 OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
970 // Emit each entry of the table.
971 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
972 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
973 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
975 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
976 MachineBasicBlock *MBB = JTBBs[i];
977 // Construct an MCExpr for the entry. We want a value of the form:
978 // (BasicBlockAddr - TableBeginAddr)
980 // For example, a table with entries jumping to basic blocks BB0 and BB1
983 // .word (LBB0 - LJTI_0_0)
984 // .word (LBB1 - LJTI_0_0)
985 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
987 if (TM.getRelocationModel() == Reloc::PIC_)
988 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
991 // If we're generating a table of Thumb addresses in static relocation
992 // model, we need to add one to keep interworking correctly.
993 else if (AFI->isThumbFunction())
994 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
996 OutStreamer.EmitValue(Expr, 4);
998 // Mark the end of jump table data-in-code region.
999 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1002 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
1003 unsigned Opcode = MI->getOpcode();
1004 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
1005 const MachineOperand &MO1 = MI->getOperand(OpNum);
1006 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
1007 unsigned JTI = MO1.getIndex();
1009 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
1010 OutStreamer.EmitLabel(JTISymbol);
1012 // Emit each entry of the table.
1013 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1014 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1015 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1016 unsigned OffsetWidth = 4;
1017 if (MI->getOpcode() == ARM::t2TBB_JT) {
1019 // Mark the jump table as data-in-code.
1020 OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
1021 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
1023 // Mark the jump table as data-in-code.
1024 OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
1027 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1028 MachineBasicBlock *MBB = JTBBs[i];
1029 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
1031 // If this isn't a TBB or TBH, the entries are direct branch instructions.
1032 if (OffsetWidth == 4) {
1033 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2B)
1034 .addExpr(MBBSymbolExpr)
1039 // Otherwise it's an offset from the dispatch instruction. Construct an
1040 // MCExpr for the entry. We want a value of the form:
1041 // (BasicBlockAddr - TableBeginAddr) / 2
1043 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1046 // .byte (LBB0 - LJTI_0_0) / 2
1047 // .byte (LBB1 - LJTI_0_0) / 2
1048 const MCExpr *Expr =
1049 MCBinaryExpr::CreateSub(MBBSymbolExpr,
1050 MCSymbolRefExpr::Create(JTISymbol, OutContext),
1052 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
1054 OutStreamer.EmitValue(Expr, OffsetWidth);
1056 // Mark the end of jump table data-in-code region. 32-bit offsets use
1057 // actual branch instructions here, so we don't mark those as a data-region
1059 if (OffsetWidth != 4)
1060 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1063 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1064 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1065 "Only instruction which are involved into frame setup code are allowed");
1067 MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
1068 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1069 const MachineFunction &MF = *MI->getParent()->getParent();
1070 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
1071 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1073 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1074 unsigned Opc = MI->getOpcode();
1075 unsigned SrcReg, DstReg;
1077 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1078 // Two special cases:
1079 // 1) tPUSH does not have src/dst regs.
1080 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1081 // load. Yes, this is pretty fragile, but for now I don't see better
1083 SrcReg = DstReg = ARM::SP;
1085 SrcReg = MI->getOperand(1).getReg();
1086 DstReg = MI->getOperand(0).getReg();
1089 // Try to figure out the unwinding opcode out of src / dst regs.
1090 if (MI->mayStore()) {
1092 assert(DstReg == ARM::SP &&
1093 "Only stack pointer as a destination reg is supported");
1095 SmallVector<unsigned, 4> RegList;
1096 // Skip src & dst reg, and pred ops.
1097 unsigned StartOp = 2 + 2;
1098 // Use all the operands.
1099 unsigned NumOffset = 0;
1104 llvm_unreachable("Unsupported opcode for unwinding information");
1106 // Special case here: no src & dst reg, but two extra imp ops.
1107 StartOp = 2; NumOffset = 2;
1108 case ARM::STMDB_UPD:
1109 case ARM::t2STMDB_UPD:
1110 case ARM::VSTMDDB_UPD:
1111 assert(SrcReg == ARM::SP &&
1112 "Only stack pointer as a source reg is supported");
1113 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1115 const MachineOperand &MO = MI->getOperand(i);
1116 // Actually, there should never be any impdef stuff here. Skip it
1117 // temporary to workaround PR11902.
1118 if (MO.isImplicit())
1120 RegList.push_back(MO.getReg());
1123 case ARM::STR_PRE_IMM:
1124 case ARM::STR_PRE_REG:
1125 case ARM::t2STR_PRE:
1126 assert(MI->getOperand(2).getReg() == ARM::SP &&
1127 "Only stack pointer as a source reg is supported");
1128 RegList.push_back(SrcReg);
1131 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM)
1132 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1134 // Changes of stack / frame pointer.
1135 if (SrcReg == ARM::SP) {
1140 llvm_unreachable("Unsupported opcode for unwinding information");
1146 Offset = -MI->getOperand(2).getImm();
1150 Offset = MI->getOperand(2).getImm();
1153 Offset = MI->getOperand(2).getImm()*4;
1157 Offset = -MI->getOperand(2).getImm()*4;
1159 case ARM::tLDRpci: {
1160 // Grab the constpool index and check, whether it corresponds to
1161 // original or cloned constpool entry.
1162 unsigned CPI = MI->getOperand(1).getIndex();
1163 const MachineConstantPool *MCP = MF.getConstantPool();
1164 if (CPI >= MCP->getConstants().size())
1165 CPI = AFI.getOriginalCPIdx(CPI);
1166 assert(CPI != -1U && "Invalid constpool index");
1168 // Derive the actual offset.
1169 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1170 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1171 // FIXME: Check for user, it should be "add" instruction!
1172 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1177 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
1178 if (DstReg == FramePtr && FramePtr != ARM::SP)
1179 // Set-up of the frame pointer. Positive values correspond to "add"
1181 ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1182 else if (DstReg == ARM::SP) {
1183 // Change of SP by an offset. Positive values correspond to "sub"
1185 ATS.emitPad(Offset);
1187 // Move of SP to a register. Positive values correspond to an "add"
1189 ATS.emitMovSP(DstReg, -Offset);
1192 } else if (DstReg == ARM::SP) {
1194 llvm_unreachable("Unsupported opcode for unwinding information");
1198 llvm_unreachable("Unsupported opcode for unwinding information");
1203 // Simple pseudo-instructions have their lowering (with expansion to real
1204 // instructions) auto-generated.
1205 #include "ARMGenMCPseudoLowering.inc"
1207 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1208 const DataLayout *DL = TM.getDataLayout();
1210 // If we just ended a constant pool, mark it as such.
1211 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1212 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1213 InConstantPool = false;
1216 // Emit unwinding stuff for frame-related instructions
1217 if (Subtarget->isTargetEHABICompatible() &&
1218 MI->getFlag(MachineInstr::FrameSetup))
1219 EmitUnwindingInstruction(MI);
1221 // Do any auto-generated pseudo lowerings.
1222 if (emitPseudoExpansionLowering(OutStreamer, MI))
1225 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1226 "Pseudo flag setting opcode should be expanded early");
1228 // Check for manual lowerings.
1229 unsigned Opc = MI->getOpcode();
1231 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1232 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1234 case ARM::tLEApcrel:
1235 case ARM::t2LEApcrel: {
1236 // FIXME: Need to also handle globals and externals
1237 MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1238 EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
1239 ARM::t2LEApcrel ? ARM::t2ADR
1240 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1242 .addReg(MI->getOperand(0).getReg())
1243 .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
1244 // Add predicate operands.
1245 .addImm(MI->getOperand(2).getImm())
1246 .addReg(MI->getOperand(3).getReg()));
1249 case ARM::LEApcrelJT:
1250 case ARM::tLEApcrelJT:
1251 case ARM::t2LEApcrelJT: {
1252 MCSymbol *JTIPICSymbol =
1253 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1254 MI->getOperand(2).getImm());
1255 EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
1256 ARM::t2LEApcrelJT ? ARM::t2ADR
1257 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1259 .addReg(MI->getOperand(0).getReg())
1260 .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
1261 // Add predicate operands.
1262 .addImm(MI->getOperand(3).getImm())
1263 .addReg(MI->getOperand(4).getReg()));
1266 // Darwin call instructions are just normal call instructions with different
1267 // clobber semantics (they clobber R9).
1268 case ARM::BX_CALL: {
1269 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1272 // Add predicate operands.
1275 // Add 's' bit operand (always reg0 for this)
1278 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
1279 .addReg(MI->getOperand(0).getReg()));
1282 case ARM::tBX_CALL: {
1283 if (Subtarget->hasV5TOps())
1284 llvm_unreachable("Expected BLX to be selected for v5t+");
1286 // On ARM v4t, when doing a call from thumb mode, we need to ensure
1287 // that the saved lr has its LSB set correctly (the arch doesn't
1289 // So here we generate a bl to a small jump pad that does bx rN.
1290 // The jump pads are emitted after the function body.
1292 unsigned TReg = MI->getOperand(0).getReg();
1293 MCSymbol *TRegSym = nullptr;
1294 for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) {
1295 if (ThumbIndirectPads[i].first == TReg) {
1296 TRegSym = ThumbIndirectPads[i].second;
1302 TRegSym = OutContext.CreateTempSymbol();
1303 ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym));
1306 // Create a link-saving branch to the Reg Indirect Jump Pad.
1307 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBL)
1308 // Predicate comes first here.
1309 .addImm(ARMCC::AL).addReg(0)
1310 .addExpr(MCSymbolRefExpr::Create(TRegSym, OutContext)));
1313 case ARM::BMOVPCRX_CALL: {
1314 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1317 // Add predicate operands.
1320 // Add 's' bit operand (always reg0 for this)
1323 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1325 .addReg(MI->getOperand(0).getReg())
1326 // Add predicate operands.
1329 // Add 's' bit operand (always reg0 for this)
1333 case ARM::BMOVPCB_CALL: {
1334 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1337 // Add predicate operands.
1340 // Add 's' bit operand (always reg0 for this)
1343 const MachineOperand &Op = MI->getOperand(0);
1344 const GlobalValue *GV = Op.getGlobal();
1345 const unsigned TF = Op.getTargetFlags();
1346 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1347 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1348 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::Bcc)
1350 // Add predicate operands.
1355 case ARM::MOVi16_ga_pcrel:
1356 case ARM::t2MOVi16_ga_pcrel: {
1358 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1359 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1361 unsigned TF = MI->getOperand(1).getTargetFlags();
1362 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1363 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1364 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1366 MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
1367 getFunctionNumber(),
1368 MI->getOperand(2).getImm(), OutContext);
1369 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1370 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1371 const MCExpr *PCRelExpr =
1372 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1373 MCBinaryExpr::CreateAdd(LabelSymExpr,
1374 MCConstantExpr::Create(PCAdj, OutContext),
1375 OutContext), OutContext), OutContext);
1376 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1378 // Add predicate operands.
1379 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1380 TmpInst.addOperand(MCOperand::CreateReg(0));
1381 // Add 's' bit operand (always reg0 for this)
1382 TmpInst.addOperand(MCOperand::CreateReg(0));
1383 EmitToStreamer(OutStreamer, TmpInst);
1386 case ARM::MOVTi16_ga_pcrel:
1387 case ARM::t2MOVTi16_ga_pcrel: {
1389 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1390 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1391 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1392 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1394 unsigned TF = MI->getOperand(2).getTargetFlags();
1395 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1396 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1397 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1399 MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
1400 getFunctionNumber(),
1401 MI->getOperand(3).getImm(), OutContext);
1402 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1403 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1404 const MCExpr *PCRelExpr =
1405 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1406 MCBinaryExpr::CreateAdd(LabelSymExpr,
1407 MCConstantExpr::Create(PCAdj, OutContext),
1408 OutContext), OutContext), OutContext);
1409 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1410 // Add predicate operands.
1411 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1412 TmpInst.addOperand(MCOperand::CreateReg(0));
1413 // Add 's' bit operand (always reg0 for this)
1414 TmpInst.addOperand(MCOperand::CreateReg(0));
1415 EmitToStreamer(OutStreamer, TmpInst);
1418 case ARM::tPICADD: {
1419 // This is a pseudo op for a label + instruction sequence, which looks like:
1422 // This adds the address of LPC0 to r0.
1425 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1426 getFunctionNumber(), MI->getOperand(2).getImm(),
1429 // Form and emit the add.
1430 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDhirr)
1431 .addReg(MI->getOperand(0).getReg())
1432 .addReg(MI->getOperand(0).getReg())
1434 // Add predicate operands.
1440 // This is a pseudo op for a label + instruction sequence, which looks like:
1443 // This adds the address of LPC0 to r0.
1446 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1447 getFunctionNumber(), MI->getOperand(2).getImm(),
1450 // Form and emit the add.
1451 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
1452 .addReg(MI->getOperand(0).getReg())
1454 .addReg(MI->getOperand(1).getReg())
1455 // Add predicate operands.
1456 .addImm(MI->getOperand(3).getImm())
1457 .addReg(MI->getOperand(4).getReg())
1458 // Add 's' bit operand (always reg0 for this)
1469 case ARM::PICLDRSH: {
1470 // This is a pseudo op for a label + instruction sequence, which looks like:
1473 // The LCP0 label is referenced by a constant pool entry in order to get
1474 // a PC-relative address at the ldr instruction.
1477 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1478 getFunctionNumber(), MI->getOperand(2).getImm(),
1481 // Form and emit the load
1483 switch (MI->getOpcode()) {
1485 llvm_unreachable("Unexpected opcode!");
1486 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1487 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1488 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1489 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1490 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1491 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1492 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1493 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1495 EmitToStreamer(OutStreamer, MCInstBuilder(Opcode)
1496 .addReg(MI->getOperand(0).getReg())
1498 .addReg(MI->getOperand(1).getReg())
1500 // Add predicate operands.
1501 .addImm(MI->getOperand(3).getImm())
1502 .addReg(MI->getOperand(4).getReg()));
1506 case ARM::CONSTPOOL_ENTRY: {
1507 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1508 /// in the function. The first operand is the ID# for this instruction, the
1509 /// second is the index into the MachineConstantPool that this is, the third
1510 /// is the size in bytes of this constant pool entry.
1511 /// The required alignment is specified on the basic block holding this MI.
1512 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1513 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1515 // If this is the first entry of the pool, mark it.
1516 if (!InConstantPool) {
1517 OutStreamer.EmitDataRegion(MCDR_DataRegion);
1518 InConstantPool = true;
1521 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1523 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1524 if (MCPE.isMachineConstantPoolEntry())
1525 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1527 EmitGlobalConstant(MCPE.Val.ConstVal);
1530 case ARM::t2BR_JT: {
1531 // Lower and emit the instruction itself, then the jump table following it.
1532 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
1534 .addReg(MI->getOperand(0).getReg())
1535 // Add predicate operands.
1539 // Output the data for the jump table itself
1543 case ARM::t2TBB_JT: {
1544 // Lower and emit the instruction itself, then the jump table following it.
1545 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBB)
1547 .addReg(MI->getOperand(0).getReg())
1548 // Add predicate operands.
1552 // Output the data for the jump table itself
1554 // Make sure the next instruction is 2-byte aligned.
1558 case ARM::t2TBH_JT: {
1559 // Lower and emit the instruction itself, then the jump table following it.
1560 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBH)
1562 .addReg(MI->getOperand(0).getReg())
1563 // Add predicate operands.
1567 // Output the data for the jump table itself
1573 // Lower and emit the instruction itself, then the jump table following it.
1576 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1577 ARM::MOVr : ARM::tMOVr;
1578 TmpInst.setOpcode(Opc);
1579 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1580 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1581 // Add predicate operands.
1582 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1583 TmpInst.addOperand(MCOperand::CreateReg(0));
1584 // Add 's' bit operand (always reg0 for this)
1585 if (Opc == ARM::MOVr)
1586 TmpInst.addOperand(MCOperand::CreateReg(0));
1587 EmitToStreamer(OutStreamer, TmpInst);
1589 // Make sure the Thumb jump table is 4-byte aligned.
1590 if (Opc == ARM::tMOVr)
1593 // Output the data for the jump table itself
1598 // Lower and emit the instruction itself, then the jump table following it.
1601 if (MI->getOperand(1).getReg() == 0) {
1603 TmpInst.setOpcode(ARM::LDRi12);
1604 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1605 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1606 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1608 TmpInst.setOpcode(ARM::LDRrs);
1609 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1610 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1611 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1612 TmpInst.addOperand(MCOperand::CreateImm(0));
1614 // Add predicate operands.
1615 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1616 TmpInst.addOperand(MCOperand::CreateReg(0));
1617 EmitToStreamer(OutStreamer, TmpInst);
1619 // Output the data for the jump table itself
1623 case ARM::BR_JTadd: {
1624 // Lower and emit the instruction itself, then the jump table following it.
1625 // add pc, target, idx
1626 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
1628 .addReg(MI->getOperand(0).getReg())
1629 .addReg(MI->getOperand(1).getReg())
1630 // Add predicate operands.
1633 // Add 's' bit operand (always reg0 for this)
1636 // Output the data for the jump table itself
1641 OutStreamer.EmitZeros(MI->getOperand(1).getImm());
1644 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1645 // FIXME: Remove this special case when they do.
1646 if (!Subtarget->isTargetMachO()) {
1647 //.long 0xe7ffdefe @ trap
1648 uint32_t Val = 0xe7ffdefeUL;
1649 OutStreamer.AddComment("trap");
1650 OutStreamer.EmitIntValue(Val, 4);
1655 case ARM::TRAPNaCl: {
1656 //.long 0xe7fedef0 @ trap
1657 uint32_t Val = 0xe7fedef0UL;
1658 OutStreamer.AddComment("trap");
1659 OutStreamer.EmitIntValue(Val, 4);
1663 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1664 // FIXME: Remove this special case when they do.
1665 if (!Subtarget->isTargetMachO()) {
1666 //.short 57086 @ trap
1667 uint16_t Val = 0xdefe;
1668 OutStreamer.AddComment("trap");
1669 OutStreamer.EmitIntValue(Val, 2);
1674 case ARM::t2Int_eh_sjlj_setjmp:
1675 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1676 case ARM::tInt_eh_sjlj_setjmp: {
1677 // Two incoming args: GPR:$src, GPR:$val
1680 // str $val, [$src, #4]
1685 unsigned SrcReg = MI->getOperand(0).getReg();
1686 unsigned ValReg = MI->getOperand(1).getReg();
1687 MCSymbol *Label = GetARMSJLJEHLabel();
1688 OutStreamer.AddComment("eh_setjmp begin");
1689 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
1696 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDi3)
1706 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tSTRi)
1709 // The offset immediate is #4. The operand value is scaled by 4 for the
1710 // tSTR instruction.
1716 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
1724 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1725 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tB)
1726 .addExpr(SymbolExpr)
1730 OutStreamer.AddComment("eh_setjmp end");
1731 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
1739 OutStreamer.EmitLabel(Label);
1743 case ARM::Int_eh_sjlj_setjmp_nofp:
1744 case ARM::Int_eh_sjlj_setjmp: {
1745 // Two incoming args: GPR:$src, GPR:$val
1747 // str $val, [$src, #+4]
1751 unsigned SrcReg = MI->getOperand(0).getReg();
1752 unsigned ValReg = MI->getOperand(1).getReg();
1754 OutStreamer.AddComment("eh_setjmp begin");
1755 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
1762 // 's' bit operand (always reg0 for this).
1765 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::STRi12)
1773 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
1779 // 's' bit operand (always reg0 for this).
1782 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
1789 // 's' bit operand (always reg0 for this).
1792 OutStreamer.AddComment("eh_setjmp end");
1793 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
1799 // 's' bit operand (always reg0 for this).
1803 case ARM::Int_eh_sjlj_longjmp: {
1804 // ldr sp, [$src, #8]
1805 // ldr $scratch, [$src, #4]
1808 unsigned SrcReg = MI->getOperand(0).getReg();
1809 unsigned ScratchReg = MI->getOperand(1).getReg();
1810 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
1818 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
1826 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
1834 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
1841 case ARM::tInt_eh_sjlj_longjmp: {
1842 // ldr $scratch, [$src, #8]
1844 // ldr $scratch, [$src, #4]
1847 unsigned SrcReg = MI->getOperand(0).getReg();
1848 unsigned ScratchReg = MI->getOperand(1).getReg();
1849 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
1852 // The offset immediate is #8. The operand value is scaled by 4 for the
1853 // tLDR instruction.
1859 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
1866 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
1874 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
1882 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
1892 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1894 EmitToStreamer(OutStreamer, TmpInst);
1897 //===----------------------------------------------------------------------===//
1898 // Target Registry Stuff
1899 //===----------------------------------------------------------------------===//
1901 // Force static initialization.
1902 extern "C" void LLVMInitializeARMAsmPrinter() {
1903 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMLETarget);
1904 RegisterAsmPrinter<ARMAsmPrinter> Y(TheARMBETarget);
1905 RegisterAsmPrinter<ARMAsmPrinter> A(TheThumbLETarget);
1906 RegisterAsmPrinter<ARMAsmPrinter> B(TheThumbBETarget);