1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
16 #include "ARMAsmPrinter.h"
18 #include "ARMBuildAttrs.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMTargetMachine.h"
22 #include "ARMTargetObjectFile.h"
23 #include "InstPrinter/ARMInstPrinter.h"
24 #include "MCTargetDesc/ARMAddressingModes.h"
25 #include "MCTargetDesc/ARMMCExpr.h"
26 #include "llvm/Analysis/DebugInfo.h"
27 #include "llvm/Constants.h"
28 #include "llvm/Module.h"
29 #include "llvm/Type.h"
30 #include "llvm/Assembly/Writer.h"
31 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCAssembler.h"
36 #include "llvm/MC/MCContext.h"
37 #include "llvm/MC/MCInst.h"
38 #include "llvm/MC/MCSectionMachO.h"
39 #include "llvm/MC/MCObjectStreamer.h"
40 #include "llvm/MC/MCStreamer.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/Target/Mangler.h"
43 #include "llvm/Target/TargetData.h"
44 #include "llvm/Target/TargetMachine.h"
45 #include "llvm/ADT/SmallString.h"
46 #include "llvm/Support/CommandLine.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/TargetRegistry.h"
50 #include "llvm/Support/raw_ostream.h"
56 // Per section and per symbol attributes are not supported.
57 // To implement them we would need the ability to delay this emission
58 // until the assembly file is fully parsed/generated as only then do we
59 // know the symbol and section numbers.
60 class AttributeEmitter {
62 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
63 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
64 virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0;
65 virtual void Finish() = 0;
66 virtual ~AttributeEmitter() {}
69 class AsmAttributeEmitter : public AttributeEmitter {
73 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
74 void MaybeSwitchVendor(StringRef Vendor) { }
76 void EmitAttribute(unsigned Attribute, unsigned Value) {
77 Streamer.EmitRawText("\t.eabi_attribute " +
78 Twine(Attribute) + ", " + Twine(Value));
81 void EmitTextAttribute(unsigned Attribute, StringRef String) {
83 default: llvm_unreachable("Unsupported Text attribute in ASM Mode");
84 case ARMBuildAttrs::CPU_name:
85 Streamer.EmitRawText(StringRef("\t.cpu ") + String.lower());
87 /* GAS requires .fpu to be emitted regardless of EABI attribute */
88 case ARMBuildAttrs::Advanced_SIMD_arch:
89 case ARMBuildAttrs::VFP_arch:
90 Streamer.EmitRawText(StringRef("\t.fpu ") + String.lower());
97 class ObjectAttributeEmitter : public AttributeEmitter {
98 // This structure holds all attributes, accounting for
99 // their string/numeric value, so we can later emmit them
100 // in declaration order, keeping all in the same vector
101 struct AttributeItemType {
109 StringRef StringValue;
112 MCObjectStreamer &Streamer;
113 StringRef CurrentVendor;
114 SmallVector<AttributeItemType, 64> Contents;
116 // Account for the ULEB/String size of each item,
117 // not just the number of items
119 // FIXME: this should be in a more generic place, but
120 // getULEBSize() is in MCAsmInfo and will be moved to MCDwarf
121 size_t getULEBSize(int Value) {
125 Size += sizeof(int8_t); // Is this really necessary?
131 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
132 Streamer(Streamer_), CurrentVendor(""), ContentsSize(0) { }
134 void MaybeSwitchVendor(StringRef Vendor) {
135 assert(!Vendor.empty() && "Vendor cannot be empty.");
137 if (CurrentVendor.empty())
138 CurrentVendor = Vendor;
139 else if (CurrentVendor == Vendor)
144 CurrentVendor = Vendor;
146 assert(Contents.size() == 0);
149 void EmitAttribute(unsigned Attribute, unsigned Value) {
150 AttributeItemType attr = {
151 AttributeItemType::NumericAttribute,
156 ContentsSize += getULEBSize(Attribute);
157 ContentsSize += getULEBSize(Value);
158 Contents.push_back(attr);
161 void EmitTextAttribute(unsigned Attribute, StringRef String) {
162 AttributeItemType attr = {
163 AttributeItemType::TextAttribute,
168 ContentsSize += getULEBSize(Attribute);
170 ContentsSize += String.size()+1;
172 Contents.push_back(attr);
176 // Vendor size + Vendor name + '\0'
177 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
180 const size_t TagHeaderSize = 1 + 4;
182 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
183 Streamer.EmitBytes(CurrentVendor, 0);
184 Streamer.EmitIntValue(0, 1); // '\0'
186 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
187 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
189 // Size should have been accounted for already, now
190 // emit each field as its type (ULEB or String)
191 for (unsigned int i=0; i<Contents.size(); ++i) {
192 AttributeItemType item = Contents[i];
193 Streamer.EmitULEB128IntValue(item.Tag, 0);
195 default: llvm_unreachable("Invalid attribute type");
196 case AttributeItemType::NumericAttribute:
197 Streamer.EmitULEB128IntValue(item.IntValue, 0);
199 case AttributeItemType::TextAttribute:
200 Streamer.EmitBytes(item.StringValue.upper(), 0);
201 Streamer.EmitIntValue(0, 1); // '\0'
210 } // end of anonymous namespace
212 MachineLocation ARMAsmPrinter::
213 getDebugValueLocation(const MachineInstr *MI) const {
214 MachineLocation Location;
215 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
216 // Frame address. Currently handles register +- offset only.
217 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
218 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
220 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
225 /// EmitDwarfRegOp - Emit dwarf register operation.
226 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
227 const TargetRegisterInfo *RI = TM.getRegisterInfo();
228 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
229 AsmPrinter::EmitDwarfRegOp(MLoc);
231 unsigned Reg = MLoc.getReg();
232 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
233 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
234 // S registers are described as bit-pieces of a register
235 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
236 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
238 unsigned SReg = Reg - ARM::S0;
239 bool odd = SReg & 0x1;
240 unsigned Rx = 256 + (SReg >> 1);
242 OutStreamer.AddComment("DW_OP_regx for S register");
243 EmitInt8(dwarf::DW_OP_regx);
245 OutStreamer.AddComment(Twine(SReg));
249 OutStreamer.AddComment("DW_OP_bit_piece 32 32");
250 EmitInt8(dwarf::DW_OP_bit_piece);
254 OutStreamer.AddComment("DW_OP_bit_piece 32 0");
255 EmitInt8(dwarf::DW_OP_bit_piece);
259 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
260 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
261 // Q registers Q0-Q15 are described by composing two D registers together.
262 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1)
265 unsigned QReg = Reg - ARM::Q0;
266 unsigned D1 = 256 + 2 * QReg;
267 unsigned D2 = D1 + 1;
269 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
270 EmitInt8(dwarf::DW_OP_regx);
272 OutStreamer.AddComment("DW_OP_piece 8");
273 EmitInt8(dwarf::DW_OP_piece);
276 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
277 EmitInt8(dwarf::DW_OP_regx);
279 OutStreamer.AddComment("DW_OP_piece 8");
280 EmitInt8(dwarf::DW_OP_piece);
286 void ARMAsmPrinter::EmitFunctionBodyEnd() {
287 // Make sure to terminate any constant pools that were at the end
291 InConstantPool = false;
292 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
295 void ARMAsmPrinter::EmitFunctionEntryLabel() {
296 if (AFI->isThumbFunction()) {
297 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
298 OutStreamer.EmitThumbFunc(CurrentFnSym);
301 OutStreamer.EmitLabel(CurrentFnSym);
304 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
305 uint64_t Size = TM.getTargetData()->getTypeAllocSize(CV->getType());
306 assert(Size && "C++ constructor pointer had zero size!");
308 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
309 assert(GV && "C++ constructor pointer was not a GlobalValue!");
311 const MCExpr *E = MCSymbolRefExpr::Create(Mang->getSymbol(GV),
312 (Subtarget->isTargetDarwin()
313 ? MCSymbolRefExpr::VK_None
314 : MCSymbolRefExpr::VK_ARM_TARGET1),
317 OutStreamer.EmitValue(E, Size);
320 /// runOnMachineFunction - This uses the EmitInstruction()
321 /// method to print assembly for each instruction.
323 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
324 AFI = MF.getInfo<ARMFunctionInfo>();
325 MCP = MF.getConstantPool();
327 return AsmPrinter::runOnMachineFunction(MF);
330 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
331 raw_ostream &O, const char *Modifier) {
332 const MachineOperand &MO = MI->getOperand(OpNum);
333 unsigned TF = MO.getTargetFlags();
335 switch (MO.getType()) {
336 default: llvm_unreachable("<unknown operand type>");
337 case MachineOperand::MO_Register: {
338 unsigned Reg = MO.getReg();
339 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
340 assert(!MO.getSubReg() && "Subregs should be eliminated!");
341 O << ARMInstPrinter::getRegisterName(Reg);
344 case MachineOperand::MO_Immediate: {
345 int64_t Imm = MO.getImm();
347 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
348 (TF == ARMII::MO_LO16))
350 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
351 (TF == ARMII::MO_HI16))
356 case MachineOperand::MO_MachineBasicBlock:
357 O << *MO.getMBB()->getSymbol();
359 case MachineOperand::MO_GlobalAddress: {
360 const GlobalValue *GV = MO.getGlobal();
361 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
362 (TF & ARMII::MO_LO16))
364 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
365 (TF & ARMII::MO_HI16))
367 O << *Mang->getSymbol(GV);
369 printOffset(MO.getOffset(), O);
370 if (TF == ARMII::MO_PLT)
374 case MachineOperand::MO_ExternalSymbol: {
375 O << *GetExternalSymbolSymbol(MO.getSymbolName());
376 if (TF == ARMII::MO_PLT)
380 case MachineOperand::MO_ConstantPoolIndex:
381 O << *GetCPISymbol(MO.getIndex());
383 case MachineOperand::MO_JumpTableIndex:
384 O << *GetJTISymbol(MO.getIndex());
389 //===--------------------------------------------------------------------===//
391 MCSymbol *ARMAsmPrinter::
392 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
393 const MachineBasicBlock *MBB) const {
394 SmallString<60> Name;
395 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
396 << getFunctionNumber() << '_' << uid << '_' << uid2
397 << "_set_" << MBB->getNumber();
398 return OutContext.GetOrCreateSymbol(Name.str());
401 MCSymbol *ARMAsmPrinter::
402 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
403 SmallString<60> Name;
404 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
405 << getFunctionNumber() << '_' << uid << '_' << uid2;
406 return OutContext.GetOrCreateSymbol(Name.str());
410 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
411 SmallString<60> Name;
412 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
413 << getFunctionNumber();
414 return OutContext.GetOrCreateSymbol(Name.str());
417 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
418 unsigned AsmVariant, const char *ExtraCode,
420 // Does this asm operand have a single letter operand modifier?
421 if (ExtraCode && ExtraCode[0]) {
422 if (ExtraCode[1] != 0) return true; // Unknown modifier.
424 switch (ExtraCode[0]) {
425 default: return true; // Unknown modifier.
426 case 'a': // Print as a memory address.
427 if (MI->getOperand(OpNum).isReg()) {
429 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
434 case 'c': // Don't print "#" before an immediate operand.
435 if (!MI->getOperand(OpNum).isImm())
437 O << MI->getOperand(OpNum).getImm();
439 case 'P': // Print a VFP double precision register.
440 case 'q': // Print a NEON quad precision register.
441 printOperand(MI, OpNum, O);
443 case 'y': // Print a VFP single precision register as indexed double.
444 // This uses the ordering of the alias table to get the first 'd' register
445 // that overlaps the 's' register. Also, s0 is an odd register, hence the
446 // odd modulus check below.
447 if (MI->getOperand(OpNum).isReg()) {
448 unsigned Reg = MI->getOperand(OpNum).getReg();
449 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
450 O << ARMInstPrinter::getRegisterName(TRI->getAliasSet(Reg)[0]) <<
451 (((Reg % 2) == 1) ? "[0]" : "[1]");
455 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
456 if (!MI->getOperand(OpNum).isImm())
458 O << ~(MI->getOperand(OpNum).getImm());
460 case 'L': // The low 16 bits of an immediate constant.
461 if (!MI->getOperand(OpNum).isImm())
463 O << (MI->getOperand(OpNum).getImm() & 0xffff);
465 case 'M': { // A register range suitable for LDM/STM.
466 if (!MI->getOperand(OpNum).isReg())
468 const MachineOperand &MO = MI->getOperand(OpNum);
469 unsigned RegBegin = MO.getReg();
470 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
471 // already got the operands in registers that are operands to the
472 // inline asm statement.
474 O << "{" << ARMInstPrinter::getRegisterName(RegBegin);
476 // FIXME: The register allocator not only may not have given us the
477 // registers in sequence, but may not be in ascending registers. This
478 // will require changes in the register allocator that'll need to be
479 // propagated down here if the operands change.
480 unsigned RegOps = OpNum + 1;
481 while (MI->getOperand(RegOps).isReg()) {
483 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
491 case 'R': // The most significant register of a pair.
492 case 'Q': { // The least significant register of a pair.
495 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
496 if (!FlagsOP.isImm())
498 unsigned Flags = FlagsOP.getImm();
499 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
502 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
503 if (RegOp >= MI->getNumOperands())
505 const MachineOperand &MO = MI->getOperand(RegOp);
508 unsigned Reg = MO.getReg();
509 O << ARMInstPrinter::getRegisterName(Reg);
513 case 'e': // The low doubleword register of a NEON quad register.
514 case 'f': { // The high doubleword register of a NEON quad register.
515 if (!MI->getOperand(OpNum).isReg())
517 unsigned Reg = MI->getOperand(OpNum).getReg();
518 if (!ARM::QPRRegClass.contains(Reg))
520 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
521 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
522 ARM::dsub_0 : ARM::dsub_1);
523 O << ARMInstPrinter::getRegisterName(SubReg);
527 // These modifiers are not yet supported.
528 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
529 case 'H': // The highest-numbered register of a pair.
534 printOperand(MI, OpNum, O);
538 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
539 unsigned OpNum, unsigned AsmVariant,
540 const char *ExtraCode,
542 // Does this asm operand have a single letter operand modifier?
543 if (ExtraCode && ExtraCode[0]) {
544 if (ExtraCode[1] != 0) return true; // Unknown modifier.
546 switch (ExtraCode[0]) {
547 case 'A': // A memory operand for a VLD1/VST1 instruction.
548 default: return true; // Unknown modifier.
549 case 'm': // The base register of a memory operand.
550 if (!MI->getOperand(OpNum).isReg())
552 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
557 const MachineOperand &MO = MI->getOperand(OpNum);
558 assert(MO.isReg() && "unexpected inline asm memory operand");
559 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
563 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
564 if (Subtarget->isTargetDarwin()) {
565 Reloc::Model RelocM = TM.getRelocationModel();
566 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
567 // Declare all the text sections up front (before the DWARF sections
568 // emitted by AsmPrinter::doInitialization) so the assembler will keep
569 // them together at the beginning of the object file. This helps
570 // avoid out-of-range branches that are due a fundamental limitation of
571 // the way symbol offsets are encoded with the current Darwin ARM
573 const TargetLoweringObjectFileMachO &TLOFMacho =
574 static_cast<const TargetLoweringObjectFileMachO &>(
575 getObjFileLowering());
576 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
577 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
578 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
579 if (RelocM == Reloc::DynamicNoPIC) {
580 const MCSection *sect =
581 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
582 MCSectionMachO::S_SYMBOL_STUBS,
583 12, SectionKind::getText());
584 OutStreamer.SwitchSection(sect);
586 const MCSection *sect =
587 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
588 MCSectionMachO::S_SYMBOL_STUBS,
589 16, SectionKind::getText());
590 OutStreamer.SwitchSection(sect);
592 const MCSection *StaticInitSect =
593 OutContext.getMachOSection("__TEXT", "__StaticInit",
594 MCSectionMachO::S_REGULAR |
595 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
596 SectionKind::getText());
597 OutStreamer.SwitchSection(StaticInitSect);
601 // Use unified assembler syntax.
602 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
604 // Emit ARM Build Attributes
605 if (Subtarget->isTargetELF())
610 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
611 if (Subtarget->isTargetDarwin()) {
612 // All darwin targets use mach-o.
613 const TargetLoweringObjectFileMachO &TLOFMacho =
614 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
615 MachineModuleInfoMachO &MMIMacho =
616 MMI->getObjFileInfo<MachineModuleInfoMachO>();
618 // Output non-lazy-pointers for external and common global variables.
619 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
621 if (!Stubs.empty()) {
622 // Switch with ".non_lazy_symbol_pointer" directive.
623 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
625 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
627 OutStreamer.EmitLabel(Stubs[i].first);
628 // .indirect_symbol _foo
629 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
630 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
633 // External to current translation unit.
634 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
636 // Internal to current translation unit.
638 // When we place the LSDA into the TEXT section, the type info
639 // pointers need to be indirect and pc-rel. We accomplish this by
640 // using NLPs; however, sometimes the types are local to the file.
641 // We need to fill in the value for the NLP in those cases.
642 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
644 4/*size*/, 0/*addrspace*/);
648 OutStreamer.AddBlankLine();
651 Stubs = MMIMacho.GetHiddenGVStubList();
652 if (!Stubs.empty()) {
653 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
655 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
657 OutStreamer.EmitLabel(Stubs[i].first);
659 OutStreamer.EmitValue(MCSymbolRefExpr::
660 Create(Stubs[i].second.getPointer(),
662 4/*size*/, 0/*addrspace*/);
666 OutStreamer.AddBlankLine();
669 // Funny Darwin hack: This flag tells the linker that no global symbols
670 // contain code that falls through to other global symbols (e.g. the obvious
671 // implementation of multiple entry points). If this doesn't occur, the
672 // linker can safely perform dead code stripping. Since LLVM never
673 // generates code that does this, it is always safe to set.
674 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
678 //===----------------------------------------------------------------------===//
679 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
681 // The following seem like one-off assembler flags, but they actually need
682 // to appear in the .ARM.attributes section in ELF.
683 // Instead of subclassing the MCELFStreamer, we do the work here.
685 void ARMAsmPrinter::emitAttributes() {
687 emitARMAttributeSection();
689 /* GAS expect .fpu to be emitted, regardless of VFP build attribute */
690 bool emitFPU = false;
691 AttributeEmitter *AttrEmitter;
692 if (OutStreamer.hasRawTextSupport()) {
693 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
696 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
697 AttrEmitter = new ObjectAttributeEmitter(O);
700 AttrEmitter->MaybeSwitchVendor("aeabi");
702 std::string CPUString = Subtarget->getCPUString();
704 if (CPUString == "cortex-a8" ||
705 Subtarget->isCortexA8()) {
706 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
707 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
708 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
709 ARMBuildAttrs::ApplicationProfile);
710 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
711 ARMBuildAttrs::Allowed);
712 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
713 ARMBuildAttrs::AllowThumb32);
714 // Fixme: figure out when this is emitted.
715 //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
716 // ARMBuildAttrs::AllowWMMXv1);
719 /// ADD additional Else-cases here!
720 } else if (CPUString == "xscale") {
721 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TEJ);
722 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
723 ARMBuildAttrs::Allowed);
724 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
725 ARMBuildAttrs::Allowed);
726 } else if (CPUString == "generic") {
727 // FIXME: Why these defaults?
728 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
729 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
730 ARMBuildAttrs::Allowed);
731 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
732 ARMBuildAttrs::Allowed);
735 if (Subtarget->hasNEON() && emitFPU) {
736 /* NEON is not exactly a VFP architecture, but GAS emit one of
737 * neon/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
738 if (Subtarget->hasVFP4())
739 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
742 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon");
743 /* If emitted for NEON, omit from VFP below, since you can have both
744 * NEON and VFP in build attributes but only one .fpu */
749 if (Subtarget->hasVFP4()) {
750 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
751 ARMBuildAttrs::AllowFPv4A);
753 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv4");
756 } else if (Subtarget->hasVFP3()) {
757 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
758 ARMBuildAttrs::AllowFPv3A);
760 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3");
763 } else if (Subtarget->hasVFP2()) {
764 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
765 ARMBuildAttrs::AllowFPv2);
767 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2");
770 /* TODO: ARMBuildAttrs::Allowed is not completely accurate,
771 * since NEON can have 1 (allowed) or 2 (MAC operations) */
772 if (Subtarget->hasNEON()) {
773 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
774 ARMBuildAttrs::Allowed);
777 // Signal various FP modes.
778 if (!TM.Options.UnsafeFPMath) {
779 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
780 ARMBuildAttrs::Allowed);
781 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
782 ARMBuildAttrs::Allowed);
785 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
786 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
787 ARMBuildAttrs::Allowed);
789 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
790 ARMBuildAttrs::AllowIEE754);
792 // FIXME: add more flags to ARMBuildAttrs.h
793 // 8-bytes alignment stuff.
794 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
795 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
797 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
798 if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard) {
799 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
800 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
802 // FIXME: Should we signal R9 usage?
804 if (Subtarget->hasDivide())
805 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
807 AttrEmitter->Finish();
811 void ARMAsmPrinter::emitARMAttributeSection() {
813 // [ <section-length> "vendor-name"
814 // [ <file-tag> <size> <attribute>*
815 // | <section-tag> <size> <section-number>* 0 <attribute>*
816 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
820 if (OutStreamer.hasRawTextSupport())
823 const ARMElfTargetObjectFile &TLOFELF =
824 static_cast<const ARMElfTargetObjectFile &>
825 (getObjFileLowering());
827 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
830 OutStreamer.EmitIntValue(0x41, 1);
833 //===----------------------------------------------------------------------===//
835 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
836 unsigned LabelId, MCContext &Ctx) {
838 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
839 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
843 static MCSymbolRefExpr::VariantKind
844 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
846 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
847 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
848 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
849 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
850 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
851 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
853 llvm_unreachable("Invalid ARMCPModifier!");
856 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
857 bool isIndirect = Subtarget->isTargetDarwin() &&
858 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
860 return Mang->getSymbol(GV);
862 // FIXME: Remove this when Darwin transition to @GOT like syntax.
863 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
864 MachineModuleInfoMachO &MMIMachO =
865 MMI->getObjFileInfo<MachineModuleInfoMachO>();
866 MachineModuleInfoImpl::StubValueTy &StubSym =
867 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
868 MMIMachO.getGVStubEntry(MCSym);
869 if (StubSym.getPointer() == 0)
870 StubSym = MachineModuleInfoImpl::
871 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
876 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
877 int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType());
879 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
882 if (ACPV->isLSDA()) {
883 SmallString<128> Str;
884 raw_svector_ostream OS(Str);
885 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
886 MCSym = OutContext.GetOrCreateSymbol(OS.str());
887 } else if (ACPV->isBlockAddress()) {
888 const BlockAddress *BA =
889 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
890 MCSym = GetBlockAddressSymbol(BA);
891 } else if (ACPV->isGlobalValue()) {
892 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
893 MCSym = GetARMGVSymbol(GV);
894 } else if (ACPV->isMachineBasicBlock()) {
895 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
896 MCSym = MBB->getSymbol();
898 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
899 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
900 MCSym = GetExternalSymbolSymbol(Sym);
903 // Create an MCSymbol for the reference.
905 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
908 if (ACPV->getPCAdjustment()) {
909 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
913 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
915 MCBinaryExpr::CreateAdd(PCRelExpr,
916 MCConstantExpr::Create(ACPV->getPCAdjustment(),
919 if (ACPV->mustAddCurrentAddress()) {
920 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
921 // label, so just emit a local label end reference that instead.
922 MCSymbol *DotSym = OutContext.CreateTempSymbol();
923 OutStreamer.EmitLabel(DotSym);
924 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
925 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
927 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
929 OutStreamer.EmitValue(Expr, Size);
932 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
933 unsigned Opcode = MI->getOpcode();
935 if (Opcode == ARM::BR_JTadd)
937 else if (Opcode == ARM::BR_JTm)
940 const MachineOperand &MO1 = MI->getOperand(OpNum);
941 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
942 unsigned JTI = MO1.getIndex();
944 // Emit a label for the jump table.
945 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
946 OutStreamer.EmitLabel(JTISymbol);
948 // Mark the jump table as data-in-code.
949 OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
951 // Emit each entry of the table.
952 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
953 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
954 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
956 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
957 MachineBasicBlock *MBB = JTBBs[i];
958 // Construct an MCExpr for the entry. We want a value of the form:
959 // (BasicBlockAddr - TableBeginAddr)
961 // For example, a table with entries jumping to basic blocks BB0 and BB1
964 // .word (LBB0 - LJTI_0_0)
965 // .word (LBB1 - LJTI_0_0)
966 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
968 if (TM.getRelocationModel() == Reloc::PIC_)
969 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
972 // If we're generating a table of Thumb addresses in static relocation
973 // model, we need to add one to keep interworking correctly.
974 else if (AFI->isThumbFunction())
975 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
977 OutStreamer.EmitValue(Expr, 4);
979 // Mark the end of jump table data-in-code region.
980 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
983 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
984 unsigned Opcode = MI->getOpcode();
985 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
986 const MachineOperand &MO1 = MI->getOperand(OpNum);
987 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
988 unsigned JTI = MO1.getIndex();
990 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
991 OutStreamer.EmitLabel(JTISymbol);
993 // Emit each entry of the table.
994 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
995 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
996 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
997 unsigned OffsetWidth = 4;
998 if (MI->getOpcode() == ARM::t2TBB_JT) {
1000 // Mark the jump table as data-in-code.
1001 OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
1002 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
1004 // Mark the jump table as data-in-code.
1005 OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
1008 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1009 MachineBasicBlock *MBB = JTBBs[i];
1010 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
1012 // If this isn't a TBB or TBH, the entries are direct branch instructions.
1013 if (OffsetWidth == 4) {
1015 BrInst.setOpcode(ARM::t2B);
1016 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
1017 BrInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1018 BrInst.addOperand(MCOperand::CreateReg(0));
1019 OutStreamer.EmitInstruction(BrInst);
1022 // Otherwise it's an offset from the dispatch instruction. Construct an
1023 // MCExpr for the entry. We want a value of the form:
1024 // (BasicBlockAddr - TableBeginAddr) / 2
1026 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1029 // .byte (LBB0 - LJTI_0_0) / 2
1030 // .byte (LBB1 - LJTI_0_0) / 2
1031 const MCExpr *Expr =
1032 MCBinaryExpr::CreateSub(MBBSymbolExpr,
1033 MCSymbolRefExpr::Create(JTISymbol, OutContext),
1035 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
1037 OutStreamer.EmitValue(Expr, OffsetWidth);
1039 // Mark the end of jump table data-in-code region. 32-bit offsets use
1040 // actual branch instructions here, so we don't mark those as a data-region
1042 if (OffsetWidth != 4)
1043 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1046 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
1048 unsigned NOps = MI->getNumOperands();
1050 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
1051 // cast away const; DIetc do not take const operands for some reason.
1052 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
1055 // Frame address. Currently handles register +- offset only.
1056 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
1057 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
1060 printOperand(MI, NOps-2, OS);
1063 static void populateADROperands(MCInst &Inst, unsigned Dest,
1064 const MCSymbol *Label,
1065 unsigned pred, unsigned ccreg,
1067 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx);
1068 Inst.addOperand(MCOperand::CreateReg(Dest));
1069 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1070 // Add predicate operands.
1071 Inst.addOperand(MCOperand::CreateImm(pred));
1072 Inst.addOperand(MCOperand::CreateReg(ccreg));
1075 void ARMAsmPrinter::EmitPatchedInstruction(const MachineInstr *MI,
1079 // Emit the instruction as usual, just patch the opcode.
1080 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1081 TmpInst.setOpcode(Opcode);
1082 OutStreamer.EmitInstruction(TmpInst);
1085 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1086 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1087 "Only instruction which are involved into frame setup code are allowed");
1089 const MachineFunction &MF = *MI->getParent()->getParent();
1090 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
1091 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1093 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1094 unsigned Opc = MI->getOpcode();
1095 unsigned SrcReg, DstReg;
1097 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1098 // Two special cases:
1099 // 1) tPUSH does not have src/dst regs.
1100 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1101 // load. Yes, this is pretty fragile, but for now I don't see better
1103 SrcReg = DstReg = ARM::SP;
1105 SrcReg = MI->getOperand(1).getReg();
1106 DstReg = MI->getOperand(0).getReg();
1109 // Try to figure out the unwinding opcode out of src / dst regs.
1110 if (MI->mayStore()) {
1112 assert(DstReg == ARM::SP &&
1113 "Only stack pointer as a destination reg is supported");
1115 SmallVector<unsigned, 4> RegList;
1116 // Skip src & dst reg, and pred ops.
1117 unsigned StartOp = 2 + 2;
1118 // Use all the operands.
1119 unsigned NumOffset = 0;
1124 llvm_unreachable("Unsupported opcode for unwinding information");
1126 // Special case here: no src & dst reg, but two extra imp ops.
1127 StartOp = 2; NumOffset = 2;
1128 case ARM::STMDB_UPD:
1129 case ARM::t2STMDB_UPD:
1130 case ARM::VSTMDDB_UPD:
1131 assert(SrcReg == ARM::SP &&
1132 "Only stack pointer as a source reg is supported");
1133 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1135 RegList.push_back(MI->getOperand(i).getReg());
1137 case ARM::STR_PRE_IMM:
1138 case ARM::STR_PRE_REG:
1139 case ARM::t2STR_PRE:
1140 assert(MI->getOperand(2).getReg() == ARM::SP &&
1141 "Only stack pointer as a source reg is supported");
1142 RegList.push_back(SrcReg);
1145 OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1147 // Changes of stack / frame pointer.
1148 if (SrcReg == ARM::SP) {
1153 llvm_unreachable("Unsupported opcode for unwinding information");
1159 Offset = -MI->getOperand(2).getImm();
1163 Offset = MI->getOperand(2).getImm();
1166 Offset = MI->getOperand(2).getImm()*4;
1170 Offset = -MI->getOperand(2).getImm()*4;
1172 case ARM::tLDRpci: {
1173 // Grab the constpool index and check, whether it corresponds to
1174 // original or cloned constpool entry.
1175 unsigned CPI = MI->getOperand(1).getIndex();
1176 const MachineConstantPool *MCP = MF.getConstantPool();
1177 if (CPI >= MCP->getConstants().size())
1178 CPI = AFI.getOriginalCPIdx(CPI);
1179 assert(CPI != -1U && "Invalid constpool index");
1181 // Derive the actual offset.
1182 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1183 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1184 // FIXME: Check for user, it should be "add" instruction!
1185 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1190 if (DstReg == FramePtr && FramePtr != ARM::SP)
1191 // Set-up of the frame pointer. Positive values correspond to "add"
1193 OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset);
1194 else if (DstReg == ARM::SP) {
1195 // Change of SP by an offset. Positive values correspond to "sub"
1197 OutStreamer.EmitPad(Offset);
1200 llvm_unreachable("Unsupported opcode for unwinding information");
1202 } else if (DstReg == ARM::SP) {
1203 // FIXME: .movsp goes here
1205 llvm_unreachable("Unsupported opcode for unwinding information");
1209 llvm_unreachable("Unsupported opcode for unwinding information");
1214 extern cl::opt<bool> EnableARMEHABI;
1216 // Simple pseudo-instructions have their lowering (with expansion to real
1217 // instructions) auto-generated.
1218 #include "ARMGenMCPseudoLowering.inc"
1220 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1221 // If we just ended a constant pool, mark it as such.
1222 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1223 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1224 InConstantPool = false;
1227 // Emit unwinding stuff for frame-related instructions
1228 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1229 EmitUnwindingInstruction(MI);
1231 // Do any auto-generated pseudo lowerings.
1232 if (emitPseudoExpansionLowering(OutStreamer, MI))
1235 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1236 "Pseudo flag setting opcode should be expanded early");
1238 // Check for manual lowerings.
1239 unsigned Opc = MI->getOpcode();
1241 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1242 case ARM::DBG_VALUE: {
1243 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
1244 SmallString<128> TmpStr;
1245 raw_svector_ostream OS(TmpStr);
1246 PrintDebugValueComment(MI, OS);
1247 OutStreamer.EmitRawText(StringRef(OS.str()));
1252 case ARM::tLEApcrel:
1253 case ARM::t2LEApcrel: {
1254 // FIXME: Need to also handle globals and externals
1256 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
1257 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1259 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1260 GetCPISymbol(MI->getOperand(1).getIndex()),
1261 MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
1263 OutStreamer.EmitInstruction(TmpInst);
1266 case ARM::LEApcrelJT:
1267 case ARM::tLEApcrelJT:
1268 case ARM::t2LEApcrelJT: {
1270 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
1271 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1273 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1274 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1275 MI->getOperand(2).getImm()),
1276 MI->getOperand(3).getImm(), MI->getOperand(4).getReg(),
1278 OutStreamer.EmitInstruction(TmpInst);
1281 // Darwin call instructions are just normal call instructions with different
1282 // clobber semantics (they clobber R9).
1283 case ARM::BX_CALL: {
1286 TmpInst.setOpcode(ARM::MOVr);
1287 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1288 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1289 // Add predicate operands.
1290 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1291 TmpInst.addOperand(MCOperand::CreateReg(0));
1292 // Add 's' bit operand (always reg0 for this)
1293 TmpInst.addOperand(MCOperand::CreateReg(0));
1294 OutStreamer.EmitInstruction(TmpInst);
1298 TmpInst.setOpcode(ARM::BX);
1299 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1300 OutStreamer.EmitInstruction(TmpInst);
1304 case ARM::tBX_CALL: {
1307 TmpInst.setOpcode(ARM::tMOVr);
1308 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1309 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1310 // Add predicate operands.
1311 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1312 TmpInst.addOperand(MCOperand::CreateReg(0));
1313 OutStreamer.EmitInstruction(TmpInst);
1317 TmpInst.setOpcode(ARM::tBX);
1318 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1319 // Add predicate operands.
1320 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1321 TmpInst.addOperand(MCOperand::CreateReg(0));
1322 OutStreamer.EmitInstruction(TmpInst);
1326 case ARM::BMOVPCRX_CALL: {
1329 TmpInst.setOpcode(ARM::MOVr);
1330 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1331 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1332 // Add predicate operands.
1333 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1334 TmpInst.addOperand(MCOperand::CreateReg(0));
1335 // Add 's' bit operand (always reg0 for this)
1336 TmpInst.addOperand(MCOperand::CreateReg(0));
1337 OutStreamer.EmitInstruction(TmpInst);
1341 TmpInst.setOpcode(ARM::MOVr);
1342 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1343 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1344 // Add predicate operands.
1345 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1346 TmpInst.addOperand(MCOperand::CreateReg(0));
1347 // Add 's' bit operand (always reg0 for this)
1348 TmpInst.addOperand(MCOperand::CreateReg(0));
1349 OutStreamer.EmitInstruction(TmpInst);
1353 case ARM::BMOVPCB_CALL: {
1356 TmpInst.setOpcode(ARM::MOVr);
1357 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1358 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1359 // Add predicate operands.
1360 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1361 TmpInst.addOperand(MCOperand::CreateReg(0));
1362 // Add 's' bit operand (always reg0 for this)
1363 TmpInst.addOperand(MCOperand::CreateReg(0));
1364 OutStreamer.EmitInstruction(TmpInst);
1368 TmpInst.setOpcode(ARM::Bcc);
1369 const GlobalValue *GV = MI->getOperand(0).getGlobal();
1370 MCSymbol *GVSym = Mang->getSymbol(GV);
1371 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1372 TmpInst.addOperand(MCOperand::CreateExpr(GVSymExpr));
1373 // Add predicate operands.
1374 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1375 TmpInst.addOperand(MCOperand::CreateReg(0));
1376 OutStreamer.EmitInstruction(TmpInst);
1380 case ARM::t2BMOVPCB_CALL: {
1383 TmpInst.setOpcode(ARM::tMOVr);
1384 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1385 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1386 // Add predicate operands.
1387 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1388 TmpInst.addOperand(MCOperand::CreateReg(0));
1389 OutStreamer.EmitInstruction(TmpInst);
1393 TmpInst.setOpcode(ARM::t2B);
1394 const GlobalValue *GV = MI->getOperand(0).getGlobal();
1395 MCSymbol *GVSym = Mang->getSymbol(GV);
1396 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1397 TmpInst.addOperand(MCOperand::CreateExpr(GVSymExpr));
1398 // Add predicate operands.
1399 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1400 TmpInst.addOperand(MCOperand::CreateReg(0));
1401 OutStreamer.EmitInstruction(TmpInst);
1405 case ARM::MOVi16_ga_pcrel:
1406 case ARM::t2MOVi16_ga_pcrel: {
1408 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1409 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1411 unsigned TF = MI->getOperand(1).getTargetFlags();
1412 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
1413 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1414 MCSymbol *GVSym = GetARMGVSymbol(GV);
1415 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1417 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1418 getFunctionNumber(),
1419 MI->getOperand(2).getImm(), OutContext);
1420 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1421 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1422 const MCExpr *PCRelExpr =
1423 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1424 MCBinaryExpr::CreateAdd(LabelSymExpr,
1425 MCConstantExpr::Create(PCAdj, OutContext),
1426 OutContext), OutContext), OutContext);
1427 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1429 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1430 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1433 // Add predicate operands.
1434 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1435 TmpInst.addOperand(MCOperand::CreateReg(0));
1436 // Add 's' bit operand (always reg0 for this)
1437 TmpInst.addOperand(MCOperand::CreateReg(0));
1438 OutStreamer.EmitInstruction(TmpInst);
1441 case ARM::MOVTi16_ga_pcrel:
1442 case ARM::t2MOVTi16_ga_pcrel: {
1444 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1445 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1446 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1447 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1449 unsigned TF = MI->getOperand(2).getTargetFlags();
1450 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
1451 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1452 MCSymbol *GVSym = GetARMGVSymbol(GV);
1453 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1455 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1456 getFunctionNumber(),
1457 MI->getOperand(3).getImm(), OutContext);
1458 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1459 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1460 const MCExpr *PCRelExpr =
1461 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1462 MCBinaryExpr::CreateAdd(LabelSymExpr,
1463 MCConstantExpr::Create(PCAdj, OutContext),
1464 OutContext), OutContext), OutContext);
1465 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1467 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1468 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1470 // Add predicate operands.
1471 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1472 TmpInst.addOperand(MCOperand::CreateReg(0));
1473 // Add 's' bit operand (always reg0 for this)
1474 TmpInst.addOperand(MCOperand::CreateReg(0));
1475 OutStreamer.EmitInstruction(TmpInst);
1478 case ARM::tPICADD: {
1479 // This is a pseudo op for a label + instruction sequence, which looks like:
1482 // This adds the address of LPC0 to r0.
1485 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1486 getFunctionNumber(), MI->getOperand(2).getImm(),
1489 // Form and emit the add.
1491 AddInst.setOpcode(ARM::tADDhirr);
1492 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1493 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1494 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1495 // Add predicate operands.
1496 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1497 AddInst.addOperand(MCOperand::CreateReg(0));
1498 OutStreamer.EmitInstruction(AddInst);
1502 // This is a pseudo op for a label + instruction sequence, which looks like:
1505 // This adds the address of LPC0 to r0.
1508 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1509 getFunctionNumber(), MI->getOperand(2).getImm(),
1512 // Form and emit the add.
1514 AddInst.setOpcode(ARM::ADDrr);
1515 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1516 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1517 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1518 // Add predicate operands.
1519 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1520 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1521 // Add 's' bit operand (always reg0 for this)
1522 AddInst.addOperand(MCOperand::CreateReg(0));
1523 OutStreamer.EmitInstruction(AddInst);
1533 case ARM::PICLDRSH: {
1534 // This is a pseudo op for a label + instruction sequence, which looks like:
1537 // The LCP0 label is referenced by a constant pool entry in order to get
1538 // a PC-relative address at the ldr instruction.
1541 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1542 getFunctionNumber(), MI->getOperand(2).getImm(),
1545 // Form and emit the load
1547 switch (MI->getOpcode()) {
1549 llvm_unreachable("Unexpected opcode!");
1550 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1551 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1552 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1553 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1554 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1555 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1556 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1557 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1560 LdStInst.setOpcode(Opcode);
1561 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1562 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
1563 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1564 LdStInst.addOperand(MCOperand::CreateImm(0));
1565 // Add predicate operands.
1566 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1567 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1568 OutStreamer.EmitInstruction(LdStInst);
1572 case ARM::CONSTPOOL_ENTRY: {
1573 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1574 /// in the function. The first operand is the ID# for this instruction, the
1575 /// second is the index into the MachineConstantPool that this is, the third
1576 /// is the size in bytes of this constant pool entry.
1577 /// The required alignment is specified on the basic block holding this MI.
1578 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1579 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1581 // If this is the first entry of the pool, mark it.
1582 if (!InConstantPool) {
1583 OutStreamer.EmitDataRegion(MCDR_DataRegion);
1584 InConstantPool = true;
1587 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1589 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1590 if (MCPE.isMachineConstantPoolEntry())
1591 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1593 EmitGlobalConstant(MCPE.Val.ConstVal);
1596 case ARM::t2BR_JT: {
1597 // Lower and emit the instruction itself, then the jump table following it.
1599 TmpInst.setOpcode(ARM::tMOVr);
1600 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1601 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1602 // Add predicate operands.
1603 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1604 TmpInst.addOperand(MCOperand::CreateReg(0));
1605 OutStreamer.EmitInstruction(TmpInst);
1606 // Output the data for the jump table itself
1610 case ARM::t2TBB_JT: {
1611 // Lower and emit the instruction itself, then the jump table following it.
1614 TmpInst.setOpcode(ARM::t2TBB);
1615 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1616 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1617 // Add predicate operands.
1618 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1619 TmpInst.addOperand(MCOperand::CreateReg(0));
1620 OutStreamer.EmitInstruction(TmpInst);
1621 // Output the data for the jump table itself
1623 // Make sure the next instruction is 2-byte aligned.
1627 case ARM::t2TBH_JT: {
1628 // Lower and emit the instruction itself, then the jump table following it.
1631 TmpInst.setOpcode(ARM::t2TBH);
1632 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1633 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1634 // Add predicate operands.
1635 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1636 TmpInst.addOperand(MCOperand::CreateReg(0));
1637 OutStreamer.EmitInstruction(TmpInst);
1638 // Output the data for the jump table itself
1644 // Lower and emit the instruction itself, then the jump table following it.
1647 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1648 ARM::MOVr : ARM::tMOVr;
1649 TmpInst.setOpcode(Opc);
1650 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1651 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1652 // Add predicate operands.
1653 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1654 TmpInst.addOperand(MCOperand::CreateReg(0));
1655 // Add 's' bit operand (always reg0 for this)
1656 if (Opc == ARM::MOVr)
1657 TmpInst.addOperand(MCOperand::CreateReg(0));
1658 OutStreamer.EmitInstruction(TmpInst);
1660 // Make sure the Thumb jump table is 4-byte aligned.
1661 if (Opc == ARM::tMOVr)
1664 // Output the data for the jump table itself
1669 // Lower and emit the instruction itself, then the jump table following it.
1672 if (MI->getOperand(1).getReg() == 0) {
1674 TmpInst.setOpcode(ARM::LDRi12);
1675 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1676 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1677 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1679 TmpInst.setOpcode(ARM::LDRrs);
1680 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1681 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1682 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1683 TmpInst.addOperand(MCOperand::CreateImm(0));
1685 // Add predicate operands.
1686 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1687 TmpInst.addOperand(MCOperand::CreateReg(0));
1688 OutStreamer.EmitInstruction(TmpInst);
1690 // Output the data for the jump table itself
1694 case ARM::BR_JTadd: {
1695 // Lower and emit the instruction itself, then the jump table following it.
1696 // add pc, target, idx
1698 TmpInst.setOpcode(ARM::ADDrr);
1699 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1700 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1701 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1702 // Add predicate operands.
1703 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1704 TmpInst.addOperand(MCOperand::CreateReg(0));
1705 // Add 's' bit operand (always reg0 for this)
1706 TmpInst.addOperand(MCOperand::CreateReg(0));
1707 OutStreamer.EmitInstruction(TmpInst);
1709 // Output the data for the jump table itself
1714 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1715 // FIXME: Remove this special case when they do.
1716 if (!Subtarget->isTargetDarwin()) {
1717 //.long 0xe7ffdefe @ trap
1718 uint32_t Val = 0xe7ffdefeUL;
1719 OutStreamer.AddComment("trap");
1720 OutStreamer.EmitIntValue(Val, 4);
1726 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1727 // FIXME: Remove this special case when they do.
1728 if (!Subtarget->isTargetDarwin()) {
1729 //.short 57086 @ trap
1730 uint16_t Val = 0xdefe;
1731 OutStreamer.AddComment("trap");
1732 OutStreamer.EmitIntValue(Val, 2);
1737 case ARM::t2Int_eh_sjlj_setjmp:
1738 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1739 case ARM::tInt_eh_sjlj_setjmp: {
1740 // Two incoming args: GPR:$src, GPR:$val
1743 // str $val, [$src, #4]
1748 unsigned SrcReg = MI->getOperand(0).getReg();
1749 unsigned ValReg = MI->getOperand(1).getReg();
1750 MCSymbol *Label = GetARMSJLJEHLabel();
1753 TmpInst.setOpcode(ARM::tMOVr);
1754 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1755 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1757 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1758 TmpInst.addOperand(MCOperand::CreateReg(0));
1759 OutStreamer.AddComment("eh_setjmp begin");
1760 OutStreamer.EmitInstruction(TmpInst);
1764 TmpInst.setOpcode(ARM::tADDi3);
1765 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1767 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1768 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1769 TmpInst.addOperand(MCOperand::CreateImm(7));
1771 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1772 TmpInst.addOperand(MCOperand::CreateReg(0));
1773 OutStreamer.EmitInstruction(TmpInst);
1777 TmpInst.setOpcode(ARM::tSTRi);
1778 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1779 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1780 // The offset immediate is #4. The operand value is scaled by 4 for the
1781 // tSTR instruction.
1782 TmpInst.addOperand(MCOperand::CreateImm(1));
1784 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1785 TmpInst.addOperand(MCOperand::CreateReg(0));
1786 OutStreamer.EmitInstruction(TmpInst);
1790 TmpInst.setOpcode(ARM::tMOVi8);
1791 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1792 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1793 TmpInst.addOperand(MCOperand::CreateImm(0));
1795 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1796 TmpInst.addOperand(MCOperand::CreateReg(0));
1797 OutStreamer.EmitInstruction(TmpInst);
1800 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1802 TmpInst.setOpcode(ARM::tB);
1803 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1804 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1805 TmpInst.addOperand(MCOperand::CreateReg(0));
1806 OutStreamer.EmitInstruction(TmpInst);
1810 TmpInst.setOpcode(ARM::tMOVi8);
1811 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1812 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1813 TmpInst.addOperand(MCOperand::CreateImm(1));
1815 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1816 TmpInst.addOperand(MCOperand::CreateReg(0));
1817 OutStreamer.AddComment("eh_setjmp end");
1818 OutStreamer.EmitInstruction(TmpInst);
1820 OutStreamer.EmitLabel(Label);
1824 case ARM::Int_eh_sjlj_setjmp_nofp:
1825 case ARM::Int_eh_sjlj_setjmp: {
1826 // Two incoming args: GPR:$src, GPR:$val
1828 // str $val, [$src, #+4]
1832 unsigned SrcReg = MI->getOperand(0).getReg();
1833 unsigned ValReg = MI->getOperand(1).getReg();
1837 TmpInst.setOpcode(ARM::ADDri);
1838 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1839 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1840 TmpInst.addOperand(MCOperand::CreateImm(8));
1842 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1843 TmpInst.addOperand(MCOperand::CreateReg(0));
1844 // 's' bit operand (always reg0 for this).
1845 TmpInst.addOperand(MCOperand::CreateReg(0));
1846 OutStreamer.AddComment("eh_setjmp begin");
1847 OutStreamer.EmitInstruction(TmpInst);
1851 TmpInst.setOpcode(ARM::STRi12);
1852 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1853 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1854 TmpInst.addOperand(MCOperand::CreateImm(4));
1856 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1857 TmpInst.addOperand(MCOperand::CreateReg(0));
1858 OutStreamer.EmitInstruction(TmpInst);
1862 TmpInst.setOpcode(ARM::MOVi);
1863 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1864 TmpInst.addOperand(MCOperand::CreateImm(0));
1866 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1867 TmpInst.addOperand(MCOperand::CreateReg(0));
1868 // 's' bit operand (always reg0 for this).
1869 TmpInst.addOperand(MCOperand::CreateReg(0));
1870 OutStreamer.EmitInstruction(TmpInst);
1874 TmpInst.setOpcode(ARM::ADDri);
1875 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1876 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1877 TmpInst.addOperand(MCOperand::CreateImm(0));
1879 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1880 TmpInst.addOperand(MCOperand::CreateReg(0));
1881 // 's' bit operand (always reg0 for this).
1882 TmpInst.addOperand(MCOperand::CreateReg(0));
1883 OutStreamer.EmitInstruction(TmpInst);
1887 TmpInst.setOpcode(ARM::MOVi);
1888 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1889 TmpInst.addOperand(MCOperand::CreateImm(1));
1891 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1892 TmpInst.addOperand(MCOperand::CreateReg(0));
1893 // 's' bit operand (always reg0 for this).
1894 TmpInst.addOperand(MCOperand::CreateReg(0));
1895 OutStreamer.AddComment("eh_setjmp end");
1896 OutStreamer.EmitInstruction(TmpInst);
1900 case ARM::Int_eh_sjlj_longjmp: {
1901 // ldr sp, [$src, #8]
1902 // ldr $scratch, [$src, #4]
1905 unsigned SrcReg = MI->getOperand(0).getReg();
1906 unsigned ScratchReg = MI->getOperand(1).getReg();
1909 TmpInst.setOpcode(ARM::LDRi12);
1910 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1911 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1912 TmpInst.addOperand(MCOperand::CreateImm(8));
1914 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1915 TmpInst.addOperand(MCOperand::CreateReg(0));
1916 OutStreamer.EmitInstruction(TmpInst);
1920 TmpInst.setOpcode(ARM::LDRi12);
1921 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1922 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1923 TmpInst.addOperand(MCOperand::CreateImm(4));
1925 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1926 TmpInst.addOperand(MCOperand::CreateReg(0));
1927 OutStreamer.EmitInstruction(TmpInst);
1931 TmpInst.setOpcode(ARM::LDRi12);
1932 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1933 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1934 TmpInst.addOperand(MCOperand::CreateImm(0));
1936 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1937 TmpInst.addOperand(MCOperand::CreateReg(0));
1938 OutStreamer.EmitInstruction(TmpInst);
1942 TmpInst.setOpcode(ARM::BX);
1943 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1945 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1946 TmpInst.addOperand(MCOperand::CreateReg(0));
1947 OutStreamer.EmitInstruction(TmpInst);
1951 case ARM::tInt_eh_sjlj_longjmp: {
1952 // ldr $scratch, [$src, #8]
1954 // ldr $scratch, [$src, #4]
1957 unsigned SrcReg = MI->getOperand(0).getReg();
1958 unsigned ScratchReg = MI->getOperand(1).getReg();
1961 TmpInst.setOpcode(ARM::tLDRi);
1962 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1963 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1964 // The offset immediate is #8. The operand value is scaled by 4 for the
1965 // tLDR instruction.
1966 TmpInst.addOperand(MCOperand::CreateImm(2));
1968 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1969 TmpInst.addOperand(MCOperand::CreateReg(0));
1970 OutStreamer.EmitInstruction(TmpInst);
1974 TmpInst.setOpcode(ARM::tMOVr);
1975 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1976 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1978 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1979 TmpInst.addOperand(MCOperand::CreateReg(0));
1980 OutStreamer.EmitInstruction(TmpInst);
1984 TmpInst.setOpcode(ARM::tLDRi);
1985 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1986 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1987 TmpInst.addOperand(MCOperand::CreateImm(1));
1989 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1990 TmpInst.addOperand(MCOperand::CreateReg(0));
1991 OutStreamer.EmitInstruction(TmpInst);
1995 TmpInst.setOpcode(ARM::tLDRi);
1996 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1997 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1998 TmpInst.addOperand(MCOperand::CreateImm(0));
2000 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
2001 TmpInst.addOperand(MCOperand::CreateReg(0));
2002 OutStreamer.EmitInstruction(TmpInst);
2006 TmpInst.setOpcode(ARM::tBX);
2007 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
2009 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
2010 TmpInst.addOperand(MCOperand::CreateReg(0));
2011 OutStreamer.EmitInstruction(TmpInst);
2018 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
2020 OutStreamer.EmitInstruction(TmpInst);
2023 //===----------------------------------------------------------------------===//
2024 // Target Registry Stuff
2025 //===----------------------------------------------------------------------===//
2027 // Force static initialization.
2028 extern "C" void LLVMInitializeARMAsmPrinter() {
2029 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
2030 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);