1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
16 #include "ARMAsmPrinter.h"
18 #include "ARMBuildAttrs.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMTargetMachine.h"
22 #include "ARMTargetObjectFile.h"
23 #include "InstPrinter/ARMInstPrinter.h"
24 #include "MCTargetDesc/ARMAddressingModes.h"
25 #include "MCTargetDesc/ARMMCExpr.h"
26 #include "llvm/ADT/SetVector.h"
27 #include "llvm/ADT/SmallString.h"
28 #include "llvm/Assembly/Writer.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
32 #include "llvm/DebugInfo.h"
33 #include "llvm/IR/Constants.h"
34 #include "llvm/IR/DataLayout.h"
35 #include "llvm/IR/Module.h"
36 #include "llvm/IR/Type.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/MC/MCAssembler.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCELFStreamer.h"
41 #include "llvm/MC/MCInst.h"
42 #include "llvm/MC/MCInstBuilder.h"
43 #include "llvm/MC/MCObjectStreamer.h"
44 #include "llvm/MC/MCSectionMachO.h"
45 #include "llvm/MC/MCStreamer.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ELF.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/TargetRegistry.h"
52 #include "llvm/Support/raw_ostream.h"
53 #include "llvm/Target/Mangler.h"
54 #include "llvm/Target/TargetMachine.h"
60 // Per section and per symbol attributes are not supported.
61 // To implement them we would need the ability to delay this emission
62 // until the assembly file is fully parsed/generated as only then do we
63 // know the symbol and section numbers.
64 class AttributeEmitter {
66 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
67 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
68 virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0;
69 virtual void Finish() = 0;
70 virtual ~AttributeEmitter() {}
73 class AsmAttributeEmitter : public AttributeEmitter {
77 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
78 void MaybeSwitchVendor(StringRef Vendor) { }
80 void EmitAttribute(unsigned Attribute, unsigned Value) {
81 Streamer.EmitRawText("\t.eabi_attribute " +
82 Twine(Attribute) + ", " + Twine(Value));
85 void EmitTextAttribute(unsigned Attribute, StringRef String) {
87 default: llvm_unreachable("Unsupported Text attribute in ASM Mode");
88 case ARMBuildAttrs::CPU_name:
89 Streamer.EmitRawText(StringRef("\t.cpu ") + String.lower());
91 /* GAS requires .fpu to be emitted regardless of EABI attribute */
92 case ARMBuildAttrs::Advanced_SIMD_arch:
93 case ARMBuildAttrs::VFP_arch:
94 Streamer.EmitRawText(StringRef("\t.fpu ") + String.lower());
101 class ObjectAttributeEmitter : public AttributeEmitter {
102 // This structure holds all attributes, accounting for
103 // their string/numeric value, so we can later emmit them
104 // in declaration order, keeping all in the same vector
105 struct AttributeItemType {
113 StringRef StringValue;
116 MCObjectStreamer &Streamer;
117 StringRef CurrentVendor;
118 SmallVector<AttributeItemType, 64> Contents;
120 // Account for the ULEB/String size of each item,
121 // not just the number of items
123 // FIXME: this should be in a more generic place, but
124 // getULEBSize() is in MCAsmInfo and will be moved to MCDwarf
125 size_t getULEBSize(int Value) {
129 Size += sizeof(int8_t); // Is this really necessary?
135 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
136 Streamer(Streamer_), CurrentVendor(""), ContentsSize(0) { }
138 void MaybeSwitchVendor(StringRef Vendor) {
139 assert(!Vendor.empty() && "Vendor cannot be empty.");
141 if (CurrentVendor.empty())
142 CurrentVendor = Vendor;
143 else if (CurrentVendor == Vendor)
148 CurrentVendor = Vendor;
150 assert(Contents.size() == 0);
153 void EmitAttribute(unsigned Attribute, unsigned Value) {
154 AttributeItemType attr = {
155 AttributeItemType::NumericAttribute,
160 ContentsSize += getULEBSize(Attribute);
161 ContentsSize += getULEBSize(Value);
162 Contents.push_back(attr);
165 void EmitTextAttribute(unsigned Attribute, StringRef String) {
166 AttributeItemType attr = {
167 AttributeItemType::TextAttribute,
172 ContentsSize += getULEBSize(Attribute);
174 ContentsSize += String.size()+1;
176 Contents.push_back(attr);
180 // Vendor size + Vendor name + '\0'
181 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
184 const size_t TagHeaderSize = 1 + 4;
186 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
187 Streamer.EmitBytes(CurrentVendor);
188 Streamer.EmitIntValue(0, 1); // '\0'
190 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
191 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
193 // Size should have been accounted for already, now
194 // emit each field as its type (ULEB or String)
195 for (unsigned int i=0; i<Contents.size(); ++i) {
196 AttributeItemType item = Contents[i];
197 Streamer.EmitULEB128IntValue(item.Tag);
199 default: llvm_unreachable("Invalid attribute type");
200 case AttributeItemType::NumericAttribute:
201 Streamer.EmitULEB128IntValue(item.IntValue);
203 case AttributeItemType::TextAttribute:
204 Streamer.EmitBytes(item.StringValue.upper());
205 Streamer.EmitIntValue(0, 1); // '\0'
214 } // end of anonymous namespace
216 /// EmitDwarfRegOp - Emit dwarf register operation.
217 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc,
218 bool Indirect) const {
219 const TargetRegisterInfo *RI = TM.getRegisterInfo();
220 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1) {
221 AsmPrinter::EmitDwarfRegOp(MLoc, Indirect);
224 assert(MLoc.isReg() && !Indirect &&
225 "This doesn't support offset/indirection - implement it if needed");
226 unsigned Reg = MLoc.getReg();
227 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
228 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
229 // S registers are described as bit-pieces of a register
230 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
231 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
233 unsigned SReg = Reg - ARM::S0;
234 bool odd = SReg & 0x1;
235 unsigned Rx = 256 + (SReg >> 1);
237 OutStreamer.AddComment("DW_OP_regx for S register");
238 EmitInt8(dwarf::DW_OP_regx);
240 OutStreamer.AddComment(Twine(SReg));
244 OutStreamer.AddComment("DW_OP_bit_piece 32 32");
245 EmitInt8(dwarf::DW_OP_bit_piece);
249 OutStreamer.AddComment("DW_OP_bit_piece 32 0");
250 EmitInt8(dwarf::DW_OP_bit_piece);
254 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
255 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
256 // Q registers Q0-Q15 are described by composing two D registers together.
257 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1)
260 unsigned QReg = Reg - ARM::Q0;
261 unsigned D1 = 256 + 2 * QReg;
262 unsigned D2 = D1 + 1;
264 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
265 EmitInt8(dwarf::DW_OP_regx);
267 OutStreamer.AddComment("DW_OP_piece 8");
268 EmitInt8(dwarf::DW_OP_piece);
271 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
272 EmitInt8(dwarf::DW_OP_regx);
274 OutStreamer.AddComment("DW_OP_piece 8");
275 EmitInt8(dwarf::DW_OP_piece);
280 void ARMAsmPrinter::EmitFunctionBodyEnd() {
281 // Make sure to terminate any constant pools that were at the end
285 InConstantPool = false;
286 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
289 void ARMAsmPrinter::EmitFunctionEntryLabel() {
290 if (AFI->isThumbFunction()) {
291 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
292 OutStreamer.EmitThumbFunc(CurrentFnSym);
295 OutStreamer.EmitLabel(CurrentFnSym);
298 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
299 uint64_t Size = TM.getDataLayout()->getTypeAllocSize(CV->getType());
300 assert(Size && "C++ constructor pointer had zero size!");
302 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
303 assert(GV && "C++ constructor pointer was not a GlobalValue!");
305 const MCExpr *E = MCSymbolRefExpr::Create(Mang->getSymbol(GV),
306 (Subtarget->isTargetDarwin()
307 ? MCSymbolRefExpr::VK_None
308 : MCSymbolRefExpr::VK_ARM_TARGET1),
311 OutStreamer.EmitValue(E, Size);
314 /// runOnMachineFunction - This uses the EmitInstruction()
315 /// method to print assembly for each instruction.
317 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
318 AFI = MF.getInfo<ARMFunctionInfo>();
319 MCP = MF.getConstantPool();
321 return AsmPrinter::runOnMachineFunction(MF);
324 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
325 raw_ostream &O, const char *Modifier) {
326 const MachineOperand &MO = MI->getOperand(OpNum);
327 unsigned TF = MO.getTargetFlags();
329 switch (MO.getType()) {
330 default: llvm_unreachable("<unknown operand type>");
331 case MachineOperand::MO_Register: {
332 unsigned Reg = MO.getReg();
333 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
334 assert(!MO.getSubReg() && "Subregs should be eliminated!");
335 if(ARM::GPRPairRegClass.contains(Reg)) {
336 const MachineFunction &MF = *MI->getParent()->getParent();
337 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
338 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
340 O << ARMInstPrinter::getRegisterName(Reg);
343 case MachineOperand::MO_Immediate: {
344 int64_t Imm = MO.getImm();
346 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
347 (TF == ARMII::MO_LO16))
349 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
350 (TF == ARMII::MO_HI16))
355 case MachineOperand::MO_MachineBasicBlock:
356 O << *MO.getMBB()->getSymbol();
358 case MachineOperand::MO_GlobalAddress: {
359 const GlobalValue *GV = MO.getGlobal();
360 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
361 (TF & ARMII::MO_LO16))
363 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
364 (TF & ARMII::MO_HI16))
366 O << *Mang->getSymbol(GV);
368 printOffset(MO.getOffset(), O);
369 if (TF == ARMII::MO_PLT)
373 case MachineOperand::MO_ExternalSymbol: {
374 O << *GetExternalSymbolSymbol(MO.getSymbolName());
375 if (TF == ARMII::MO_PLT)
379 case MachineOperand::MO_ConstantPoolIndex:
380 O << *GetCPISymbol(MO.getIndex());
382 case MachineOperand::MO_JumpTableIndex:
383 O << *GetJTISymbol(MO.getIndex());
388 //===--------------------------------------------------------------------===//
390 MCSymbol *ARMAsmPrinter::
391 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
392 SmallString<60> Name;
393 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
394 << getFunctionNumber() << '_' << uid << '_' << uid2;
395 return OutContext.GetOrCreateSymbol(Name.str());
399 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const {
400 SmallString<60> Name;
401 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
402 << getFunctionNumber();
403 return OutContext.GetOrCreateSymbol(Name.str());
406 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
407 unsigned AsmVariant, const char *ExtraCode,
409 // Does this asm operand have a single letter operand modifier?
410 if (ExtraCode && ExtraCode[0]) {
411 if (ExtraCode[1] != 0) return true; // Unknown modifier.
413 switch (ExtraCode[0]) {
415 // See if this is a generic print operand
416 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
417 case 'a': // Print as a memory address.
418 if (MI->getOperand(OpNum).isReg()) {
420 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
425 case 'c': // Don't print "#" before an immediate operand.
426 if (!MI->getOperand(OpNum).isImm())
428 O << MI->getOperand(OpNum).getImm();
430 case 'P': // Print a VFP double precision register.
431 case 'q': // Print a NEON quad precision register.
432 printOperand(MI, OpNum, O);
434 case 'y': // Print a VFP single precision register as indexed double.
435 if (MI->getOperand(OpNum).isReg()) {
436 unsigned Reg = MI->getOperand(OpNum).getReg();
437 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
438 // Find the 'd' register that has this 's' register as a sub-register,
439 // and determine the lane number.
440 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
441 if (!ARM::DPRRegClass.contains(*SR))
443 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
444 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
449 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
450 if (!MI->getOperand(OpNum).isImm())
452 O << ~(MI->getOperand(OpNum).getImm());
454 case 'L': // The low 16 bits of an immediate constant.
455 if (!MI->getOperand(OpNum).isImm())
457 O << (MI->getOperand(OpNum).getImm() & 0xffff);
459 case 'M': { // A register range suitable for LDM/STM.
460 if (!MI->getOperand(OpNum).isReg())
462 const MachineOperand &MO = MI->getOperand(OpNum);
463 unsigned RegBegin = MO.getReg();
464 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
465 // already got the operands in registers that are operands to the
466 // inline asm statement.
468 if (ARM::GPRPairRegClass.contains(RegBegin)) {
469 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
470 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
471 O << ARMInstPrinter::getRegisterName(Reg0) << ", ";;
472 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
474 O << ARMInstPrinter::getRegisterName(RegBegin);
476 // FIXME: The register allocator not only may not have given us the
477 // registers in sequence, but may not be in ascending registers. This
478 // will require changes in the register allocator that'll need to be
479 // propagated down here if the operands change.
480 unsigned RegOps = OpNum + 1;
481 while (MI->getOperand(RegOps).isReg()) {
483 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
491 case 'R': // The most significant register of a pair.
492 case 'Q': { // The least significant register of a pair.
495 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
496 if (!FlagsOP.isImm())
498 unsigned Flags = FlagsOP.getImm();
500 // This operand may not be the one that actually provides the register. If
501 // it's tied to a previous one then we should refer instead to that one
502 // for registers and their classes.
504 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
505 for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
506 unsigned OpFlags = MI->getOperand(OpNum).getImm();
507 OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
509 Flags = MI->getOperand(OpNum).getImm();
511 // Later code expects OpNum to be pointing at the register rather than
516 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
518 InlineAsm::hasRegClassConstraint(Flags, RC);
519 if (RC == ARM::GPRPairRegClassID) {
522 const MachineOperand &MO = MI->getOperand(OpNum);
525 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
526 unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
527 ARM::gsub_0 : ARM::gsub_1);
528 O << ARMInstPrinter::getRegisterName(Reg);
533 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
534 if (RegOp >= MI->getNumOperands())
536 const MachineOperand &MO = MI->getOperand(RegOp);
539 unsigned Reg = MO.getReg();
540 O << ARMInstPrinter::getRegisterName(Reg);
544 case 'e': // The low doubleword register of a NEON quad register.
545 case 'f': { // The high doubleword register of a NEON quad register.
546 if (!MI->getOperand(OpNum).isReg())
548 unsigned Reg = MI->getOperand(OpNum).getReg();
549 if (!ARM::QPRRegClass.contains(Reg))
551 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
552 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
553 ARM::dsub_0 : ARM::dsub_1);
554 O << ARMInstPrinter::getRegisterName(SubReg);
558 // This modifier is not yet supported.
559 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
561 case 'H': { // The highest-numbered register of a pair.
562 const MachineOperand &MO = MI->getOperand(OpNum);
565 const MachineFunction &MF = *MI->getParent()->getParent();
566 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
567 unsigned Reg = MO.getReg();
568 if(!ARM::GPRPairRegClass.contains(Reg))
570 Reg = TRI->getSubReg(Reg, ARM::gsub_1);
571 O << ARMInstPrinter::getRegisterName(Reg);
577 printOperand(MI, OpNum, O);
581 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
582 unsigned OpNum, unsigned AsmVariant,
583 const char *ExtraCode,
585 // Does this asm operand have a single letter operand modifier?
586 if (ExtraCode && ExtraCode[0]) {
587 if (ExtraCode[1] != 0) return true; // Unknown modifier.
589 switch (ExtraCode[0]) {
590 case 'A': // A memory operand for a VLD1/VST1 instruction.
591 default: return true; // Unknown modifier.
592 case 'm': // The base register of a memory operand.
593 if (!MI->getOperand(OpNum).isReg())
595 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
600 const MachineOperand &MO = MI->getOperand(OpNum);
601 assert(MO.isReg() && "unexpected inline asm memory operand");
602 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
606 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
607 if (Subtarget->isTargetDarwin()) {
608 Reloc::Model RelocM = TM.getRelocationModel();
609 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
610 // Declare all the text sections up front (before the DWARF sections
611 // emitted by AsmPrinter::doInitialization) so the assembler will keep
612 // them together at the beginning of the object file. This helps
613 // avoid out-of-range branches that are due a fundamental limitation of
614 // the way symbol offsets are encoded with the current Darwin ARM
616 const TargetLoweringObjectFileMachO &TLOFMacho =
617 static_cast<const TargetLoweringObjectFileMachO &>(
618 getObjFileLowering());
620 // Collect the set of sections our functions will go into.
621 SetVector<const MCSection *, SmallVector<const MCSection *, 8>,
622 SmallPtrSet<const MCSection *, 8> > TextSections;
623 // Default text section comes first.
624 TextSections.insert(TLOFMacho.getTextSection());
625 // Now any user defined text sections from function attributes.
626 for (Module::iterator F = M.begin(), e = M.end(); F != e; ++F)
627 if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage())
628 TextSections.insert(TLOFMacho.SectionForGlobal(F, Mang, TM));
629 // Now the coalescable sections.
630 TextSections.insert(TLOFMacho.getTextCoalSection());
631 TextSections.insert(TLOFMacho.getConstTextCoalSection());
633 // Emit the sections in the .s file header to fix the order.
634 for (unsigned i = 0, e = TextSections.size(); i != e; ++i)
635 OutStreamer.SwitchSection(TextSections[i]);
637 if (RelocM == Reloc::DynamicNoPIC) {
638 const MCSection *sect =
639 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
640 MCSectionMachO::S_SYMBOL_STUBS,
641 12, SectionKind::getText());
642 OutStreamer.SwitchSection(sect);
644 const MCSection *sect =
645 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
646 MCSectionMachO::S_SYMBOL_STUBS,
647 16, SectionKind::getText());
648 OutStreamer.SwitchSection(sect);
650 const MCSection *StaticInitSect =
651 OutContext.getMachOSection("__TEXT", "__StaticInit",
652 MCSectionMachO::S_REGULAR |
653 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
654 SectionKind::getText());
655 OutStreamer.SwitchSection(StaticInitSect);
659 // Use unified assembler syntax.
660 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
662 // Emit ARM Build Attributes
663 if (Subtarget->isTargetELF())
668 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
669 if (Subtarget->isTargetDarwin()) {
670 // All darwin targets use mach-o.
671 const TargetLoweringObjectFileMachO &TLOFMacho =
672 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
673 MachineModuleInfoMachO &MMIMacho =
674 MMI->getObjFileInfo<MachineModuleInfoMachO>();
676 // Output non-lazy-pointers for external and common global variables.
677 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
679 if (!Stubs.empty()) {
680 // Switch with ".non_lazy_symbol_pointer" directive.
681 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
683 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
685 OutStreamer.EmitLabel(Stubs[i].first);
686 // .indirect_symbol _foo
687 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
688 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
691 // External to current translation unit.
692 OutStreamer.EmitIntValue(0, 4/*size*/);
694 // Internal to current translation unit.
696 // When we place the LSDA into the TEXT section, the type info
697 // pointers need to be indirect and pc-rel. We accomplish this by
698 // using NLPs; however, sometimes the types are local to the file.
699 // We need to fill in the value for the NLP in those cases.
700 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
706 OutStreamer.AddBlankLine();
709 Stubs = MMIMacho.GetHiddenGVStubList();
710 if (!Stubs.empty()) {
711 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
713 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
715 OutStreamer.EmitLabel(Stubs[i].first);
717 OutStreamer.EmitValue(MCSymbolRefExpr::
718 Create(Stubs[i].second.getPointer(),
724 OutStreamer.AddBlankLine();
727 // Funny Darwin hack: This flag tells the linker that no global symbols
728 // contain code that falls through to other global symbols (e.g. the obvious
729 // implementation of multiple entry points). If this doesn't occur, the
730 // linker can safely perform dead code stripping. Since LLVM never
731 // generates code that does this, it is always safe to set.
732 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
734 // FIXME: This should eventually end up somewhere else where more
735 // intelligent flag decisions can be made. For now we are just maintaining
736 // the status quo for ARM and setting EF_ARM_EABI_VER5 as the default.
737 if (MCELFStreamer *MES = dyn_cast<MCELFStreamer>(&OutStreamer))
738 MES->getAssembler().setELFHeaderEFlags(ELF::EF_ARM_EABI_VER5);
741 //===----------------------------------------------------------------------===//
742 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
744 // The following seem like one-off assembler flags, but they actually need
745 // to appear in the .ARM.attributes section in ELF.
746 // Instead of subclassing the MCELFStreamer, we do the work here.
748 void ARMAsmPrinter::emitAttributes() {
750 emitARMAttributeSection();
752 /* GAS expect .fpu to be emitted, regardless of VFP build attribute */
753 bool emitFPU = false;
754 AttributeEmitter *AttrEmitter;
755 if (OutStreamer.hasRawTextSupport()) {
756 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
759 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
760 AttrEmitter = new ObjectAttributeEmitter(O);
763 AttrEmitter->MaybeSwitchVendor("aeabi");
765 std::string CPUString = Subtarget->getCPUString();
767 if (CPUString == "cortex-a8" ||
768 Subtarget->isCortexA8()) {
769 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
770 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
771 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
772 ARMBuildAttrs::ApplicationProfile);
773 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
774 ARMBuildAttrs::Allowed);
775 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
776 ARMBuildAttrs::AllowThumb32);
777 // Fixme: figure out when this is emitted.
778 //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
779 // ARMBuildAttrs::AllowWMMXv1);
782 /// ADD additional Else-cases here!
783 } else if (CPUString == "xscale") {
784 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TEJ);
785 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
786 ARMBuildAttrs::Allowed);
787 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
788 ARMBuildAttrs::Allowed);
789 } else if (Subtarget->hasV8Ops())
790 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v8);
791 else if (Subtarget->hasV7Ops()) {
792 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
793 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
794 ARMBuildAttrs::AllowThumb32);
795 } else if (Subtarget->hasV6T2Ops())
796 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v6T2);
797 else if (Subtarget->hasV6Ops())
798 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v6);
799 else if (Subtarget->hasV5TEOps())
800 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TE);
801 else if (Subtarget->hasV5TOps())
802 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5T);
803 else if (Subtarget->hasV4TOps())
804 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
806 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4);
808 if (Subtarget->hasNEON() && emitFPU) {
809 /* NEON is not exactly a VFP architecture, but GAS emit one of
810 * neon/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
811 if (Subtarget->hasVFP4())
812 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
815 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon");
816 /* If emitted for NEON, omit from VFP below, since you can have both
817 * NEON and VFP in build attributes but only one .fpu */
822 if (Subtarget->hasV8FP()) {
823 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
824 ARMBuildAttrs::AllowV8FPA);
826 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "v8fp");
828 } else if (Subtarget->hasVFP4()) {
829 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
830 ARMBuildAttrs::AllowFPv4A);
832 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv4");
835 } else if (Subtarget->hasVFP3()) {
836 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
837 ARMBuildAttrs::AllowFPv3A);
839 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3");
842 } else if (Subtarget->hasVFP2()) {
843 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
844 ARMBuildAttrs::AllowFPv2);
846 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2");
849 /* TODO: ARMBuildAttrs::Allowed is not completely accurate,
850 * since NEON can have 1 (allowed) or 2 (MAC operations) */
851 if (Subtarget->hasNEON()) {
852 if (Subtarget->hasV8Ops())
853 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
854 ARMBuildAttrs::AllowedNeonV8);
856 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
857 ARMBuildAttrs::Allowed);
860 // Signal various FP modes.
861 if (!TM.Options.UnsafeFPMath) {
862 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
863 ARMBuildAttrs::Allowed);
864 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
865 ARMBuildAttrs::Allowed);
868 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
869 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
870 ARMBuildAttrs::Allowed);
872 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
873 ARMBuildAttrs::AllowIEE754);
875 // FIXME: add more flags to ARMBuildAttrs.h
876 // 8-bytes alignment stuff.
877 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
878 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
880 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
881 if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard) {
882 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
883 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
885 // FIXME: Should we signal R9 usage?
887 if (Subtarget->hasDivide())
888 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
890 AttrEmitter->Finish();
894 void ARMAsmPrinter::emitARMAttributeSection() {
896 // [ <section-length> "vendor-name"
897 // [ <file-tag> <size> <attribute>*
898 // | <section-tag> <size> <section-number>* 0 <attribute>*
899 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
903 if (OutStreamer.hasRawTextSupport())
906 const ARMElfTargetObjectFile &TLOFELF =
907 static_cast<const ARMElfTargetObjectFile &>
908 (getObjFileLowering());
910 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
913 OutStreamer.EmitIntValue(0x41, 1);
916 //===----------------------------------------------------------------------===//
918 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
919 unsigned LabelId, MCContext &Ctx) {
921 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
922 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
926 static MCSymbolRefExpr::VariantKind
927 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
929 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
930 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
931 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
932 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
933 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
934 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
936 llvm_unreachable("Invalid ARMCPModifier!");
939 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
940 bool isIndirect = Subtarget->isTargetDarwin() &&
941 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
943 return Mang->getSymbol(GV);
945 // FIXME: Remove this when Darwin transition to @GOT like syntax.
946 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
947 MachineModuleInfoMachO &MMIMachO =
948 MMI->getObjFileInfo<MachineModuleInfoMachO>();
949 MachineModuleInfoImpl::StubValueTy &StubSym =
950 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
951 MMIMachO.getGVStubEntry(MCSym);
952 if (StubSym.getPointer() == 0)
953 StubSym = MachineModuleInfoImpl::
954 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
959 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
960 int Size = TM.getDataLayout()->getTypeAllocSize(MCPV->getType());
962 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
965 if (ACPV->isLSDA()) {
966 SmallString<128> Str;
967 raw_svector_ostream OS(Str);
968 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
969 MCSym = OutContext.GetOrCreateSymbol(OS.str());
970 } else if (ACPV->isBlockAddress()) {
971 const BlockAddress *BA =
972 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
973 MCSym = GetBlockAddressSymbol(BA);
974 } else if (ACPV->isGlobalValue()) {
975 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
976 MCSym = GetARMGVSymbol(GV);
977 } else if (ACPV->isMachineBasicBlock()) {
978 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
979 MCSym = MBB->getSymbol();
981 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
982 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
983 MCSym = GetExternalSymbolSymbol(Sym);
986 // Create an MCSymbol for the reference.
988 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
991 if (ACPV->getPCAdjustment()) {
992 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
996 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
998 MCBinaryExpr::CreateAdd(PCRelExpr,
999 MCConstantExpr::Create(ACPV->getPCAdjustment(),
1002 if (ACPV->mustAddCurrentAddress()) {
1003 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
1004 // label, so just emit a local label end reference that instead.
1005 MCSymbol *DotSym = OutContext.CreateTempSymbol();
1006 OutStreamer.EmitLabel(DotSym);
1007 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
1008 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
1010 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
1012 OutStreamer.EmitValue(Expr, Size);
1015 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
1016 unsigned Opcode = MI->getOpcode();
1018 if (Opcode == ARM::BR_JTadd)
1020 else if (Opcode == ARM::BR_JTm)
1023 const MachineOperand &MO1 = MI->getOperand(OpNum);
1024 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
1025 unsigned JTI = MO1.getIndex();
1027 // Emit a label for the jump table.
1028 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
1029 OutStreamer.EmitLabel(JTISymbol);
1031 // Mark the jump table as data-in-code.
1032 OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
1034 // Emit each entry of the table.
1035 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1036 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1037 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1039 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1040 MachineBasicBlock *MBB = JTBBs[i];
1041 // Construct an MCExpr for the entry. We want a value of the form:
1042 // (BasicBlockAddr - TableBeginAddr)
1044 // For example, a table with entries jumping to basic blocks BB0 and BB1
1047 // .word (LBB0 - LJTI_0_0)
1048 // .word (LBB1 - LJTI_0_0)
1049 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
1051 if (TM.getRelocationModel() == Reloc::PIC_)
1052 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
1055 // If we're generating a table of Thumb addresses in static relocation
1056 // model, we need to add one to keep interworking correctly.
1057 else if (AFI->isThumbFunction())
1058 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
1060 OutStreamer.EmitValue(Expr, 4);
1062 // Mark the end of jump table data-in-code region.
1063 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1066 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
1067 unsigned Opcode = MI->getOpcode();
1068 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
1069 const MachineOperand &MO1 = MI->getOperand(OpNum);
1070 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
1071 unsigned JTI = MO1.getIndex();
1073 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
1074 OutStreamer.EmitLabel(JTISymbol);
1076 // Emit each entry of the table.
1077 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1078 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1079 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1080 unsigned OffsetWidth = 4;
1081 if (MI->getOpcode() == ARM::t2TBB_JT) {
1083 // Mark the jump table as data-in-code.
1084 OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
1085 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
1087 // Mark the jump table as data-in-code.
1088 OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
1091 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1092 MachineBasicBlock *MBB = JTBBs[i];
1093 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
1095 // If this isn't a TBB or TBH, the entries are direct branch instructions.
1096 if (OffsetWidth == 4) {
1097 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2B)
1098 .addExpr(MBBSymbolExpr)
1103 // Otherwise it's an offset from the dispatch instruction. Construct an
1104 // MCExpr for the entry. We want a value of the form:
1105 // (BasicBlockAddr - TableBeginAddr) / 2
1107 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1110 // .byte (LBB0 - LJTI_0_0) / 2
1111 // .byte (LBB1 - LJTI_0_0) / 2
1112 const MCExpr *Expr =
1113 MCBinaryExpr::CreateSub(MBBSymbolExpr,
1114 MCSymbolRefExpr::Create(JTISymbol, OutContext),
1116 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
1118 OutStreamer.EmitValue(Expr, OffsetWidth);
1120 // Mark the end of jump table data-in-code region. 32-bit offsets use
1121 // actual branch instructions here, so we don't mark those as a data-region
1123 if (OffsetWidth != 4)
1124 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1127 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1128 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1129 "Only instruction which are involved into frame setup code are allowed");
1131 const MachineFunction &MF = *MI->getParent()->getParent();
1132 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
1133 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1135 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1136 unsigned Opc = MI->getOpcode();
1137 unsigned SrcReg, DstReg;
1139 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1140 // Two special cases:
1141 // 1) tPUSH does not have src/dst regs.
1142 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1143 // load. Yes, this is pretty fragile, but for now I don't see better
1145 SrcReg = DstReg = ARM::SP;
1147 SrcReg = MI->getOperand(1).getReg();
1148 DstReg = MI->getOperand(0).getReg();
1151 // Try to figure out the unwinding opcode out of src / dst regs.
1152 if (MI->mayStore()) {
1154 assert(DstReg == ARM::SP &&
1155 "Only stack pointer as a destination reg is supported");
1157 SmallVector<unsigned, 4> RegList;
1158 // Skip src & dst reg, and pred ops.
1159 unsigned StartOp = 2 + 2;
1160 // Use all the operands.
1161 unsigned NumOffset = 0;
1166 llvm_unreachable("Unsupported opcode for unwinding information");
1168 // Special case here: no src & dst reg, but two extra imp ops.
1169 StartOp = 2; NumOffset = 2;
1170 case ARM::STMDB_UPD:
1171 case ARM::t2STMDB_UPD:
1172 case ARM::VSTMDDB_UPD:
1173 assert(SrcReg == ARM::SP &&
1174 "Only stack pointer as a source reg is supported");
1175 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1177 const MachineOperand &MO = MI->getOperand(i);
1178 // Actually, there should never be any impdef stuff here. Skip it
1179 // temporary to workaround PR11902.
1180 if (MO.isImplicit())
1182 RegList.push_back(MO.getReg());
1185 case ARM::STR_PRE_IMM:
1186 case ARM::STR_PRE_REG:
1187 case ARM::t2STR_PRE:
1188 assert(MI->getOperand(2).getReg() == ARM::SP &&
1189 "Only stack pointer as a source reg is supported");
1190 RegList.push_back(SrcReg);
1193 OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1195 // Changes of stack / frame pointer.
1196 if (SrcReg == ARM::SP) {
1201 llvm_unreachable("Unsupported opcode for unwinding information");
1207 Offset = -MI->getOperand(2).getImm();
1211 Offset = MI->getOperand(2).getImm();
1214 Offset = MI->getOperand(2).getImm()*4;
1218 Offset = -MI->getOperand(2).getImm()*4;
1220 case ARM::tLDRpci: {
1221 // Grab the constpool index and check, whether it corresponds to
1222 // original or cloned constpool entry.
1223 unsigned CPI = MI->getOperand(1).getIndex();
1224 const MachineConstantPool *MCP = MF.getConstantPool();
1225 if (CPI >= MCP->getConstants().size())
1226 CPI = AFI.getOriginalCPIdx(CPI);
1227 assert(CPI != -1U && "Invalid constpool index");
1229 // Derive the actual offset.
1230 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1231 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1232 // FIXME: Check for user, it should be "add" instruction!
1233 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1238 if (DstReg == FramePtr && FramePtr != ARM::SP)
1239 // Set-up of the frame pointer. Positive values correspond to "add"
1241 OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset);
1242 else if (DstReg == ARM::SP) {
1243 // Change of SP by an offset. Positive values correspond to "sub"
1245 OutStreamer.EmitPad(Offset);
1248 llvm_unreachable("Unsupported opcode for unwinding information");
1250 } else if (DstReg == ARM::SP) {
1251 // FIXME: .movsp goes here
1253 llvm_unreachable("Unsupported opcode for unwinding information");
1257 llvm_unreachable("Unsupported opcode for unwinding information");
1262 extern cl::opt<bool> EnableARMEHABI;
1264 // Simple pseudo-instructions have their lowering (with expansion to real
1265 // instructions) auto-generated.
1266 #include "ARMGenMCPseudoLowering.inc"
1268 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1269 // If we just ended a constant pool, mark it as such.
1270 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1271 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1272 InConstantPool = false;
1275 // Emit unwinding stuff for frame-related instructions
1276 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1277 EmitUnwindingInstruction(MI);
1279 // Do any auto-generated pseudo lowerings.
1280 if (emitPseudoExpansionLowering(OutStreamer, MI))
1283 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1284 "Pseudo flag setting opcode should be expanded early");
1286 // Check for manual lowerings.
1287 unsigned Opc = MI->getOpcode();
1289 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1290 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1292 case ARM::tLEApcrel:
1293 case ARM::t2LEApcrel: {
1294 // FIXME: Need to also handle globals and externals
1295 MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1296 OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() ==
1297 ARM::t2LEApcrel ? ARM::t2ADR
1298 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1300 .addReg(MI->getOperand(0).getReg())
1301 .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
1302 // Add predicate operands.
1303 .addImm(MI->getOperand(2).getImm())
1304 .addReg(MI->getOperand(3).getReg()));
1307 case ARM::LEApcrelJT:
1308 case ARM::tLEApcrelJT:
1309 case ARM::t2LEApcrelJT: {
1310 MCSymbol *JTIPICSymbol =
1311 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1312 MI->getOperand(2).getImm());
1313 OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() ==
1314 ARM::t2LEApcrelJT ? ARM::t2ADR
1315 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1317 .addReg(MI->getOperand(0).getReg())
1318 .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
1319 // Add predicate operands.
1320 .addImm(MI->getOperand(3).getImm())
1321 .addReg(MI->getOperand(4).getReg()));
1324 // Darwin call instructions are just normal call instructions with different
1325 // clobber semantics (they clobber R9).
1326 case ARM::BX_CALL: {
1327 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1330 // Add predicate operands.
1333 // Add 's' bit operand (always reg0 for this)
1336 OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX)
1337 .addReg(MI->getOperand(0).getReg()));
1340 case ARM::tBX_CALL: {
1341 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1344 // Add predicate operands.
1348 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX)
1349 .addReg(MI->getOperand(0).getReg())
1350 // Add predicate operands.
1355 case ARM::BMOVPCRX_CALL: {
1356 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1359 // Add predicate operands.
1362 // Add 's' bit operand (always reg0 for this)
1365 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1367 .addReg(MI->getOperand(0).getReg())
1368 // Add predicate operands.
1371 // Add 's' bit operand (always reg0 for this)
1375 case ARM::BMOVPCB_CALL: {
1376 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1379 // Add predicate operands.
1382 // Add 's' bit operand (always reg0 for this)
1385 const GlobalValue *GV = MI->getOperand(0).getGlobal();
1386 MCSymbol *GVSym = Mang->getSymbol(GV);
1387 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1388 OutStreamer.EmitInstruction(MCInstBuilder(ARM::Bcc)
1390 // Add predicate operands.
1395 case ARM::MOVi16_ga_pcrel:
1396 case ARM::t2MOVi16_ga_pcrel: {
1398 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1399 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1401 unsigned TF = MI->getOperand(1).getTargetFlags();
1402 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
1403 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1404 MCSymbol *GVSym = GetARMGVSymbol(GV);
1405 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1407 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1408 getFunctionNumber(),
1409 MI->getOperand(2).getImm(), OutContext);
1410 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1411 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1412 const MCExpr *PCRelExpr =
1413 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1414 MCBinaryExpr::CreateAdd(LabelSymExpr,
1415 MCConstantExpr::Create(PCAdj, OutContext),
1416 OutContext), OutContext), OutContext);
1417 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1419 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1420 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1423 // Add predicate operands.
1424 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1425 TmpInst.addOperand(MCOperand::CreateReg(0));
1426 // Add 's' bit operand (always reg0 for this)
1427 TmpInst.addOperand(MCOperand::CreateReg(0));
1428 OutStreamer.EmitInstruction(TmpInst);
1431 case ARM::MOVTi16_ga_pcrel:
1432 case ARM::t2MOVTi16_ga_pcrel: {
1434 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1435 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1436 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1437 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1439 unsigned TF = MI->getOperand(2).getTargetFlags();
1440 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
1441 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1442 MCSymbol *GVSym = GetARMGVSymbol(GV);
1443 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1445 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1446 getFunctionNumber(),
1447 MI->getOperand(3).getImm(), OutContext);
1448 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1449 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1450 const MCExpr *PCRelExpr =
1451 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1452 MCBinaryExpr::CreateAdd(LabelSymExpr,
1453 MCConstantExpr::Create(PCAdj, OutContext),
1454 OutContext), OutContext), OutContext);
1455 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1457 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1458 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1460 // Add predicate operands.
1461 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1462 TmpInst.addOperand(MCOperand::CreateReg(0));
1463 // Add 's' bit operand (always reg0 for this)
1464 TmpInst.addOperand(MCOperand::CreateReg(0));
1465 OutStreamer.EmitInstruction(TmpInst);
1468 case ARM::tPICADD: {
1469 // This is a pseudo op for a label + instruction sequence, which looks like:
1472 // This adds the address of LPC0 to r0.
1475 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1476 getFunctionNumber(), MI->getOperand(2).getImm(),
1479 // Form and emit the add.
1480 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDhirr)
1481 .addReg(MI->getOperand(0).getReg())
1482 .addReg(MI->getOperand(0).getReg())
1484 // Add predicate operands.
1490 // This is a pseudo op for a label + instruction sequence, which looks like:
1493 // This adds the address of LPC0 to r0.
1496 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1497 getFunctionNumber(), MI->getOperand(2).getImm(),
1500 // Form and emit the add.
1501 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr)
1502 .addReg(MI->getOperand(0).getReg())
1504 .addReg(MI->getOperand(1).getReg())
1505 // Add predicate operands.
1506 .addImm(MI->getOperand(3).getImm())
1507 .addReg(MI->getOperand(4).getReg())
1508 // Add 's' bit operand (always reg0 for this)
1519 case ARM::PICLDRSH: {
1520 // This is a pseudo op for a label + instruction sequence, which looks like:
1523 // The LCP0 label is referenced by a constant pool entry in order to get
1524 // a PC-relative address at the ldr instruction.
1527 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1528 getFunctionNumber(), MI->getOperand(2).getImm(),
1531 // Form and emit the load
1533 switch (MI->getOpcode()) {
1535 llvm_unreachable("Unexpected opcode!");
1536 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1537 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1538 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1539 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1540 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1541 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1542 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1543 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1545 OutStreamer.EmitInstruction(MCInstBuilder(Opcode)
1546 .addReg(MI->getOperand(0).getReg())
1548 .addReg(MI->getOperand(1).getReg())
1550 // Add predicate operands.
1551 .addImm(MI->getOperand(3).getImm())
1552 .addReg(MI->getOperand(4).getReg()));
1556 case ARM::CONSTPOOL_ENTRY: {
1557 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1558 /// in the function. The first operand is the ID# for this instruction, the
1559 /// second is the index into the MachineConstantPool that this is, the third
1560 /// is the size in bytes of this constant pool entry.
1561 /// The required alignment is specified on the basic block holding this MI.
1562 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1563 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1565 // If this is the first entry of the pool, mark it.
1566 if (!InConstantPool) {
1567 OutStreamer.EmitDataRegion(MCDR_DataRegion);
1568 InConstantPool = true;
1571 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1573 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1574 if (MCPE.isMachineConstantPoolEntry())
1575 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1577 EmitGlobalConstant(MCPE.Val.ConstVal);
1580 case ARM::t2BR_JT: {
1581 // Lower and emit the instruction itself, then the jump table following it.
1582 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1584 .addReg(MI->getOperand(0).getReg())
1585 // Add predicate operands.
1589 // Output the data for the jump table itself
1593 case ARM::t2TBB_JT: {
1594 // Lower and emit the instruction itself, then the jump table following it.
1595 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBB)
1597 .addReg(MI->getOperand(0).getReg())
1598 // Add predicate operands.
1602 // Output the data for the jump table itself
1604 // Make sure the next instruction is 2-byte aligned.
1608 case ARM::t2TBH_JT: {
1609 // Lower and emit the instruction itself, then the jump table following it.
1610 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBH)
1612 .addReg(MI->getOperand(0).getReg())
1613 // Add predicate operands.
1617 // Output the data for the jump table itself
1623 // Lower and emit the instruction itself, then the jump table following it.
1626 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1627 ARM::MOVr : ARM::tMOVr;
1628 TmpInst.setOpcode(Opc);
1629 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1630 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1631 // Add predicate operands.
1632 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1633 TmpInst.addOperand(MCOperand::CreateReg(0));
1634 // Add 's' bit operand (always reg0 for this)
1635 if (Opc == ARM::MOVr)
1636 TmpInst.addOperand(MCOperand::CreateReg(0));
1637 OutStreamer.EmitInstruction(TmpInst);
1639 // Make sure the Thumb jump table is 4-byte aligned.
1640 if (Opc == ARM::tMOVr)
1643 // Output the data for the jump table itself
1648 // Lower and emit the instruction itself, then the jump table following it.
1651 if (MI->getOperand(1).getReg() == 0) {
1653 TmpInst.setOpcode(ARM::LDRi12);
1654 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1655 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1656 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1658 TmpInst.setOpcode(ARM::LDRrs);
1659 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1660 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1661 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1662 TmpInst.addOperand(MCOperand::CreateImm(0));
1664 // Add predicate operands.
1665 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1666 TmpInst.addOperand(MCOperand::CreateReg(0));
1667 OutStreamer.EmitInstruction(TmpInst);
1669 // Output the data for the jump table itself
1673 case ARM::BR_JTadd: {
1674 // Lower and emit the instruction itself, then the jump table following it.
1675 // add pc, target, idx
1676 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr)
1678 .addReg(MI->getOperand(0).getReg())
1679 .addReg(MI->getOperand(1).getReg())
1680 // Add predicate operands.
1683 // Add 's' bit operand (always reg0 for this)
1686 // Output the data for the jump table itself
1691 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1692 // FIXME: Remove this special case when they do.
1693 if (!Subtarget->isTargetDarwin()) {
1694 //.long 0xe7ffdefe @ trap
1695 uint32_t Val = 0xe7ffdefeUL;
1696 OutStreamer.AddComment("trap");
1697 OutStreamer.EmitIntValue(Val, 4);
1702 case ARM::TRAPNaCl: {
1703 //.long 0xe7fedef0 @ trap
1704 uint32_t Val = 0xe7fedef0UL;
1705 OutStreamer.AddComment("trap");
1706 OutStreamer.EmitIntValue(Val, 4);
1710 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1711 // FIXME: Remove this special case when they do.
1712 if (!Subtarget->isTargetDarwin()) {
1713 //.short 57086 @ trap
1714 uint16_t Val = 0xdefe;
1715 OutStreamer.AddComment("trap");
1716 OutStreamer.EmitIntValue(Val, 2);
1721 case ARM::t2Int_eh_sjlj_setjmp:
1722 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1723 case ARM::tInt_eh_sjlj_setjmp: {
1724 // Two incoming args: GPR:$src, GPR:$val
1727 // str $val, [$src, #4]
1732 unsigned SrcReg = MI->getOperand(0).getReg();
1733 unsigned ValReg = MI->getOperand(1).getReg();
1734 MCSymbol *Label = GetARMSJLJEHLabel();
1735 OutStreamer.AddComment("eh_setjmp begin");
1736 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1743 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDi3)
1753 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tSTRi)
1756 // The offset immediate is #4. The operand value is scaled by 4 for the
1757 // tSTR instruction.
1763 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8)
1771 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1772 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tB)
1773 .addExpr(SymbolExpr)
1777 OutStreamer.AddComment("eh_setjmp end");
1778 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8)
1786 OutStreamer.EmitLabel(Label);
1790 case ARM::Int_eh_sjlj_setjmp_nofp:
1791 case ARM::Int_eh_sjlj_setjmp: {
1792 // Two incoming args: GPR:$src, GPR:$val
1794 // str $val, [$src, #+4]
1798 unsigned SrcReg = MI->getOperand(0).getReg();
1799 unsigned ValReg = MI->getOperand(1).getReg();
1801 OutStreamer.AddComment("eh_setjmp begin");
1802 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri)
1809 // 's' bit operand (always reg0 for this).
1812 OutStreamer.EmitInstruction(MCInstBuilder(ARM::STRi12)
1820 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi)
1826 // 's' bit operand (always reg0 for this).
1829 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri)
1836 // 's' bit operand (always reg0 for this).
1839 OutStreamer.AddComment("eh_setjmp end");
1840 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi)
1846 // 's' bit operand (always reg0 for this).
1850 case ARM::Int_eh_sjlj_longjmp: {
1851 // ldr sp, [$src, #8]
1852 // ldr $scratch, [$src, #4]
1855 unsigned SrcReg = MI->getOperand(0).getReg();
1856 unsigned ScratchReg = MI->getOperand(1).getReg();
1857 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1865 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1873 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1881 OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX)
1888 case ARM::tInt_eh_sjlj_longjmp: {
1889 // ldr $scratch, [$src, #8]
1891 // ldr $scratch, [$src, #4]
1894 unsigned SrcReg = MI->getOperand(0).getReg();
1895 unsigned ScratchReg = MI->getOperand(1).getReg();
1896 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1899 // The offset immediate is #8. The operand value is scaled by 4 for the
1900 // tLDR instruction.
1906 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1913 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1921 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1929 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX)
1939 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1941 OutStreamer.EmitInstruction(TmpInst);
1944 //===----------------------------------------------------------------------===//
1945 // Target Registry Stuff
1946 //===----------------------------------------------------------------------===//
1948 // Force static initialization.
1949 extern "C" void LLVMInitializeARMAsmPrinter() {
1950 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1951 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);