1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARMAddressingModes.h"
12 #include "ARMFixupKinds.h"
13 #include "llvm/ADT/Twine.h"
14 #include "llvm/MC/MCAssembler.h"
15 #include "llvm/MC/MCDirectives.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCObjectFormat.h"
18 #include "llvm/MC/MCObjectWriter.h"
19 #include "llvm/MC/MCSectionELF.h"
20 #include "llvm/MC/MCSectionMachO.h"
21 #include "llvm/Object/MachOFormat.h"
22 #include "llvm/Support/ELF.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
25 #include "llvm/Target/TargetAsmBackend.h"
26 #include "llvm/Target/TargetRegistry.h"
30 class ARMAsmBackend : public TargetAsmBackend {
31 bool isThumbMode; // Currently emitting Thumb code.
33 ARMAsmBackend(const Target &T) : TargetAsmBackend(), isThumbMode(false) {}
35 bool MayNeedRelaxation(const MCInst &Inst) const;
37 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
39 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
41 void HandleAssemblerFlag(MCAssemblerFlag Flag) {
53 unsigned getPointerSize() const { return 4; }
54 bool isThumb() const { return isThumbMode; }
55 void setIsThumb(bool it) { isThumbMode = it; }
57 } // end anonymous namespace
59 bool ARMAsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
60 // FIXME: Thumb targets, different move constant targets..
64 void ARMAsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
65 assert(0 && "ARMAsmBackend::RelaxInstruction() unimplemented");
69 bool ARMAsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
71 assert (((Count & 1) == 0) && "Unaligned Nop data fragment!");
72 // FIXME: 0xbf00 is the ARMv7 value. For v6 and before, we'll need to
73 // use 0x46c0 (which is a 'mov r8, r8' insn).
75 for (uint64_t i = 0; i != Count; ++i)
81 for (uint64_t i = 0; i != Count; ++i)
82 OW->Write32(0xe1a00000);
86 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
89 llvm_unreachable("Unknown fixup kind!");
92 case ARM::fixup_arm_movt_hi16:
93 case ARM::fixup_arm_movw_lo16: {
94 unsigned Hi4 = (Value & 0xF000) >> 12;
95 unsigned Lo12 = Value & 0x0FFF;
98 Value = (Hi4 << 16) | (Lo12);
101 case ARM::fixup_arm_ldst_pcrel_12:
102 // ARM PC-relative values are offset by 8.
105 case ARM::fixup_t2_ldst_pcrel_12: {
106 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
109 if ((int64_t)Value < 0) {
113 assert ((Value < 4096) && "Out of range pc-relative fixup value!");
114 Value |= isAdd << 23;
116 // Same addressing mode as fixup_arm_pcrel_10,
117 // but with 16-bit halfwords swapped.
118 if (Kind == ARM::fixup_t2_ldst_pcrel_12) {
119 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
120 swapped |= (Value & 0x0000FFFF) << 16;
126 case ARM::fixup_thumb_adr_pcrel_10:
127 return ((Value - 4) >> 2) & 0xff;
128 case ARM::fixup_arm_adr_pcrel_12: {
129 // ARM PC-relative values are offset by 8.
131 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
132 if ((int64_t)Value < 0) {
136 assert(ARM_AM::getSOImmVal(Value) != -1 &&
137 "Out of range pc-relative fixup value!");
138 // Encode the immediate and shift the opcode into place.
139 return ARM_AM::getSOImmVal(Value) | (opc << 21);
142 case ARM::fixup_t2_adr_pcrel_12: {
145 if ((int64_t)Value < 0) {
150 uint32_t out = (opc << 21);
151 out |= (Value & 0x800) << 14;
152 out |= (Value & 0x700) << 4;
153 out |= (Value & 0x0FF);
155 uint64_t swapped = (out & 0xFFFF0000) >> 16;
156 swapped |= (out & 0x0000FFFF) << 16;
160 case ARM::fixup_arm_branch:
161 // These values don't encode the low two bits since they're always zero.
162 // Offset by 8 just as above.
163 return 0xffffff & ((Value - 8) >> 2);
164 case ARM::fixup_t2_uncondbranch: {
166 Value >>= 1; // Low bit is not encoded.
169 bool I = Value & 0x800000;
170 bool J1 = Value & 0x400000;
171 bool J2 = Value & 0x200000;
175 out |= I << 26; // S bit
176 out |= !J1 << 13; // J1 bit
177 out |= !J2 << 11; // J2 bit
178 out |= (Value & 0x1FF800) << 5; // imm6 field
179 out |= (Value & 0x0007FF); // imm11 field
181 uint64_t swapped = (out & 0xFFFF0000) >> 16;
182 swapped |= (out & 0x0000FFFF) << 16;
185 case ARM::fixup_t2_condbranch: {
187 Value >>= 1; // Low bit is not encoded.
190 out |= (Value & 0x80000) << 7; // S bit
191 out |= (Value & 0x40000) >> 7; // J2 bit
192 out |= (Value & 0x20000) >> 4; // J1 bit
193 out |= (Value & 0x1F800) << 5; // imm6 field
194 out |= (Value & 0x007FF); // imm11 field
196 uint32_t swapped = (out & 0xFFFF0000) >> 16;
197 swapped |= (out & 0x0000FFFF) << 16;
200 case ARM::fixup_arm_thumb_bl: {
201 // The value doesn't encode the low bit (always zero) and is offset by
202 // four. The value is encoded into disjoint bit positions in the destination
203 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit
205 // BL: xxxxxSIIIIIIIIII xxxxxIIIIIIIIIII
207 // Note that the halfwords are stored high first, low second; so we need
208 // to transpose the fixup value here to map properly.
209 unsigned isNeg = (int64_t(Value) < 0) ? 1 : 0;
211 Value = 0x3fffff & ((Value - 4) >> 1);
212 Binary = (Value & 0x7ff) << 16; // Low imm11 value.
213 Binary |= (Value & 0x1ffc00) >> 11; // High imm10 value.
214 Binary |= isNeg << 10; // Sign bit.
217 case ARM::fixup_arm_thumb_blx: {
218 // The value doesn't encode the low two bits (always zero) and is offset by
219 // four (see fixup_arm_thumb_cp). The value is encoded into disjoint bit
220 // positions in the destination opcode. x = unchanged, I = immediate value
221 // bit, S = sign extension bit, 0 = zero.
223 // BLX: xxxxxSIIIIIIIIII xxxxxIIIIIIIIII0
225 // Note that the halfwords are stored high first, low second; so we need
226 // to transpose the fixup value here to map properly.
227 unsigned isNeg = (int64_t(Value) < 0) ? 1 : 0;
229 Value = 0xfffff & ((Value - 2) >> 2);
230 Binary = (Value & 0x3ff) << 17; // Low imm10L value.
231 Binary |= (Value & 0xffc00) >> 10; // High imm10H value.
232 Binary |= isNeg << 10; // Sign bit.
235 case ARM::fixup_arm_thumb_cp:
236 // Offset by 4, and don't encode the low two bits. Two bytes of that
237 // 'off by 4' is implicitly handled by the half-word ordering of the
238 // Thumb encoding, so we only need to adjust by 2 here.
239 return ((Value - 2) >> 2) & 0xff;
240 case ARM::fixup_arm_thumb_cb: {
241 // Offset by 4 and don't encode the lower bit, which is always 0.
242 uint32_t Binary = (Value - 4) >> 1;
243 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
245 case ARM::fixup_arm_thumb_br:
246 // Offset by 4 and don't encode the lower bit, which is always 0.
247 return ((Value - 4) >> 1) & 0x7ff;
248 case ARM::fixup_arm_thumb_bcc:
249 // Offset by 4 and don't encode the lower bit, which is always 0.
250 return ((Value - 4) >> 1) & 0xff;
251 case ARM::fixup_arm_pcrel_10:
252 Value = Value - 4; // ARM fixups offset by an additional word and don't
253 // need to adjust for the half-word ordering.
255 case ARM::fixup_t2_pcrel_10: {
256 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
259 if ((int64_t)Value < 0) {
263 // These values don't encode the low two bits since they're always zero.
265 assert ((Value < 256) && "Out of range pc-relative fixup value!");
266 Value |= isAdd << 23;
268 // Same addressing mode as fixup_arm_pcrel_10,
269 // but with 16-bit halfwords swapped.
270 if (Kind == ARM::fixup_t2_pcrel_10) {
271 uint32_t swapped = (Value & 0xFFFF0000) >> 16;
272 swapped |= (Value & 0x0000FFFF) << 16;
283 // FIXME: This should be in a separate file.
284 // ELF is an ELF of course...
285 class ELFARMAsmBackend : public ARMAsmBackend {
286 MCELFObjectFormat Format;
289 Triple::OSType OSType;
290 ELFARMAsmBackend(const Target &T, Triple::OSType _OSType)
291 : ARMAsmBackend(T), OSType(_OSType) {
292 HasScatteredSymbols = true;
295 virtual const MCObjectFormat &getObjectFormat() const {
299 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
300 uint64_t Value) const;
302 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
303 return createELFObjectWriter(OS, /*Is64Bit=*/false,
305 /*IsLittleEndian=*/true,
306 /*HasRelocationAddend=*/false);
310 // FIXME: Raise this to share code between Darwin and ELF.
311 void ELFARMAsmBackend::ApplyFixup(const MCFixup &Fixup, char *Data,
312 unsigned DataSize, uint64_t Value) const {
313 unsigned NumBytes = 4; // FIXME: 2 for Thumb
314 Value = adjustFixupValue(Fixup.getKind(), Value);
315 if (!Value) return; // Doesn't change encoding.
317 unsigned Offset = Fixup.getOffset();
318 assert(Offset % NumBytes == 0 && "Offset mod NumBytes is nonzero!");
320 // For each byte of the fragment that the fixup touches, mask in the bits from
321 // the fixup value. The Value has been "split up" into the appropriate
323 for (unsigned i = 0; i != NumBytes; ++i)
324 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
327 // FIXME: This should be in a separate file.
328 class DarwinARMAsmBackend : public ARMAsmBackend {
329 MCMachOObjectFormat Format;
331 DarwinARMAsmBackend(const Target &T) : ARMAsmBackend(T) {
332 HasScatteredSymbols = true;
335 virtual const MCObjectFormat &getObjectFormat() const {
339 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
340 uint64_t Value) const;
342 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
343 // FIXME: Subtarget info should be derived. Force v7 for now.
344 return createMachObjectWriter(OS, /*Is64Bit=*/false,
345 object::mach::CTM_ARM,
346 object::mach::CSARM_V7,
347 /*IsLittleEndian=*/true);
350 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
355 /// getFixupKindNumBytes - The number of bytes the fixup may change.
356 static unsigned getFixupKindNumBytes(unsigned Kind) {
359 llvm_unreachable("Unknown fixup kind!");
361 case ARM::fixup_arm_thumb_bcc:
362 case ARM::fixup_arm_thumb_cp:
363 case ARM::fixup_thumb_adr_pcrel_10:
366 case ARM::fixup_arm_thumb_br:
367 case ARM::fixup_arm_thumb_cb:
370 case ARM::fixup_arm_ldst_pcrel_12:
371 case ARM::fixup_arm_pcrel_10:
372 case ARM::fixup_arm_adr_pcrel_12:
373 case ARM::fixup_arm_branch:
377 case ARM::fixup_t2_ldst_pcrel_12:
378 case ARM::fixup_t2_condbranch:
379 case ARM::fixup_t2_uncondbranch:
380 case ARM::fixup_t2_pcrel_10:
381 case ARM::fixup_t2_adr_pcrel_12:
382 case ARM::fixup_arm_thumb_bl:
383 case ARM::fixup_arm_thumb_blx:
388 void DarwinARMAsmBackend::ApplyFixup(const MCFixup &Fixup, char *Data,
389 unsigned DataSize, uint64_t Value) const {
390 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
391 Value = adjustFixupValue(Fixup.getKind(), Value);
392 if (!Value) return; // Doesn't change encoding.
394 unsigned Offset = Fixup.getOffset();
395 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
397 // For each byte of the fragment that the fixup touches, mask in the
398 // bits from the fixup value.
399 for (unsigned i = 0; i != NumBytes; ++i)
400 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
403 } // end anonymous namespace
405 TargetAsmBackend *llvm::createARMAsmBackend(const Target &T,
406 const std::string &TT) {
407 switch (Triple(TT).getOS()) {
409 return new DarwinARMAsmBackend(T);
410 case Triple::MinGW32:
413 assert(0 && "Windows not supported on ARM");
415 return new ELFARMAsmBackend(T, Triple(TT).getOS());