lib/Target/ARM/ARM.td

   1 //===- ARM.td - Describe the ARM Target Machine ------------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Target-independent interfaces which we are implementing
  15 //===----------------------------------------------------------------------===//
  16
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // ARM Subtarget state.
  21 //
  22
  23 def ModeThumb  : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
  24                                   "Thumb mode">;
  25
  26 //===----------------------------------------------------------------------===//
  27 // ARM Subtarget features.
  28 //
  29
  30 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
  31                                    "Enable VFP2 instructions">;
  32 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
  33                                    "Enable VFP3 instructions",
  34                                    [FeatureVFP2]>;
  35 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
  36                                    "Enable NEON instructions",
  37                                    [FeatureVFP3]>;
  38 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
  39                                      "Enable Thumb2 instructions">;
  40 def FeatureNoARM  : SubtargetFeature<"noarm", "NoARM", "true",
  41                                      "Does not support ARM mode execution">;
  42 def FeatureFP16   : SubtargetFeature<"fp16", "HasFP16", "true",
  43                                      "Enable half-precision floating point">;
  44 def FeatureD16    : SubtargetFeature<"d16", "HasD16", "true",
  45                                      "Restrict VFP3 to 16 double registers">;
  46 def FeatureHWDiv  : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
  47                                      "Enable divide instructions">;
  48 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
  49                                  "Enable Thumb2 extract and pack instructions">;
  50 def FeatureDB     : SubtargetFeature<"db", "HasDataBarrier", "true",
  51                                    "Has data barrier (dmb / dsb) instructions">;
  52 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
  53                                          "FP compare + branch is slow">;
  54 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
  55                           "Floating point unit supports single precision only">;
  56
  57 // Some processors have FP multiply-accumulate instructions that don't
  58 // play nicely with other VFP / NEON instructions, and it's generally better
  59 // to just not use them.
  60 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
  61                                          "Disable VFP / NEON MAC instructions">;
  62
  63 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
  64 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
  65                                        "HasVMLxForwarding", "true",
  66                                        "Has multiplier accumulator forwarding">;
  67
  68 // Some processors benefit from using NEON instructions for scalar
  69 // single-precision FP operations.
  70 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
  71                                         "true",
  72                                         "Use NEON for single precision FP">;
  73
  74 // Disable 32-bit to 16-bit narrowing for experimentation.
  75 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
  76                                              "Prefer 32-bit Thumb instrs">;
  77
  78 /// Some instructions update CPSR partially, which can add false dependency for
  79 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
  80 /// mapped to a separate physical register. Avoid partial CPSR update for these
  81 /// processors.
  82 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
  83                                                "AvoidCPSRPartialUpdate", "true",
  84                                  "Avoid CPSR partial update for OOO execution">;
  85
  86 /// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
  87 def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
  88                                  "Supports v7 DSP instructions in Thumb2">;
  89
  90 // Multiprocessing extension.
  91 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
  92                                  "Supports Multiprocessing extension">;
  93
  94 // ARM ISAs.
  95 def HasV4TOps   : SubtargetFeature<"v4t", "HasV4TOps", "true",
  96                                    "Support ARM v4T instructions">;
  97 def HasV5TOps   : SubtargetFeature<"v5t", "HasV5TOps", "true",
  98                                    "Support ARM v5T instructions",
  99                                    [HasV4TOps]>;
 100 def HasV5TEOps  : SubtargetFeature<"v5te", "HasV5TEOps", "true",
 101                              "Support ARM v5TE, v5TEj, and v5TExp instructions",
 102                                    [HasV5TOps]>;
 103 def HasV6Ops    : SubtargetFeature<"v6", "HasV6Ops", "true",
 104                                    "Support ARM v6 instructions",
 105                                    [HasV5TEOps]>;
 106 def HasV6T2Ops  : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
 107                                    "Support ARM v6t2 instructions",
 108                                    [HasV6Ops, FeatureThumb2, FeatureDSPThumb2]>;
 109 def HasV7Ops    : SubtargetFeature<"v7", "HasV7Ops", "true",
 110                                    "Support ARM v7 instructions",
 111                                    [HasV6T2Ops]>;
 112
 113 //===----------------------------------------------------------------------===//
 114 // ARM Processors supported.
 115 //
 116
 117 include "ARMSchedule.td"
 118
 119 // ARM processor families.
 120 def ProcA8      : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
 121                                    "Cortex-A8 ARM processors",
 122                                    [FeatureSlowFPBrcc, FeatureNEONForFP,
 123                                     FeatureHasSlowFPVMLx, FeatureVMLxForwarding,
 124                                     FeatureT2XtPk]>;
 125 def ProcA9      : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
 126                                    "Cortex-A9 ARM processors",
 127                                    [FeatureVMLxForwarding,
 128                                     FeatureT2XtPk, FeatureFP16,
 129                                     FeatureAvoidPartialCPSR]>;
 130
 131 class ProcNoItin<string Name, list<SubtargetFeature> Features>
 132  : Processor<Name, GenericItineraries, Features>;
 133
 134 // V4 Processors.
 135 def : ProcNoItin<"generic",         []>;
 136 def : ProcNoItin<"arm8",            []>;
 137 def : ProcNoItin<"arm810",          []>;
 138 def : ProcNoItin<"strongarm",       []>;
 139 def : ProcNoItin<"strongarm110",    []>;
 140 def : ProcNoItin<"strongarm1100",   []>;
 141 def : ProcNoItin<"strongarm1110",   []>;
 142
 143 // V4T Processors.
 144 def : ProcNoItin<"arm7tdmi",        [HasV4TOps]>;
 145 def : ProcNoItin<"arm7tdmi-s",      [HasV4TOps]>;
 146 def : ProcNoItin<"arm710t",         [HasV4TOps]>;
 147 def : ProcNoItin<"arm720t",         [HasV4TOps]>;
 148 def : ProcNoItin<"arm9",            [HasV4TOps]>;
 149 def : ProcNoItin<"arm9tdmi",        [HasV4TOps]>;
 150 def : ProcNoItin<"arm920",          [HasV4TOps]>;
 151 def : ProcNoItin<"arm920t",         [HasV4TOps]>;
 152 def : ProcNoItin<"arm922t",         [HasV4TOps]>;
 153 def : ProcNoItin<"arm940t",         [HasV4TOps]>;
 154 def : ProcNoItin<"ep9312",          [HasV4TOps]>;
 155
 156 // V5T Processors.
 157 def : ProcNoItin<"arm10tdmi",       [HasV5TOps]>;
 158 def : ProcNoItin<"arm1020t",        [HasV5TOps]>;
 159
 160 // V5TE Processors.
 161 def : ProcNoItin<"arm9e",           [HasV5TEOps]>;
 162 def : ProcNoItin<"arm926ej-s",      [HasV5TEOps]>;
 163 def : ProcNoItin<"arm946e-s",       [HasV5TEOps]>;
 164 def : ProcNoItin<"arm966e-s",       [HasV5TEOps]>;
 165 def : ProcNoItin<"arm968e-s",       [HasV5TEOps]>;
 166 def : ProcNoItin<"arm10e",          [HasV5TEOps]>;
 167 def : ProcNoItin<"arm1020e",        [HasV5TEOps]>;
 168 def : ProcNoItin<"arm1022e",        [HasV5TEOps]>;
 169 def : ProcNoItin<"xscale",          [HasV5TEOps]>;
 170 def : ProcNoItin<"iwmmxt",          [HasV5TEOps]>;
 171
 172 // V6 Processors.
 173 def : Processor<"arm1136j-s",       ARMV6Itineraries, [HasV6Ops]>;
 174 def : Processor<"arm1136jf-s",      ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
 175                                                        FeatureHasSlowFPVMLx]>;
 176 def : Processor<"arm1176jz-s",      ARMV6Itineraries, [HasV6Ops]>;
 177 def : Processor<"arm1176jzf-s",     ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
 178                                                        FeatureHasSlowFPVMLx]>;
 179 def : Processor<"mpcorenovfp",      ARMV6Itineraries, [HasV6Ops]>;
 180 def : Processor<"mpcore",           ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
 181                                                        FeatureHasSlowFPVMLx]>;
 182
 183 // V6M Processors.
 184 def : Processor<"cortex-m0",        ARMV6Itineraries, [HasV6Ops, FeatureNoARM,
 185                                                        FeatureDB]>;
 186
 187 // V6T2 Processors.
 188 def : Processor<"arm1156t2-s",      ARMV6Itineraries, [HasV6T2Ops]>;
 189 def : Processor<"arm1156t2f-s",     ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
 190                                                        FeatureHasSlowFPVMLx]>;
 191
 192 // V7a Processors.
 193 def : Processor<"cortex-a8",        CortexA8Itineraries,
 194                                     [ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
 195                                      FeatureDSPThumb2]>;
 196 def : Processor<"cortex-a9",        CortexA9Itineraries,
 197                                     [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
 198                                      FeatureDSPThumb2]>;
 199 def : Processor<"cortex-a9-mp",     CortexA9Itineraries,
 200                                     [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
 201                                      FeatureDSPThumb2, FeatureMP]>;
 202
 203 // V7M Processors.
 204 def : ProcNoItin<"cortex-m3",       [HasV7Ops,
 205                                      FeatureThumb2, FeatureNoARM, FeatureDB,
 206                                      FeatureHWDiv]>;
 207
 208 // V7EM Processors.
 209 def : ProcNoItin<"cortex-m4",       [HasV7Ops,
 210                                      FeatureThumb2, FeatureNoARM, FeatureDB,
 211                                      FeatureHWDiv, FeatureDSPThumb2,
 212                                      FeatureT2XtPk, FeatureVFP2,
 213                                      FeatureVFPOnlySP]>;
 214
 215 //===----------------------------------------------------------------------===//
 216 // Register File Description
 217 //===----------------------------------------------------------------------===//
 218
 219 include "ARMRegisterInfo.td"
 220
 221 include "ARMCallingConv.td"
 222
 223 //===----------------------------------------------------------------------===//
 224 // Instruction Descriptions
 225 //===----------------------------------------------------------------------===//
 226
 227 include "ARMInstrInfo.td"
 228
 229 def ARMInstrInfo : InstrInfo;
 230
 231
 232 //===----------------------------------------------------------------------===//
 233 // Assembly printer
 234 //===----------------------------------------------------------------------===//
 235 // ARM Uses the MC printer for asm output, so make sure the TableGen
 236 // AsmWriter bits get associated with the correct class.
 237 def ARMAsmWriter : AsmWriter {
 238   string AsmWriterClassName  = "InstPrinter";
 239   bit isMCAsmWriter = 1;
 240 }
 241
 242 //===----------------------------------------------------------------------===//
 243 // Declare the target which we are implementing
 244 //===----------------------------------------------------------------------===//
 245
 246 def ARM : Target {
 247   // Pull in Instruction Info:
 248   let InstructionSet = ARMInstrInfo;
 249
 250   let AssemblyWriters = [ARMAsmWriter];
 251 }