lib/Target/ARM/ARM.td

   1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Target-independent interfaces which we are implementing
  15 //===----------------------------------------------------------------------===//
  16
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // ARM Subtarget state.
  21 //
  22
  23 def ModeThumb  : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
  24                                   "Thumb mode">;
  25
  26 //===----------------------------------------------------------------------===//
  27 // ARM Subtarget features.
  28 //
  29
  30 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
  31                                    "Enable VFP2 instructions">;
  32 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
  33                                    "Enable VFP3 instructions",
  34                                    [FeatureVFP2]>;
  35 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
  36                                    "Enable NEON instructions",
  37                                    [FeatureVFP3]>;
  38 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
  39                                      "Enable Thumb2 instructions">;
  40 def FeatureNoARM  : SubtargetFeature<"noarm", "NoARM", "true",
  41                                      "Does not support ARM mode execution">;
  42 def FeatureFP16   : SubtargetFeature<"fp16", "HasFP16", "true",
  43                                      "Enable half-precision floating point">;
  44 def FeatureVFP4   : SubtargetFeature<"vfp4", "HasVFPv4", "true",
  45                                      "Enable VFP4 instructions",
  46                                      [FeatureVFP3, FeatureFP16]>;
  47 def FeatureD16    : SubtargetFeature<"d16", "HasD16", "true",
  48                                      "Restrict VFP3 to 16 double registers">;
  49 def FeatureHWDiv  : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
  50                                      "Enable divide instructions">;
  51 def FeatureHWDivARM  : SubtargetFeature<"hwdiv-arm",
  52                                         "HasHardwareDivideInARM", "true",
  53                                       "Enable divide instructions in ARM mode">;
  54 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
  55                                  "Enable Thumb2 extract and pack instructions">;
  56 def FeatureDB     : SubtargetFeature<"db", "HasDataBarrier", "true",
  57                                    "Has data barrier (dmb / dsb) instructions">;
  58 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
  59                                          "FP compare + branch is slow">;
  60 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
  61                           "Floating point unit supports single precision only">;
  62 def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
  63                           "Enable support for TrustZone security extensions">;
  64
  65 // Some processors have FP multiply-accumulate instructions that don't
  66 // play nicely with other VFP / NEON instructions, and it's generally better
  67 // to just not use them.
  68 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
  69                                          "Disable VFP / NEON MAC instructions">;
  70
  71 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
  72 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
  73                                        "HasVMLxForwarding", "true",
  74                                        "Has multiplier accumulator forwarding">;
  75
  76 // Some processors benefit from using NEON instructions for scalar
  77 // single-precision FP operations.
  78 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
  79                                         "true",
  80                                         "Use NEON for single precision FP">;
  81
  82 // Disable 32-bit to 16-bit narrowing for experimentation.
  83 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
  84                                              "Prefer 32-bit Thumb instrs">;
  85
  86 /// Some instructions update CPSR partially, which can add false dependency for
  87 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
  88 /// mapped to a separate physical register. Avoid partial CPSR update for these
  89 /// processors.
  90 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
  91                                                "AvoidCPSRPartialUpdate", "true",
  92                                  "Avoid CPSR partial update for OOO execution">;
  93
  94 def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
  95                                             "AvoidMOVsShifterOperand", "true",
  96                                 "Avoid movs instructions with shifter operand">;
  97
  98 // Some processors perform return stack prediction. CodeGen should avoid issue
  99 // "normal" call instructions to callees which do not return.
 100 def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true",
 101                                      "Has return address stack">;
 102
 103 /// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
 104 def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
 105                                  "Supports v7 DSP instructions in Thumb2">;
 106
 107 // Multiprocessing extension.
 108 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
 109                                  "Supports Multiprocessing extension">;
 110
 111 // M-series ISA?
 112 def FeatureMClass : SubtargetFeature<"mclass", "IsMClass", "true",
 113                                      "Is microcontroller profile ('M' series)">;
 114
 115 // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
 116 // See ARMInstrInfo.td for details.
 117 def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
 118                                        "NaCl trap">;
 119
 120 // ARM ISAs.
 121 def HasV4TOps   : SubtargetFeature<"v4t", "HasV4TOps", "true",
 122                                    "Support ARM v4T instructions">;
 123 def HasV5TOps   : SubtargetFeature<"v5t", "HasV5TOps", "true",
 124                                    "Support ARM v5T instructions",
 125                                    [HasV4TOps]>;
 126 def HasV5TEOps  : SubtargetFeature<"v5te", "HasV5TEOps", "true",
 127                              "Support ARM v5TE, v5TEj, and v5TExp instructions",
 128                                    [HasV5TOps]>;
 129 def HasV6Ops    : SubtargetFeature<"v6", "HasV6Ops", "true",
 130                                    "Support ARM v6 instructions",
 131                                    [HasV5TEOps]>;
 132 def HasV6T2Ops  : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
 133                                    "Support ARM v6t2 instructions",
 134                                    [HasV6Ops, FeatureThumb2]>;
 135 def HasV7Ops    : SubtargetFeature<"v7", "HasV7Ops", "true",
 136                                    "Support ARM v7 instructions",
 137                                    [HasV6T2Ops]>;
 138
 139 //===----------------------------------------------------------------------===//
 140 // ARM Processors supported.
 141 //
 142
 143 include "ARMSchedule.td"
 144
 145 // ARM processor families.
 146 def ProcA5      : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
 147                                    "Cortex-A5 ARM processors",
 148                                    [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
 149                                     FeatureVMLxForwarding, FeatureT2XtPk,
 150                                     FeatureTrustZone]>;
 151 def ProcA8      : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
 152                                    "Cortex-A8 ARM processors",
 153                                    [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
 154                                     FeatureVMLxForwarding, FeatureT2XtPk,
 155                                     FeatureTrustZone]>;
 156 def ProcA9      : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
 157                                    "Cortex-A9 ARM processors",
 158                                    [FeatureVMLxForwarding,
 159                                     FeatureT2XtPk, FeatureFP16,
 160                                     FeatureAvoidPartialCPSR,
 161                                     FeatureTrustZone]>;
 162 def ProcSwift   : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
 163                                    "Swift ARM processors",
 164                                    [FeatureNEONForFP, FeatureT2XtPk,
 165                                     FeatureVFP4, FeatureMP, FeatureHWDiv,
 166                                     FeatureHWDivARM, FeatureAvoidPartialCPSR,
 167                                     FeatureAvoidMOVsShOp,
 168                                     FeatureHasSlowFPVMLx, FeatureTrustZone]>;
 169
 170 // FIXME: It has not been determined if A15 has these features.
 171 def ProcA15      : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
 172                                    "Cortex-A15 ARM processors",
 173                                    [FeatureT2XtPk, FeatureFP16,
 174                                     FeatureAvoidPartialCPSR,
 175                                     FeatureTrustZone]>;
 176 def ProcR5      : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
 177                                    "Cortex-R5 ARM processors",
 178                                    [FeatureSlowFPBrcc, FeatureHWDivARM,
 179                                     FeatureHasSlowFPVMLx,
 180                                     FeatureAvoidPartialCPSR,
 181                                     FeatureT2XtPk]>;
 182
 183 class ProcNoItin<string Name, list<SubtargetFeature> Features>
 184  : Processor<Name, NoItineraries, Features>;
 185
 186 // V4 Processors.
 187 def : ProcNoItin<"generic",         []>;
 188 def : ProcNoItin<"arm8",            []>;
 189 def : ProcNoItin<"arm810",          []>;
 190 def : ProcNoItin<"strongarm",       []>;
 191 def : ProcNoItin<"strongarm110",    []>;
 192 def : ProcNoItin<"strongarm1100",   []>;
 193 def : ProcNoItin<"strongarm1110",   []>;
 194
 195 // V4T Processors.
 196 def : ProcNoItin<"arm7tdmi",        [HasV4TOps]>;
 197 def : ProcNoItin<"arm7tdmi-s",      [HasV4TOps]>;
 198 def : ProcNoItin<"arm710t",         [HasV4TOps]>;
 199 def : ProcNoItin<"arm720t",         [HasV4TOps]>;
 200 def : ProcNoItin<"arm9",            [HasV4TOps]>;
 201 def : ProcNoItin<"arm9tdmi",        [HasV4TOps]>;
 202 def : ProcNoItin<"arm920",          [HasV4TOps]>;
 203 def : ProcNoItin<"arm920t",         [HasV4TOps]>;
 204 def : ProcNoItin<"arm922t",         [HasV4TOps]>;
 205 def : ProcNoItin<"arm940t",         [HasV4TOps]>;
 206 def : ProcNoItin<"ep9312",          [HasV4TOps]>;
 207
 208 // V5T Processors.
 209 def : ProcNoItin<"arm10tdmi",       [HasV5TOps]>;
 210 def : ProcNoItin<"arm1020t",        [HasV5TOps]>;
 211
 212 // V5TE Processors.
 213 def : ProcNoItin<"arm9e",           [HasV5TEOps]>;
 214 def : ProcNoItin<"arm926ej-s",      [HasV5TEOps]>;
 215 def : ProcNoItin<"arm946e-s",       [HasV5TEOps]>;
 216 def : ProcNoItin<"arm966e-s",       [HasV5TEOps]>;
 217 def : ProcNoItin<"arm968e-s",       [HasV5TEOps]>;
 218 def : ProcNoItin<"arm10e",          [HasV5TEOps]>;
 219 def : ProcNoItin<"arm1020e",        [HasV5TEOps]>;
 220 def : ProcNoItin<"arm1022e",        [HasV5TEOps]>;
 221 def : ProcNoItin<"xscale",          [HasV5TEOps]>;
 222 def : ProcNoItin<"iwmmxt",          [HasV5TEOps]>;
 223
 224 // V6 Processors.
 225 def : Processor<"arm1136j-s",       ARMV6Itineraries, [HasV6Ops]>;
 226 def : Processor<"arm1136jf-s",      ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
 227                                                        FeatureHasSlowFPVMLx]>;
 228 def : Processor<"arm1176jz-s",      ARMV6Itineraries, [HasV6Ops]>;
 229 def : Processor<"arm1176jzf-s",     ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
 230                                                        FeatureHasSlowFPVMLx]>;
 231 def : Processor<"mpcorenovfp",      ARMV6Itineraries, [HasV6Ops]>;
 232 def : Processor<"mpcore",           ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
 233                                                        FeatureHasSlowFPVMLx]>;
 234
 235 // V6M Processors.
 236 def : Processor<"cortex-m0",        ARMV6Itineraries, [HasV6Ops, FeatureNoARM,
 237                                                        FeatureDB, FeatureMClass]>;
 238
 239 // V6T2 Processors.
 240 def : Processor<"arm1156t2-s",      ARMV6Itineraries, [HasV6T2Ops,
 241                                                        FeatureDSPThumb2]>;
 242 def : Processor<"arm1156t2f-s",     ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
 243                                                        FeatureHasSlowFPVMLx,
 244                                                        FeatureDSPThumb2]>;
 245
 246 // V7a Processors.
 247 // FIXME: A5 has currently the same Schedule model as A8
 248 def : ProcessorModel<"cortex-a5",   CortexA8Model,
 249                                     [ProcA5, HasV7Ops, FeatureNEON, FeatureDB,
 250                                      FeatureVFP4, FeatureDSPThumb2,
 251                                      FeatureHasRAS]>;
 252 def : ProcessorModel<"cortex-a8",   CortexA8Model,
 253                                     [ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
 254                                      FeatureDSPThumb2, FeatureHasRAS]>;
 255 def : ProcessorModel<"cortex-a9",   CortexA9Model,
 256                                     [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
 257                                      FeatureDSPThumb2, FeatureHasRAS]>;
 258 def : ProcessorModel<"cortex-a9-mp", CortexA9Model,
 259                                     [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
 260                                      FeatureDSPThumb2, FeatureMP,
 261                                      FeatureHasRAS]>;
 262 // FIXME: A15 has currently the same ProcessorModel as A9.
 263 def : ProcessorModel<"cortex-a15",   CortexA9Model,
 264                                     [ProcA15, HasV7Ops, FeatureNEON, FeatureDB,
 265                                      FeatureDSPThumb2, FeatureHasRAS]>;
 266 // FIXME: R5 has currently the same ProcessorModel as A8.
 267 def : ProcessorModel<"cortex-r5",   CortexA8Model,
 268                                     [ProcR5, HasV7Ops, FeatureDB,
 269                                      FeatureVFP3, FeatureDSPThumb2,
 270                                      FeatureHasRAS]>;
 271
 272 // V7M Processors.
 273 def : ProcNoItin<"cortex-m3",       [HasV7Ops,
 274                                      FeatureThumb2, FeatureNoARM, FeatureDB,
 275                                      FeatureHWDiv, FeatureMClass]>;
 276
 277 // V7EM Processors.
 278 def : ProcNoItin<"cortex-m4",       [HasV7Ops,
 279                                      FeatureThumb2, FeatureNoARM, FeatureDB,
 280                                      FeatureHWDiv, FeatureDSPThumb2,
 281                                      FeatureT2XtPk, FeatureVFP4,
 282                                      FeatureVFPOnlySP, FeatureMClass]>;
 283
 284 // Swift uArch Processors.
 285 def : ProcessorModel<"swift",       SwiftModel,
 286                                     [ProcSwift, HasV7Ops, FeatureNEON,
 287                                      FeatureDB, FeatureDSPThumb2,
 288                                      FeatureHasRAS]>;
 289
 290 //===----------------------------------------------------------------------===//
 291 // Register File Description
 292 //===----------------------------------------------------------------------===//
 293
 294 include "ARMRegisterInfo.td"
 295
 296 include "ARMCallingConv.td"
 297
 298 //===----------------------------------------------------------------------===//
 299 // Instruction Descriptions
 300 //===----------------------------------------------------------------------===//
 301
 302 include "ARMInstrInfo.td"
 303
 304 def ARMInstrInfo : InstrInfo;
 305
 306
 307 //===----------------------------------------------------------------------===//
 308 // Assembly printer
 309 //===----------------------------------------------------------------------===//
 310 // ARM Uses the MC printer for asm output, so make sure the TableGen
 311 // AsmWriter bits get associated with the correct class.
 312 def ARMAsmWriter : AsmWriter {
 313   string AsmWriterClassName  = "InstPrinter";
 314   bit isMCAsmWriter = 1;
 315 }
 316
 317 //===----------------------------------------------------------------------===//
 318 // Declare the target which we are implementing
 319 //===----------------------------------------------------------------------===//
 320
 321 def ARM : Target {
 322   // Pull in Instruction Info:
 323   let InstructionSet = ARMInstrInfo;
 324
 325   let AssemblyWriters = [ARMAsmWriter];
 326 }