1 //===- ARM.td - Describe the ARM Target Machine ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
20 //===----------------------------------------------------------------------===//
21 // ARM Subtarget features.
24 def FeatureVFP2 : SubtargetFeature<"vfp2", "ARMFPUType", "VFPv2",
25 "Enable VFP2 instructions">;
26 def FeatureVFP3 : SubtargetFeature<"vfp3", "ARMFPUType", "VFPv3",
27 "Enable VFP3 instructions">;
28 def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON",
29 "Enable NEON instructions">;
30 def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2",
31 "Enable Thumb2 instructions">;
32 def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
33 "Does not support ARM mode execution">;
34 def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
35 "Enable half-precision floating point">;
36 def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true",
37 "Restrict VFP3 to 16 double registers">;
38 def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
39 "Enable divide instructions">;
40 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
41 "Enable Thumb2 extract and pack instructions">;
42 def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
43 "Has data barrier (dmb / dsb) instructions">;
44 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
45 "FP compare + branch is slow">;
46 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
47 "Floating point unit supports single precision only">;
49 // Some processors have FP multiply-accumulate instructions that don't
50 // play nicely with other VFP / NEON instructions, and it's generally better
51 // to just not use them.
52 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
53 "Disable VFP / NEON MAC instructions">;
55 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
56 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
57 "HasVMLxForwarding", "true",
58 "Has multiplier accumulator forwarding">;
60 // Some processors benefit from using NEON instructions for scalar
61 // single-precision FP operations.
62 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
64 "Use NEON for single precision FP">;
66 // Disable 32-bit to 16-bit narrowing for experimentation.
67 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
68 "Prefer 32-bit Thumb instrs">;
70 /// Some instructions update CPSR partially, which can add false dependency for
71 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
72 /// mapped to a separate physical register. Avoid partial CPSR update for these
74 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
75 "AvoidCPSRPartialUpdate", "true",
76 "Avoid CPSR partial update for OOO execution">;
78 // Multiprocessing extension.
79 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
80 "Supports Multiprocessing extension">;
83 def ArchV4T : SubtargetFeature<"v4t", "ARMArchVersion", "V4T",
85 def ArchV5T : SubtargetFeature<"v5t", "ARMArchVersion", "V5T",
87 def ArchV5TE : SubtargetFeature<"v5te", "ARMArchVersion", "V5TE",
88 "ARM v5TE, v5TEj, v5TExp">;
89 def ArchV6 : SubtargetFeature<"v6", "ARMArchVersion", "V6",
91 def ArchV6M : SubtargetFeature<"v6m", "ARMArchVersion", "V6M",
93 [FeatureNoARM, FeatureDB]>;
94 def ArchV6T2 : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2",
97 def ArchV7A : SubtargetFeature<"v7a", "ARMArchVersion", "V7A",
99 [FeatureThumb2, FeatureNEON, FeatureDB]>;
100 def ArchV7M : SubtargetFeature<"v7m", "ARMArchVersion", "V7M",
102 [FeatureThumb2, FeatureNoARM, FeatureDB,
105 //===----------------------------------------------------------------------===//
106 // ARM Processors supported.
109 include "ARMSchedule.td"
111 // ARM processor families.
112 def ProcOthers : SubtargetFeature<"others", "ARMProcFamily", "Others",
113 "One of the other ARM processor families">;
114 def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
115 "Cortex-A8 ARM processors",
116 [FeatureSlowFPBrcc, FeatureNEONForFP,
117 FeatureHasSlowFPVMLx, FeatureVMLxForwarding,
119 def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
120 "Cortex-A9 ARM processors",
121 [FeatureVMLxForwarding,
122 FeatureT2XtPk, FeatureFP16,
123 FeatureAvoidPartialCPSR]>;
125 class ProcNoItin<string Name, list<SubtargetFeature> Features>
126 : Processor<Name, GenericItineraries, Features>;
129 def : ProcNoItin<"generic", []>;
130 def : ProcNoItin<"arm8", []>;
131 def : ProcNoItin<"arm810", []>;
132 def : ProcNoItin<"strongarm", []>;
133 def : ProcNoItin<"strongarm110", []>;
134 def : ProcNoItin<"strongarm1100", []>;
135 def : ProcNoItin<"strongarm1110", []>;
138 def : ProcNoItin<"arm7tdmi", [ArchV4T]>;
139 def : ProcNoItin<"arm7tdmi-s", [ArchV4T]>;
140 def : ProcNoItin<"arm710t", [ArchV4T]>;
141 def : ProcNoItin<"arm720t", [ArchV4T]>;
142 def : ProcNoItin<"arm9", [ArchV4T]>;
143 def : ProcNoItin<"arm9tdmi", [ArchV4T]>;
144 def : ProcNoItin<"arm920", [ArchV4T]>;
145 def : ProcNoItin<"arm920t", [ArchV4T]>;
146 def : ProcNoItin<"arm922t", [ArchV4T]>;
147 def : ProcNoItin<"arm940t", [ArchV4T]>;
148 def : ProcNoItin<"ep9312", [ArchV4T]>;
151 def : ProcNoItin<"arm10tdmi", [ArchV5T]>;
152 def : ProcNoItin<"arm1020t", [ArchV5T]>;
155 def : ProcNoItin<"arm9e", [ArchV5TE]>;
156 def : ProcNoItin<"arm926ej-s", [ArchV5TE]>;
157 def : ProcNoItin<"arm946e-s", [ArchV5TE]>;
158 def : ProcNoItin<"arm966e-s", [ArchV5TE]>;
159 def : ProcNoItin<"arm968e-s", [ArchV5TE]>;
160 def : ProcNoItin<"arm10e", [ArchV5TE]>;
161 def : ProcNoItin<"arm1020e", [ArchV5TE]>;
162 def : ProcNoItin<"arm1022e", [ArchV5TE]>;
163 def : ProcNoItin<"xscale", [ArchV5TE]>;
164 def : ProcNoItin<"iwmmxt", [ArchV5TE]>;
167 def : Processor<"arm1136j-s", ARMV6Itineraries, [ArchV6]>;
168 def : Processor<"arm1136jf-s", ARMV6Itineraries, [ArchV6, FeatureVFP2,
169 FeatureHasSlowFPVMLx]>;
170 def : Processor<"arm1176jz-s", ARMV6Itineraries, [ArchV6]>;
171 def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ArchV6, FeatureVFP2,
172 FeatureHasSlowFPVMLx]>;
173 def : Processor<"mpcorenovfp", ARMV6Itineraries, [ArchV6]>;
174 def : Processor<"mpcore", ARMV6Itineraries, [ArchV6, FeatureVFP2,
175 FeatureHasSlowFPVMLx]>;
178 def : Processor<"cortex-m0", ARMV6Itineraries, [ArchV6M]>;
181 def : Processor<"arm1156t2-s", ARMV6Itineraries, [ArchV6T2]>;
182 def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ArchV6T2, FeatureVFP2,
183 FeatureHasSlowFPVMLx]>;
186 def : Processor<"cortex-a8", CortexA8Itineraries,
188 def : Processor<"cortex-a9", CortexA9Itineraries,
190 def : Processor<"cortex-a9-mp", CortexA9Itineraries,
191 [ArchV7A, ProcA9, FeatureMP]>;
194 def : ProcNoItin<"cortex-m3", [ArchV7M]>;
195 def : ProcNoItin<"cortex-m4", [ArchV7M, FeatureVFP2, FeatureVFPOnlySP]>;
197 //===----------------------------------------------------------------------===//
198 // Register File Description
199 //===----------------------------------------------------------------------===//
201 include "ARMRegisterInfo.td"
203 include "ARMCallingConv.td"
205 //===----------------------------------------------------------------------===//
206 // Instruction Descriptions
207 //===----------------------------------------------------------------------===//
209 include "ARMInstrInfo.td"
211 def ARMInstrInfo : InstrInfo;
214 //===----------------------------------------------------------------------===//
216 //===----------------------------------------------------------------------===//
217 // ARM Uses the MC printer for asm output, so make sure the TableGen
218 // AsmWriter bits get associated with the correct class.
219 def ARMAsmWriter : AsmWriter {
220 string AsmWriterClassName = "InstPrinter";
221 bit isMCAsmWriter = 1;
224 //===----------------------------------------------------------------------===//
225 // Declare the target which we are implementing
226 //===----------------------------------------------------------------------===//
229 // Pull in Instruction Info:
230 let InstructionSet = ARMInstrInfo;
232 let AssemblyWriters = [ARMAsmWriter];