lib/Target/ARM/ARM.td

   1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Target-independent interfaces which we are implementing
  15 //===----------------------------------------------------------------------===//
  16
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // ARM Subtarget state.
  21 //
  22
  23 def ModeThumb  : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
  24                                   "Thumb mode">;
  25
  26 //===----------------------------------------------------------------------===//
  27 // ARM Subtarget features.
  28 //
  29
  30 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
  31                                    "Enable VFP2 instructions">;
  32 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
  33                                    "Enable VFP3 instructions",
  34                                    [FeatureVFP2]>;
  35 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
  36                                    "Enable NEON instructions",
  37                                    [FeatureVFP3]>;
  38 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
  39                                      "Enable Thumb2 instructions">;
  40 def FeatureNoARM  : SubtargetFeature<"noarm", "NoARM", "true",
  41                                      "Does not support ARM mode execution",
  42                                      [ModeThumb]>;
  43 def FeatureFP16   : SubtargetFeature<"fp16", "HasFP16", "true",
  44                                      "Enable half-precision floating point">;
  45 def FeatureVFP4   : SubtargetFeature<"vfp4", "HasVFPv4", "true",
  46                                      "Enable VFP4 instructions",
  47                                      [FeatureVFP3, FeatureFP16]>;
  48 def FeatureD16    : SubtargetFeature<"d16", "HasD16", "true",
  49                                      "Restrict VFP3 to 16 double registers">;
  50 def FeatureHWDiv  : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
  51                                      "Enable divide instructions">;
  52 def FeatureHWDivARM  : SubtargetFeature<"hwdiv-arm",
  53                                         "HasHardwareDivideInARM", "true",
  54                                       "Enable divide instructions in ARM mode">;
  55 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
  56                                  "Enable Thumb2 extract and pack instructions">;
  57 def FeatureDB     : SubtargetFeature<"db", "HasDataBarrier", "true",
  58                                    "Has data barrier (dmb / dsb) instructions">;
  59 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
  60                                          "FP compare + branch is slow">;
  61 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
  62                           "Floating point unit supports single precision only">;
  63 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
  64                            "Enable support for Performance Monitor extensions">;
  65 def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
  66                           "Enable support for TrustZone security extensions">;
  67
  68 // Some processors have FP multiply-accumulate instructions that don't
  69 // play nicely with other VFP / NEON instructions, and it's generally better
  70 // to just not use them.
  71 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
  72                                          "Disable VFP / NEON MAC instructions">;
  73
  74 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
  75 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
  76                                        "HasVMLxForwarding", "true",
  77                                        "Has multiplier accumulator forwarding">;
  78
  79 // Some processors benefit from using NEON instructions for scalar
  80 // single-precision FP operations.
  81 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
  82                                         "true",
  83                                         "Use NEON for single precision FP">;
  84
  85 // Disable 32-bit to 16-bit narrowing for experimentation.
  86 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
  87                                              "Prefer 32-bit Thumb instrs">;
  88
  89 /// Some instructions update CPSR partially, which can add false dependency for
  90 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
  91 /// mapped to a separate physical register. Avoid partial CPSR update for these
  92 /// processors.
  93 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
  94                                                "AvoidCPSRPartialUpdate", "true",
  95                                  "Avoid CPSR partial update for OOO execution">;
  96
  97 def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
  98                                             "AvoidMOVsShifterOperand", "true",
  99                                 "Avoid movs instructions with shifter operand">;
 100
 101 // Some processors perform return stack prediction. CodeGen should avoid issue
 102 // "normal" call instructions to callees which do not return.
 103 def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true",
 104                                      "Has return address stack">;
 105
 106 /// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
 107 def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
 108                                  "Supports v7 DSP instructions in Thumb2">;
 109
 110 // Multiprocessing extension.
 111 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
 112                                  "Supports Multiprocessing extension">;
 113
 114 // M-series ISA?
 115 def FeatureMClass : SubtargetFeature<"mclass", "IsMClass", "true",
 116                                      "Is microcontroller profile ('M' series)">;
 117
 118 // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
 119 // See ARMInstrInfo.td for details.
 120 def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
 121                                        "NaCl trap">;
 122
 123 // ARM ISAs.
 124 def HasV4TOps   : SubtargetFeature<"v4t", "HasV4TOps", "true",
 125                                    "Support ARM v4T instructions">;
 126 def HasV5TOps   : SubtargetFeature<"v5t", "HasV5TOps", "true",
 127                                    "Support ARM v5T instructions",
 128                                    [HasV4TOps]>;
 129 def HasV5TEOps  : SubtargetFeature<"v5te", "HasV5TEOps", "true",
 130                              "Support ARM v5TE, v5TEj, and v5TExp instructions",
 131                                    [HasV5TOps]>;
 132 def HasV6Ops    : SubtargetFeature<"v6", "HasV6Ops", "true",
 133                                    "Support ARM v6 instructions",
 134                                    [HasV5TEOps]>;
 135 def HasV6T2Ops  : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
 136                                    "Support ARM v6t2 instructions",
 137                                    [HasV6Ops, FeatureThumb2]>;
 138 def HasV7Ops    : SubtargetFeature<"v7", "HasV7Ops", "true",
 139                                    "Support ARM v7 instructions",
 140                                    [HasV6T2Ops, FeaturePerfMon]>;
 141 def HasV8Ops    : SubtargetFeature<"v8", "HasV8Ops", "true",
 142                                    "Support ARM v8 instructions",
 143                                    [HasV7Ops]>;
 144
 145 //===----------------------------------------------------------------------===//
 146 // ARM Processors supported.
 147 //
 148
 149 include "ARMSchedule.td"
 150
 151 // ARM processor families.
 152 def ProcA5      : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
 153                                    "Cortex-A5 ARM processors",
 154                                    [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
 155                                     FeatureVMLxForwarding, FeatureT2XtPk,
 156                                     FeatureTrustZone]>;
 157 def ProcA8      : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
 158                                    "Cortex-A8 ARM processors",
 159                                    [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
 160                                     FeatureVMLxForwarding, FeatureT2XtPk,
 161                                     FeatureTrustZone]>;
 162 def ProcA9      : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
 163                                    "Cortex-A9 ARM processors",
 164                                    [FeatureVMLxForwarding,
 165                                     FeatureT2XtPk, FeatureFP16,
 166                                     FeatureAvoidPartialCPSR,
 167                                     FeatureTrustZone]>;
 168 def ProcSwift   : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
 169                                    "Swift ARM processors",
 170                                    [FeatureNEONForFP, FeatureT2XtPk,
 171                                     FeatureVFP4, FeatureMP, FeatureHWDiv,
 172                                     FeatureHWDivARM, FeatureAvoidPartialCPSR,
 173                                     FeatureAvoidMOVsShOp,
 174                                     FeatureHasSlowFPVMLx, FeatureTrustZone]>;
 175
 176 // FIXME: It has not been determined if A15 has these features.
 177 def ProcA15      : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
 178                                    "Cortex-A15 ARM processors",
 179                                    [FeatureT2XtPk, FeatureFP16,
 180                                     FeatureAvoidPartialCPSR,
 181                                     FeatureTrustZone]>;
 182 def ProcR5      : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
 183                                    "Cortex-R5 ARM processors",
 184                                    [FeatureSlowFPBrcc,
 185                                     FeatureHWDiv, FeatureHWDivARM,
 186                                     FeatureHasSlowFPVMLx,
 187                                     FeatureAvoidPartialCPSR,
 188                                     FeatureT2XtPk]>;
 189
 190 class ProcNoItin<string Name, list<SubtargetFeature> Features>
 191  : Processor<Name, NoItineraries, Features>;
 192
 193 // V4 Processors.
 194 def : ProcNoItin<"generic",         []>;
 195 def : ProcNoItin<"arm8",            []>;
 196 def : ProcNoItin<"arm810",          []>;
 197 def : ProcNoItin<"strongarm",       []>;
 198 def : ProcNoItin<"strongarm110",    []>;
 199 def : ProcNoItin<"strongarm1100",   []>;
 200 def : ProcNoItin<"strongarm1110",   []>;
 201
 202 // V4T Processors.
 203 def : ProcNoItin<"arm7tdmi",        [HasV4TOps]>;
 204 def : ProcNoItin<"arm7tdmi-s",      [HasV4TOps]>;
 205 def : ProcNoItin<"arm710t",         [HasV4TOps]>;
 206 def : ProcNoItin<"arm720t",         [HasV4TOps]>;
 207 def : ProcNoItin<"arm9",            [HasV4TOps]>;
 208 def : ProcNoItin<"arm9tdmi",        [HasV4TOps]>;
 209 def : ProcNoItin<"arm920",          [HasV4TOps]>;
 210 def : ProcNoItin<"arm920t",         [HasV4TOps]>;
 211 def : ProcNoItin<"arm922t",         [HasV4TOps]>;
 212 def : ProcNoItin<"arm940t",         [HasV4TOps]>;
 213 def : ProcNoItin<"ep9312",          [HasV4TOps]>;
 214
 215 // V5T Processors.
 216 def : ProcNoItin<"arm10tdmi",       [HasV5TOps]>;
 217 def : ProcNoItin<"arm1020t",        [HasV5TOps]>;
 218
 219 // V5TE Processors.
 220 def : ProcNoItin<"arm9e",           [HasV5TEOps]>;
 221 def : ProcNoItin<"arm926ej-s",      [HasV5TEOps]>;
 222 def : ProcNoItin<"arm946e-s",       [HasV5TEOps]>;
 223 def : ProcNoItin<"arm966e-s",       [HasV5TEOps]>;
 224 def : ProcNoItin<"arm968e-s",       [HasV5TEOps]>;
 225 def : ProcNoItin<"arm10e",          [HasV5TEOps]>;
 226 def : ProcNoItin<"arm1020e",        [HasV5TEOps]>;
 227 def : ProcNoItin<"arm1022e",        [HasV5TEOps]>;
 228 def : ProcNoItin<"xscale",          [HasV5TEOps]>;
 229 def : ProcNoItin<"iwmmxt",          [HasV5TEOps]>;
 230
 231 // V6 Processors.
 232 def : Processor<"arm1136j-s",       ARMV6Itineraries, [HasV6Ops]>;
 233 def : Processor<"arm1136jf-s",      ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
 234                                                        FeatureHasSlowFPVMLx]>;
 235 def : Processor<"arm1176jz-s",      ARMV6Itineraries, [HasV6Ops]>;
 236 def : Processor<"arm1176jzf-s",     ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
 237                                                        FeatureHasSlowFPVMLx]>;
 238 def : Processor<"mpcorenovfp",      ARMV6Itineraries, [HasV6Ops]>;
 239 def : Processor<"mpcore",           ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
 240                                                        FeatureHasSlowFPVMLx]>;
 241
 242 // V6M Processors.
 243 def : Processor<"cortex-m0",        ARMV6Itineraries, [HasV6Ops, FeatureNoARM,
 244                                                        FeatureDB, FeatureMClass]>;
 245
 246 // V6T2 Processors.
 247 def : Processor<"arm1156t2-s",      ARMV6Itineraries, [HasV6T2Ops,
 248                                                        FeatureDSPThumb2]>;
 249 def : Processor<"arm1156t2f-s",     ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
 250                                                        FeatureHasSlowFPVMLx,
 251                                                        FeatureDSPThumb2]>;
 252
 253 // V7a Processors.
 254 // FIXME: A5 has currently the same Schedule model as A8
 255 def : ProcessorModel<"cortex-a5",   CortexA8Model,
 256                                     [ProcA5, HasV7Ops, FeatureNEON, FeatureDB,
 257                                      FeatureVFP4, FeatureDSPThumb2,
 258                                      FeatureHasRAS]>;
 259 def : ProcessorModel<"cortex-a8",   CortexA8Model,
 260                                     [ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
 261                                      FeatureDSPThumb2, FeatureHasRAS]>;
 262 def : ProcessorModel<"cortex-a9",   CortexA9Model,
 263                                     [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
 264                                      FeatureDSPThumb2, FeatureHasRAS]>;
 265 def : ProcessorModel<"cortex-a9-mp", CortexA9Model,
 266                                     [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
 267                                      FeatureDSPThumb2, FeatureMP,
 268                                      FeatureHasRAS]>;
 269 // FIXME: A15 has currently the same ProcessorModel as A9.
 270 def : ProcessorModel<"cortex-a15",   CortexA9Model,
 271                                     [ProcA15, HasV7Ops, FeatureNEON, FeatureDB,
 272                                      FeatureDSPThumb2, FeatureHasRAS]>;
 273 // FIXME: R5 has currently the same ProcessorModel as A8.
 274 def : ProcessorModel<"cortex-r5",   CortexA8Model,
 275                                     [ProcR5, HasV7Ops, FeatureDB,
 276                                      FeatureVFP3, FeatureDSPThumb2,
 277                                      FeatureHasRAS]>;
 278
 279 // V7M Processors.
 280 def : ProcNoItin<"cortex-m3",       [HasV7Ops,
 281                                      FeatureThumb2, FeatureNoARM, FeatureDB,
 282                                      FeatureHWDiv, FeatureMClass]>;
 283
 284 // V7EM Processors.
 285 def : ProcNoItin<"cortex-m4",       [HasV7Ops,
 286                                      FeatureThumb2, FeatureNoARM, FeatureDB,
 287                                      FeatureHWDiv, FeatureDSPThumb2,
 288                                      FeatureT2XtPk, FeatureVFP4,
 289                                      FeatureVFPOnlySP, FeatureMClass]>;
 290
 291 // Swift uArch Processors.
 292 def : ProcessorModel<"swift",       SwiftModel,
 293                                     [ProcSwift, HasV7Ops, FeatureNEON,
 294                                      FeatureDB, FeatureDSPThumb2,
 295                                      FeatureHasRAS]>;
 296
 297 // V8 Processors
 298 def : ProcNoItin<"cortex-a53",      [HasV8Ops]>;
 299
 300 //===----------------------------------------------------------------------===//
 301 // Register File Description
 302 //===----------------------------------------------------------------------===//
 303
 304 include "ARMRegisterInfo.td"
 305
 306 include "ARMCallingConv.td"
 307
 308 //===----------------------------------------------------------------------===//
 309 // Instruction Descriptions
 310 //===----------------------------------------------------------------------===//
 311
 312 include "ARMInstrInfo.td"
 313
 314 def ARMInstrInfo : InstrInfo;
 315
 316
 317 //===----------------------------------------------------------------------===//
 318 // Assembly printer
 319 //===----------------------------------------------------------------------===//
 320 // ARM Uses the MC printer for asm output, so make sure the TableGen
 321 // AsmWriter bits get associated with the correct class.
 322 def ARMAsmWriter : AsmWriter {
 323   string AsmWriterClassName  = "InstPrinter";
 324   bit isMCAsmWriter = 1;
 325 }
 326
 327 //===----------------------------------------------------------------------===//
 328 // Declare the target which we are implementing
 329 //===----------------------------------------------------------------------===//
 330
 331 def ARM : Target {
 332   // Pull in Instruction Info:
 333   let InstructionSet = ARMInstrInfo;
 334
 335   let AssemblyWriters = [ARMAsmWriter];
 336 }