lib/Target/ARM/ARM.td

   1 //===- ARM.td - Describe the ARM Target Machine ------------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Target-independent interfaces which we are implementing
  15 //===----------------------------------------------------------------------===//
  16
  17 include "llvm/Target/Target.td"
  18
  19
  20 //===----------------------------------------------------------------------===//
  21 // ARM Subtarget features.
  22 //
  23
  24 def FeatureVFP2 : SubtargetFeature<"vfp2", "ARMFPUType", "VFPv2",
  25                                    "Enable VFP2 instructions">;
  26 def FeatureVFP3 : SubtargetFeature<"vfp3", "ARMFPUType", "VFPv3",
  27                                    "Enable VFP3 instructions">;
  28 def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON",
  29                                    "Enable NEON instructions">;
  30 def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2",
  31                                      "Enable Thumb2 instructions">;
  32 def FeatureNoARM  : SubtargetFeature<"noarm", "NoARM", "true",
  33                                      "Does not support ARM mode execution">;
  34 def FeatureFP16   : SubtargetFeature<"fp16", "HasFP16", "true",
  35                                      "Enable half-precision floating point">;
  36 def FeatureD16    : SubtargetFeature<"d16", "HasD16", "true",
  37                                      "Restrict VFP3 to 16 double registers">;
  38 def FeatureHWDiv  : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
  39                                      "Enable divide instructions">;
  40 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
  41                                  "Enable Thumb2 extract and pack instructions">;
  42 def FeatureDB     : SubtargetFeature<"db", "HasDataBarrier", "true",
  43                                    "Has data barrier (dmb / dsb) instructions">;
  44 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
  45                                          "FP compare + branch is slow">;
  46 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
  47                           "Floating point unit supports single precision only">;
  48
  49 // Some processors have multiply-accumulate instructions that don't
  50 // play nicely with other VFP instructions, and it's generally better
  51 // to just not use them.
  52 // FIXME: Currently, this is only flagged for Cortex-A8. It may be true for
  53 // others as well. We should do more benchmarking and confirm one way or
  54 // the other.
  55 def FeatureHasSlowVMLx : SubtargetFeature<"vmlx", "SlowVMLx", "true",
  56                                           "Disable VFP MAC instructions">;
  57 // Some processors benefit from using NEON instructions for scalar
  58 // single-precision FP operations.
  59 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
  60                                         "true",
  61                                         "Use NEON for single precision FP">;
  62
  63 // Disable 32-bit to 16-bit narrowing for experimentation.
  64 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
  65                                              "Prefer 32-bit Thumb instrs">;
  66
  67
  68 // ARM architectures.
  69 def ArchV4T     : SubtargetFeature<"v4t", "ARMArchVersion", "V4T",
  70                                    "ARM v4T">;
  71 def ArchV5T     : SubtargetFeature<"v5t", "ARMArchVersion", "V5T",
  72                                    "ARM v5T">;
  73 def ArchV5TE    : SubtargetFeature<"v5te", "ARMArchVersion", "V5TE",
  74                                    "ARM v5TE, v5TEj, v5TExp">;
  75 def ArchV6      : SubtargetFeature<"v6", "ARMArchVersion", "V6",
  76                                    "ARM v6">;
  77 def ArchV6M     : SubtargetFeature<"v6m", "ARMArchVersion", "V6M",
  78                                    "ARM v6m",
  79                                    [FeatureNoARM, FeatureDB]>;
  80 def ArchV6T2    : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2",
  81                                    "ARM v6t2",
  82                                    [FeatureThumb2]>;
  83 def ArchV7A     : SubtargetFeature<"v7a", "ARMArchVersion", "V7A",
  84                                    "ARM v7A",
  85                                    [FeatureThumb2, FeatureNEON, FeatureDB]>;
  86 def ArchV7M     : SubtargetFeature<"v7m", "ARMArchVersion", "V7M",
  87                                    "ARM v7M",
  88                                    [FeatureThumb2, FeatureNoARM, FeatureDB,
  89                                     FeatureHWDiv]>;
  90
  91 //===----------------------------------------------------------------------===//
  92 // ARM Processors supported.
  93 //
  94
  95 include "ARMSchedule.td"
  96
  97 // ARM processor families.
  98 def ProcOthers  : SubtargetFeature<"others", "ARMProcFamily", "Others",
  99                                    "One of the other ARM processor families">;
 100 def ProcA8      : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
 101                                    "Cortex-A8 ARM processors",
 102                                    [FeatureSlowFPBrcc, FeatureNEONForFP]>;
 103 def ProcA9      : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
 104                                    "Cortex-A9 ARM processors">;
 105
 106 class ProcNoItin<string Name, list<SubtargetFeature> Features>
 107  : Processor<Name, GenericItineraries, Features>;
 108
 109 // V4 Processors.
 110 def : ProcNoItin<"generic",         []>;
 111 def : ProcNoItin<"arm8",            []>;
 112 def : ProcNoItin<"arm810",          []>;
 113 def : ProcNoItin<"strongarm",       []>;
 114 def : ProcNoItin<"strongarm110",    []>;
 115 def : ProcNoItin<"strongarm1100",   []>;
 116 def : ProcNoItin<"strongarm1110",   []>;
 117
 118 // V4T Processors.
 119 def : ProcNoItin<"arm7tdmi",        [ArchV4T]>;
 120 def : ProcNoItin<"arm7tdmi-s",      [ArchV4T]>;
 121 def : ProcNoItin<"arm710t",         [ArchV4T]>;
 122 def : ProcNoItin<"arm720t",         [ArchV4T]>;
 123 def : ProcNoItin<"arm9",            [ArchV4T]>;
 124 def : ProcNoItin<"arm9tdmi",        [ArchV4T]>;
 125 def : ProcNoItin<"arm920",          [ArchV4T]>;
 126 def : ProcNoItin<"arm920t",         [ArchV4T]>;
 127 def : ProcNoItin<"arm922t",         [ArchV4T]>;
 128 def : ProcNoItin<"arm940t",         [ArchV4T]>;
 129 def : ProcNoItin<"ep9312",          [ArchV4T]>;
 130
 131 // V5T Processors.
 132 def : ProcNoItin<"arm10tdmi",       [ArchV5T]>;
 133 def : ProcNoItin<"arm1020t",        [ArchV5T]>;
 134
 135 // V5TE Processors.
 136 def : ProcNoItin<"arm9e",           [ArchV5TE]>;
 137 def : ProcNoItin<"arm926ej-s",      [ArchV5TE]>;
 138 def : ProcNoItin<"arm946e-s",       [ArchV5TE]>;
 139 def : ProcNoItin<"arm966e-s",       [ArchV5TE]>;
 140 def : ProcNoItin<"arm968e-s",       [ArchV5TE]>;
 141 def : ProcNoItin<"arm10e",          [ArchV5TE]>;
 142 def : ProcNoItin<"arm1020e",        [ArchV5TE]>;
 143 def : ProcNoItin<"arm1022e",        [ArchV5TE]>;
 144 def : ProcNoItin<"xscale",          [ArchV5TE]>;
 145 def : ProcNoItin<"iwmmxt",          [ArchV5TE]>;
 146
 147 // V6 Processors.
 148 def : Processor<"arm1136j-s",       ARMV6Itineraries, [ArchV6]>;
 149 def : Processor<"arm1136jf-s",      ARMV6Itineraries, [ArchV6, FeatureVFP2,
 150                                                        FeatureHasSlowVMLx]>;
 151 def : Processor<"arm1176jz-s",      ARMV6Itineraries, [ArchV6]>;
 152 def : Processor<"arm1176jzf-s",     ARMV6Itineraries, [ArchV6, FeatureVFP2]>;
 153 def : Processor<"mpcorenovfp",      ARMV6Itineraries, [ArchV6]>;
 154 def : Processor<"mpcore",           ARMV6Itineraries, [ArchV6, FeatureVFP2]>;
 155
 156 // V6M Processors.
 157 def : Processor<"cortex-m0",        ARMV6Itineraries, [ArchV6M]>;
 158
 159 // V6T2 Processors.
 160 def : Processor<"arm1156t2-s",      ARMV6Itineraries, [ArchV6T2]>;
 161 def : Processor<"arm1156t2f-s",     ARMV6Itineraries, [ArchV6T2, FeatureVFP2]>;
 162
 163 // V7 Processors.
 164 def : Processor<"cortex-a8",        CortexA8Itineraries,
 165                                     [ArchV7A, ProcA8,
 166                                      FeatureHasSlowVMLx, FeatureT2XtPk]>;
 167 def : Processor<"cortex-a9",        CortexA9Itineraries,
 168                                     [ArchV7A, ProcA9, FeatureT2XtPk]>;
 169
 170 // V7M Processors.
 171 def : ProcNoItin<"cortex-m3",       [ArchV7M]>;
 172 def : ProcNoItin<"cortex-m4",       [ArchV7M, FeatureVFP2, FeatureVFPOnlySP]>;
 173
 174 //===----------------------------------------------------------------------===//
 175 // Register File Description
 176 //===----------------------------------------------------------------------===//
 177
 178 include "ARMRegisterInfo.td"
 179
 180 include "ARMCallingConv.td"
 181
 182 //===----------------------------------------------------------------------===//
 183 // Instruction Descriptions
 184 //===----------------------------------------------------------------------===//
 185
 186 include "ARMInstrInfo.td"
 187
 188 def ARMInstrInfo : InstrInfo;
 189
 190
 191 //===----------------------------------------------------------------------===//
 192 // Assembly printer
 193 //===----------------------------------------------------------------------===//
 194 // ARM Uses the MC printer for asm output, so make sure the TableGen
 195 // AsmWriter bits get associated with the correct class.
 196 def ARMAsmWriter : AsmWriter {
 197   string AsmWriterClassName  = "InstPrinter";
 198   bit isMCAsmWriter = 1;
 199 }
 200
 201 //===----------------------------------------------------------------------===//
 202 // Declare the target which we are implementing
 203 //===----------------------------------------------------------------------===//
 204
 205 def ARM : Target {
 206   // Pull in Instruction Info:
 207   let InstructionSet = ARMInstrInfo;
 208
 209   let AssemblyWriters = [ARMAsmWriter];
 210 }