lib/Target/ARM/ARM.td

   1 //===- ARM.td - Describe the ARM Target Machine ------------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Target-independent interfaces which we are implementing
  15 //===----------------------------------------------------------------------===//
  16
  17 include "llvm/Target/Target.td"
  18
  19
  20 //===----------------------------------------------------------------------===//
  21 // ARM Subtarget features.
  22 //
  23
  24 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
  25                                    "Enable VFP2 instructions">;
  26 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
  27                                    "Enable VFP3 instructions",
  28                                    [FeatureVFP2]>;
  29 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
  30                                    "Enable NEON instructions",
  31                                    [FeatureVFP3]>;
  32 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
  33                                      "Enable Thumb2 instructions">;
  34 def FeatureNoARM  : SubtargetFeature<"noarm", "NoARM", "true",
  35                                      "Does not support ARM mode execution">;
  36 def FeatureFP16   : SubtargetFeature<"fp16", "HasFP16", "true",
  37                                      "Enable half-precision floating point">;
  38 def FeatureD16    : SubtargetFeature<"d16", "HasD16", "true",
  39                                      "Restrict VFP3 to 16 double registers">;
  40 def FeatureHWDiv  : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
  41                                      "Enable divide instructions">;
  42 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
  43                                  "Enable Thumb2 extract and pack instructions">;
  44 def FeatureDB     : SubtargetFeature<"db", "HasDataBarrier", "true",
  45                                    "Has data barrier (dmb / dsb) instructions">;
  46 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
  47                                          "FP compare + branch is slow">;
  48 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
  49                           "Floating point unit supports single precision only">;
  50
  51 // Some processors have FP multiply-accumulate instructions that don't
  52 // play nicely with other VFP / NEON instructions, and it's generally better
  53 // to just not use them.
  54 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
  55                                          "Disable VFP / NEON MAC instructions">;
  56
  57 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
  58 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
  59                                        "HasVMLxForwarding", "true",
  60                                        "Has multiplier accumulator forwarding">;
  61
  62 // Some processors benefit from using NEON instructions for scalar
  63 // single-precision FP operations.
  64 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
  65                                         "true",
  66                                         "Use NEON for single precision FP">;
  67
  68 // Disable 32-bit to 16-bit narrowing for experimentation.
  69 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
  70                                              "Prefer 32-bit Thumb instrs">;
  71
  72 /// Some instructions update CPSR partially, which can add false dependency for
  73 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
  74 /// mapped to a separate physical register. Avoid partial CPSR update for these
  75 /// processors.
  76 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
  77                                                "AvoidCPSRPartialUpdate", "true",
  78                                  "Avoid CPSR partial update for OOO execution">;
  79
  80 /// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
  81 def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
  82                                  "Supports v7 DSP instructions in Thumb2.">;
  83
  84 // Multiprocessing extension.
  85 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
  86                                  "Supports Multiprocessing extension">;
  87
  88 // ARM architectures.
  89 def HasV4TOps   : SubtargetFeature<"v4t", "HasV4TOps", "true",
  90                                    "ARM v4T">;
  91 def HasV5TOps   : SubtargetFeature<"v5t", "HasV5TOps", "true",
  92                                    "ARM v5T",
  93                                    [HasV4TOps]>;
  94 def HasV5TEOps  : SubtargetFeature<"v5te", "HasV5TEOps", "true",
  95                                    "ARM v5TE, v5TEj, v5TExp",
  96                                    [HasV5TOps]>;
  97 def HasV6Ops    : SubtargetFeature<"v6", "HasV6Ops", "true",
  98                                    "ARM v6",
  99                                    [HasV5TEOps]>;
 100 def HasV6T2Ops  : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
 101                                    "ARM v6t2",
 102                                    [HasV6Ops, FeatureThumb2, FeatureDSPThumb2]>;
 103 def HasV7Ops    : SubtargetFeature<"v7", "HasV7Ops", "true",
 104                                    "ARM v7",
 105                                    [HasV6T2Ops]>;
 106
 107 //===----------------------------------------------------------------------===//
 108 // ARM Processors supported.
 109 //
 110
 111 include "ARMSchedule.td"
 112
 113 // ARM processor families.
 114 def ProcOthers  : SubtargetFeature<"others", "ARMProcFamily", "Others",
 115                                    "One of the other ARM processor families">;
 116 def ProcA8      : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
 117                                    "Cortex-A8 ARM processors",
 118                                    [FeatureSlowFPBrcc, FeatureNEONForFP,
 119                                     FeatureHasSlowFPVMLx, FeatureVMLxForwarding,
 120                                     FeatureT2XtPk]>;
 121 def ProcA9      : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
 122                                    "Cortex-A9 ARM processors",
 123                                    [FeatureVMLxForwarding,
 124                                     FeatureT2XtPk, FeatureFP16,
 125                                     FeatureAvoidPartialCPSR]>;
 126
 127 class ProcNoItin<string Name, list<SubtargetFeature> Features>
 128  : Processor<Name, GenericItineraries, Features>;
 129
 130 // V4 Processors.
 131 def : ProcNoItin<"generic",         []>;
 132 def : ProcNoItin<"arm8",            []>;
 133 def : ProcNoItin<"arm810",          []>;
 134 def : ProcNoItin<"strongarm",       []>;
 135 def : ProcNoItin<"strongarm110",    []>;
 136 def : ProcNoItin<"strongarm1100",   []>;
 137 def : ProcNoItin<"strongarm1110",   []>;
 138
 139 // V4T Processors.
 140 def : ProcNoItin<"arm7tdmi",        [HasV4TOps]>;
 141 def : ProcNoItin<"arm7tdmi-s",      [HasV4TOps]>;
 142 def : ProcNoItin<"arm710t",         [HasV4TOps]>;
 143 def : ProcNoItin<"arm720t",         [HasV4TOps]>;
 144 def : ProcNoItin<"arm9",            [HasV4TOps]>;
 145 def : ProcNoItin<"arm9tdmi",        [HasV4TOps]>;
 146 def : ProcNoItin<"arm920",          [HasV4TOps]>;
 147 def : ProcNoItin<"arm920t",         [HasV4TOps]>;
 148 def : ProcNoItin<"arm922t",         [HasV4TOps]>;
 149 def : ProcNoItin<"arm940t",         [HasV4TOps]>;
 150 def : ProcNoItin<"ep9312",          [HasV4TOps]>;
 151
 152 // V5T Processors.
 153 def : ProcNoItin<"arm10tdmi",       [HasV5TOps]>;
 154 def : ProcNoItin<"arm1020t",        [HasV5TOps]>;
 155
 156 // V5TE Processors.
 157 def : ProcNoItin<"arm9e",           [HasV5TEOps]>;
 158 def : ProcNoItin<"arm926ej-s",      [HasV5TEOps]>;
 159 def : ProcNoItin<"arm946e-s",       [HasV5TEOps]>;
 160 def : ProcNoItin<"arm966e-s",       [HasV5TEOps]>;
 161 def : ProcNoItin<"arm968e-s",       [HasV5TEOps]>;
 162 def : ProcNoItin<"arm10e",          [HasV5TEOps]>;
 163 def : ProcNoItin<"arm1020e",        [HasV5TEOps]>;
 164 def : ProcNoItin<"arm1022e",        [HasV5TEOps]>;
 165 def : ProcNoItin<"xscale",          [HasV5TEOps]>;
 166 def : ProcNoItin<"iwmmxt",          [HasV5TEOps]>;
 167
 168 // V6 Processors.
 169 def : Processor<"arm1136j-s",       ARMV6Itineraries, [HasV6Ops]>;
 170 def : Processor<"arm1136jf-s",      ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
 171                                                        FeatureHasSlowFPVMLx]>;
 172 def : Processor<"arm1176jz-s",      ARMV6Itineraries, [HasV6Ops]>;
 173 def : Processor<"arm1176jzf-s",     ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
 174                                                        FeatureHasSlowFPVMLx]>;
 175 def : Processor<"mpcorenovfp",      ARMV6Itineraries, [HasV6Ops]>;
 176 def : Processor<"mpcore",           ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
 177                                                        FeatureHasSlowFPVMLx]>;
 178
 179 // V6M Processors.
 180 def : Processor<"cortex-m0",        ARMV6Itineraries, [HasV6Ops, FeatureNoARM,
 181                                                        FeatureDB]>;
 182
 183 // V6T2 Processors.
 184 def : Processor<"arm1156t2-s",      ARMV6Itineraries, [HasV6T2Ops]>;
 185 def : Processor<"arm1156t2f-s",     ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
 186                                                        FeatureHasSlowFPVMLx]>;
 187
 188 // V7a Processors.
 189 def : Processor<"cortex-a8",        CortexA8Itineraries,
 190                                     [ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
 191                                      FeatureDSPThumb2]>;
 192 def : Processor<"cortex-a9",        CortexA9Itineraries,
 193                                     [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
 194                                      FeatureDSPThumb2]>;
 195 def : Processor<"cortex-a9-mp",     CortexA9Itineraries,
 196                                     [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
 197                                      FeatureDSPThumb2, FeatureMP]>;
 198
 199 // V7M Processors.
 200 def : ProcNoItin<"cortex-m3",       [HasV7Ops,
 201                                      FeatureThumb2, FeatureNoARM, FeatureDB,
 202                                      FeatureHWDiv]>;
 203
 204 // V7EM Processors.
 205 def : ProcNoItin<"cortex-m4",       [HasV7Ops,
 206                                      FeatureThumb2, FeatureNoARM, FeatureDB,
 207                                      FeatureHWDiv, FeatureDSPThumb2,
 208                                      FeatureT2XtPk, FeatureVFP2,
 209                                      FeatureVFPOnlySP]>;
 210
 211 //===----------------------------------------------------------------------===//
 212 // Register File Description
 213 //===----------------------------------------------------------------------===//
 214
 215 include "ARMRegisterInfo.td"
 216
 217 include "ARMCallingConv.td"
 218
 219 //===----------------------------------------------------------------------===//
 220 // Instruction Descriptions
 221 //===----------------------------------------------------------------------===//
 222
 223 include "ARMInstrInfo.td"
 224
 225 def ARMInstrInfo : InstrInfo;
 226
 227
 228 //===----------------------------------------------------------------------===//
 229 // Assembly printer
 230 //===----------------------------------------------------------------------===//
 231 // ARM Uses the MC printer for asm output, so make sure the TableGen
 232 // AsmWriter bits get associated with the correct class.
 233 def ARMAsmWriter : AsmWriter {
 234   string AsmWriterClassName  = "InstPrinter";
 235   bit isMCAsmWriter = 1;
 236 }
 237
 238 //===----------------------------------------------------------------------===//
 239 // Declare the target which we are implementing
 240 //===----------------------------------------------------------------------===//
 241
 242 def ARM : Target {
 243   // Pull in Instruction Info:
 244   let InstructionSet = ARMInstrInfo;
 245
 246   let AssemblyWriters = [ARMAsmWriter];
 247 }