lib/Target/ARM/ARM.td

   1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Target-independent interfaces which we are implementing
  15 //===----------------------------------------------------------------------===//
  16
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // ARM Subtarget state.
  21 //
  22
  23 def ModeThumb  : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
  24                                   "Thumb mode">;
  25
  26 def ModeSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
  27                                      "Use software floating point features.">;
  28
  29 //===----------------------------------------------------------------------===//
  30 // ARM Subtarget features.
  31 //
  32
  33 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
  34                                    "Enable VFP2 instructions">;
  35 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
  36                                    "Enable VFP3 instructions",
  37                                    [FeatureVFP2]>;
  38 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
  39                                    "Enable NEON instructions",
  40                                    [FeatureVFP3]>;
  41 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
  42                                      "Enable Thumb2 instructions">;
  43 def FeatureNoARM  : SubtargetFeature<"noarm", "NoARM", "true",
  44                                      "Does not support ARM mode execution",
  45                                      [ModeThumb]>;
  46 def FeatureFP16   : SubtargetFeature<"fp16", "HasFP16", "true",
  47                                      "Enable half-precision floating point">;
  48 def FeatureVFP4   : SubtargetFeature<"vfp4", "HasVFPv4", "true",
  49                                      "Enable VFP4 instructions",
  50                                      [FeatureVFP3, FeatureFP16]>;
  51 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8",
  52                                    "true", "Enable ARMv8 FP",
  53                                    [FeatureVFP4]>;
  54 def FeatureD16    : SubtargetFeature<"d16", "HasD16", "true",
  55                                      "Restrict VFP3 to 16 double registers">;
  56 def FeatureHWDiv  : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
  57                                      "Enable divide instructions">;
  58 def FeatureHWDivARM  : SubtargetFeature<"hwdiv-arm",
  59                                         "HasHardwareDivideInARM", "true",
  60                                       "Enable divide instructions in ARM mode">;
  61 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
  62                                  "Enable Thumb2 extract and pack instructions">;
  63 def FeatureDB     : SubtargetFeature<"db", "HasDataBarrier", "true",
  64                                    "Has data barrier (dmb / dsb) instructions">;
  65 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
  66                                          "FP compare + branch is slow">;
  67 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
  68                           "Floating point unit supports single precision only">;
  69 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
  70                            "Enable support for Performance Monitor extensions">;
  71 def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
  72                           "Enable support for TrustZone security extensions">;
  73 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
  74                           "Enable support for Cryptography extensions",
  75                           [FeatureNEON]>;
  76 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
  77                           "Enable support for CRC instructions">;
  78
  79 // Cyclone has preferred instructions for zeroing VFP registers, which can
  80 // execute in 0 cycles.
  81 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
  82                                         "Has zero-cycle zeroing instructions">;
  83
  84 // Some processors have FP multiply-accumulate instructions that don't
  85 // play nicely with other VFP / NEON instructions, and it's generally better
  86 // to just not use them.
  87 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
  88                                          "Disable VFP / NEON MAC instructions">;
  89
  90 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
  91 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
  92                                        "HasVMLxForwarding", "true",
  93                                        "Has multiplier accumulator forwarding">;
  94
  95 // Some processors benefit from using NEON instructions for scalar
  96 // single-precision FP operations.
  97 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
  98                                         "true",
  99                                         "Use NEON for single precision FP">;
 100
 101 // Disable 32-bit to 16-bit narrowing for experimentation.
 102 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
 103                                              "Prefer 32-bit Thumb instrs">;
 104
 105 /// Some instructions update CPSR partially, which can add false dependency for
 106 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
 107 /// mapped to a separate physical register. Avoid partial CPSR update for these
 108 /// processors.
 109 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
 110                                                "AvoidCPSRPartialUpdate", "true",
 111                                  "Avoid CPSR partial update for OOO execution">;
 112
 113 def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
 114                                             "AvoidMOVsShifterOperand", "true",
 115                                 "Avoid movs instructions with shifter operand">;
 116
 117 // Some processors perform return stack prediction. CodeGen should avoid issue
 118 // "normal" call instructions to callees which do not return.
 119 def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true",
 120                                      "Has return address stack">;
 121
 122 /// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
 123 def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
 124                                  "Supports v7 DSP instructions in Thumb2">;
 125
 126 // Multiprocessing extension.
 127 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
 128                                  "Supports Multiprocessing extension">;
 129
 130 // Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
 131 def FeatureVirtualization : SubtargetFeature<"virtualization",
 132                                  "HasVirtualization", "true",
 133                                  "Supports Virtualization extension",
 134                                  [FeatureHWDiv, FeatureHWDivARM]>;
 135
 136 // M-series ISA
 137 def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
 138                                      "Is microcontroller profile ('M' series)">;
 139
 140 // R-series ISA
 141 def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
 142                                      "Is realtime profile ('R' series)">;
 143
 144 // A-series ISA
 145 def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
 146                                      "Is application profile ('A' series)">;
 147
 148 // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
 149 // See ARMInstrInfo.td for details.
 150 def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
 151                                        "NaCl trap">;
 152
 153 def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true",
 154                                         "Generate calls via indirect call "
 155                                         "instructions">;
 156
 157 def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
 158                                         "Reserve R9, making it unavailable as "
 159                                         "GPR">;
 160
 161 def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true",
 162                                      "Don't use movt/movw pairs for 32-bit "
 163                                      "imms">;
 164
 165 // ARM ISAs.
 166 def HasV4TOps   : SubtargetFeature<"v4t", "HasV4TOps", "true",
 167                                    "Support ARM v4T instructions">;
 168 def HasV5TOps   : SubtargetFeature<"v5t", "HasV5TOps", "true",
 169                                    "Support ARM v5T instructions",
 170                                    [HasV4TOps]>;
 171 def HasV5TEOps  : SubtargetFeature<"v5te", "HasV5TEOps", "true",
 172                              "Support ARM v5TE, v5TEj, and v5TExp instructions",
 173                                    [HasV5TOps]>;
 174 def HasV6Ops    : SubtargetFeature<"v6", "HasV6Ops", "true",
 175                                    "Support ARM v6 instructions",
 176                                    [HasV5TEOps]>;
 177 def HasV6MOps   : SubtargetFeature<"v6m", "HasV6MOps", "true",
 178                                    "Support ARM v6M instructions",
 179                                    [HasV6Ops]>;
 180 def HasV6KOps   : SubtargetFeature<"v6k", "HasV6KOps", "true",
 181                                    "Support ARM v6k instructions",
 182                                    [HasV6Ops]>;
 183 def HasV6T2Ops  : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
 184                                    "Support ARM v6t2 instructions",
 185                                    [HasV6MOps, HasV6KOps, FeatureThumb2]>;
 186 def HasV7Ops    : SubtargetFeature<"v7", "HasV7Ops", "true",
 187                                    "Support ARM v7 instructions",
 188                                    [HasV6T2Ops, FeaturePerfMon]>;
 189 def HasV8Ops    : SubtargetFeature<"v8", "HasV8Ops", "true",
 190                                    "Support ARM v8 instructions",
 191                                    [HasV7Ops, FeatureVirtualization,
 192                                     FeatureMP]>;
 193 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
 194                                    "Support ARM v8.1a instructions",
 195                                    [HasV8Ops, FeatureAClass, FeatureCRC]>;
 196
 197 //===----------------------------------------------------------------------===//
 198 // ARM Processors supported.
 199 //
 200
 201 include "ARMSchedule.td"
 202
 203 // ARM processor families.
 204 def ProcA5      : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
 205                                    "Cortex-A5 ARM processors",
 206                                    [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
 207                                     FeatureVMLxForwarding, FeatureT2XtPk,
 208                                     FeatureTrustZone, FeatureMP]>;
 209 def ProcA7      : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7",
 210                                    "Cortex-A7 ARM processors",
 211                                    [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
 212                                     FeatureVMLxForwarding, FeatureT2XtPk,
 213                                     FeatureVFP4, FeatureMP,
 214                                     FeatureHWDiv, FeatureHWDivARM,
 215                                     FeatureTrustZone, FeatureVirtualization]>;
 216 def ProcA8      : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
 217                                    "Cortex-A8 ARM processors",
 218                                    [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
 219                                     FeatureVMLxForwarding, FeatureT2XtPk,
 220                                     FeatureTrustZone]>;
 221 def ProcA9      : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
 222                                    "Cortex-A9 ARM processors",
 223                                    [FeatureVMLxForwarding,
 224                                     FeatureT2XtPk, FeatureFP16,
 225                                     FeatureAvoidPartialCPSR,
 226                                     FeatureTrustZone]>;
 227 def ProcSwift   : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
 228                                    "Swift ARM processors",
 229                                    [FeatureNEONForFP, FeatureT2XtPk,
 230                                     FeatureVFP4, FeatureMP, FeatureHWDiv,
 231                                     FeatureHWDivARM, FeatureAvoidPartialCPSR,
 232                                     FeatureAvoidMOVsShOp,
 233                                     FeatureHasSlowFPVMLx, FeatureTrustZone]>;
 234 def ProcA12     : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12",
 235                                    "Cortex-A12 ARM processors",
 236                                    [FeatureVMLxForwarding,
 237                                     FeatureT2XtPk, FeatureVFP4,
 238                                     FeatureHWDiv, FeatureHWDivARM,
 239                                     FeatureAvoidPartialCPSR,
 240                                     FeatureVirtualization,
 241                                     FeatureTrustZone]>;
 242
 243
 244 // FIXME: It has not been determined if A15 has these features.
 245 def ProcA15      : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
 246                                    "Cortex-A15 ARM processors",
 247                                    [FeatureT2XtPk, FeatureVFP4,
 248                                     FeatureMP, FeatureHWDiv, FeatureHWDivARM,
 249                                     FeatureAvoidPartialCPSR,
 250                                     FeatureTrustZone, FeatureVirtualization]>;
 251
 252 def ProcA17     : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17",
 253                                    "Cortex-A17 ARM processors",
 254                                    [FeatureVMLxForwarding,
 255                                     FeatureT2XtPk, FeatureVFP4,
 256                                     FeatureHWDiv, FeatureHWDivARM,
 257                                     FeatureAvoidPartialCPSR,
 258                                     FeatureVirtualization,
 259                                     FeatureTrustZone]>;
 260
 261 def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
 262                                    "Cortex-A53 ARM processors",
 263                                    [FeatureHWDiv, FeatureHWDivARM,
 264                                     FeatureTrustZone, FeatureT2XtPk,
 265                                     FeatureCrypto, FeatureCRC]>;
 266
 267 def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
 268                                    "Cortex-A57 ARM processors",
 269                                    [FeatureHWDiv, FeatureHWDivARM,
 270                                     FeatureTrustZone, FeatureT2XtPk,
 271                                     FeatureCrypto, FeatureCRC]>;
 272
 273 def ProcR4      : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4",
 274                                    "Cortex-R4 ARM processors",
 275                                    [FeatureHWDiv,
 276                                     FeatureAvoidPartialCPSR,
 277                                     FeatureDSPThumb2, FeatureT2XtPk,
 278                                     HasV7Ops, FeatureDB, FeatureHasRAS,
 279                                     FeatureRClass]>;
 280
 281 def ProcR5      : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
 282                                    "Cortex-R5 ARM processors",
 283                                    [FeatureSlowFPBrcc,
 284                                     FeatureHWDiv, FeatureHWDivARM,
 285                                     FeatureHasSlowFPVMLx,
 286                                     FeatureAvoidPartialCPSR,
 287                                     FeatureT2XtPk]>;
 288
 289 // FIXME: krait has currently the same features as A9
 290 // plus VFP4 and hardware division features.
 291 def ProcKrait   : SubtargetFeature<"krait", "ARMProcFamily", "Krait",
 292                                    "Qualcomm ARM processors",
 293                                    [FeatureVMLxForwarding,
 294                                     FeatureT2XtPk, FeatureFP16,
 295                                     FeatureAvoidPartialCPSR,
 296                                     FeatureTrustZone,
 297                                     FeatureVFP4,
 298                                     FeatureHWDiv,
 299                                     FeatureHWDivARM]>;
 300
 301
 302 class ProcNoItin<string Name, list<SubtargetFeature> Features>
 303  : Processor<Name, NoItineraries, Features>;
 304
 305 // V4 Processors.
 306 def : ProcNoItin<"generic",         []>;
 307 def : ProcNoItin<"arm8",            []>;
 308 def : ProcNoItin<"arm810",          []>;
 309 def : ProcNoItin<"strongarm",       []>;
 310 def : ProcNoItin<"strongarm110",    []>;
 311 def : ProcNoItin<"strongarm1100",   []>;
 312 def : ProcNoItin<"strongarm1110",   []>;
 313
 314 // V4T Processors.
 315 def : ProcNoItin<"arm7tdmi",        [HasV4TOps]>;
 316 def : ProcNoItin<"arm7tdmi-s",      [HasV4TOps]>;
 317 def : ProcNoItin<"arm710t",         [HasV4TOps]>;
 318 def : ProcNoItin<"arm720t",         [HasV4TOps]>;
 319 def : ProcNoItin<"arm9",            [HasV4TOps]>;
 320 def : ProcNoItin<"arm9tdmi",        [HasV4TOps]>;
 321 def : ProcNoItin<"arm920",          [HasV4TOps]>;
 322 def : ProcNoItin<"arm920t",         [HasV4TOps]>;
 323 def : ProcNoItin<"arm922t",         [HasV4TOps]>;
 324 def : ProcNoItin<"arm940t",         [HasV4TOps]>;
 325 def : ProcNoItin<"ep9312",          [HasV4TOps]>;
 326
 327 // V5T Processors.
 328 def : ProcNoItin<"arm10tdmi",       [HasV5TOps]>;
 329 def : ProcNoItin<"arm1020t",        [HasV5TOps]>;
 330
 331 // V5TE Processors.
 332 def : ProcNoItin<"arm9e",           [HasV5TEOps]>;
 333 def : ProcNoItin<"arm926ej-s",      [HasV5TEOps]>;
 334 def : ProcNoItin<"arm946e-s",       [HasV5TEOps]>;
 335 def : ProcNoItin<"arm966e-s",       [HasV5TEOps]>;
 336 def : ProcNoItin<"arm968e-s",       [HasV5TEOps]>;
 337 def : ProcNoItin<"arm10e",          [HasV5TEOps]>;
 338 def : ProcNoItin<"arm1020e",        [HasV5TEOps]>;
 339 def : ProcNoItin<"arm1022e",        [HasV5TEOps]>;
 340 def : ProcNoItin<"xscale",          [HasV5TEOps]>;
 341 def : ProcNoItin<"iwmmxt",          [HasV5TEOps]>;
 342
 343 // V6 Processors.
 344 def : Processor<"arm1136j-s",       ARMV6Itineraries, [HasV6Ops]>;
 345 def : Processor<"arm1136jf-s",      ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
 346                                                        FeatureHasSlowFPVMLx]>;
 347
 348 // V6M Processors.
 349 def : Processor<"cortex-m0",        ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
 350                                                        FeatureDB, FeatureMClass]>;
 351 def : Processor<"cortex-m0plus",    ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
 352                                                        FeatureDB, FeatureMClass]>;
 353 def : Processor<"cortex-m1",        ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
 354                                                        FeatureDB, FeatureMClass]>;
 355 def : Processor<"sc000",            ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
 356                                                        FeatureDB, FeatureMClass]>;
 357
 358 // V6K Processors.
 359 def : Processor<"arm1176jz-s",      ARMV6Itineraries, [HasV6KOps]>;
 360 def : Processor<"arm1176jzf-s",     ARMV6Itineraries, [HasV6KOps, FeatureVFP2,
 361                                                        FeatureHasSlowFPVMLx]>;
 362 def : Processor<"mpcorenovfp",      ARMV6Itineraries, [HasV6KOps]>;
 363 def : Processor<"mpcore",           ARMV6Itineraries, [HasV6KOps, FeatureVFP2,
 364                                                        FeatureHasSlowFPVMLx]>;
 365
 366 // V6T2 Processors.
 367 def : Processor<"arm1156t2-s",      ARMV6Itineraries, [HasV6T2Ops,
 368                                                        FeatureDSPThumb2]>;
 369 def : Processor<"arm1156t2f-s",     ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
 370                                                        FeatureHasSlowFPVMLx,
 371                                                        FeatureDSPThumb2]>;
 372
 373 // V7a Processors.
 374 // FIXME: A5 has currently the same Schedule model as A8
 375 def : ProcessorModel<"cortex-a5",   CortexA8Model,
 376                                     [ProcA5, HasV7Ops, FeatureNEON, FeatureDB,
 377                                      FeatureVFP4, FeatureDSPThumb2,
 378                                      FeatureHasRAS, FeatureAClass]>;
 379 def : ProcessorModel<"cortex-a7",   CortexA8Model,
 380                                     [ProcA7, HasV7Ops, FeatureNEON, FeatureDB,
 381                                      FeatureDSPThumb2, FeatureHasRAS,
 382                                      FeatureAClass]>;
 383 def : ProcessorModel<"cortex-a8",   CortexA8Model,
 384                                     [ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
 385                                      FeatureDSPThumb2, FeatureHasRAS,
 386                                      FeatureAClass]>;
 387 def : ProcessorModel<"cortex-a9",   CortexA9Model,
 388                                     [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
 389                                      FeatureDSPThumb2, FeatureHasRAS, FeatureMP,
 390                                      FeatureAClass]>;
 391
 392 // FIXME: A12 has currently the same Schedule model as A9
 393 def : ProcessorModel<"cortex-a12", CortexA9Model,
 394                                     [ProcA12, HasV7Ops, FeatureNEON, FeatureDB,
 395                                      FeatureDSPThumb2, FeatureMP,
 396                                      FeatureHasRAS, FeatureAClass]>;
 397
 398 // FIXME: A15 has currently the same ProcessorModel as A9.
 399 def : ProcessorModel<"cortex-a15",   CortexA9Model,
 400                                     [ProcA15, HasV7Ops, FeatureNEON, FeatureDB,
 401                                      FeatureDSPThumb2, FeatureHasRAS,
 402                                      FeatureAClass]>;
 403
 404 // FIXME: A17 has currently the same Schedule model as A9
 405 def : ProcessorModel<"cortex-a17",  CortexA9Model,
 406                                     [ProcA17, HasV7Ops, FeatureNEON, FeatureDB,
 407                                      FeatureDSPThumb2, FeatureMP,
 408                                      FeatureHasRAS, FeatureAClass]>;
 409
 410 // FIXME: krait has currently the same Schedule model as A9
 411 def : ProcessorModel<"krait",       CortexA9Model,
 412                                     [ProcKrait, HasV7Ops,
 413                                      FeatureNEON, FeatureDB,
 414                                      FeatureDSPThumb2, FeatureHasRAS,
 415                                      FeatureAClass]>;
 416
 417 // FIXME: R4 has currently the same ProcessorModel as A8.
 418 def : ProcessorModel<"cortex-r4",   CortexA8Model,
 419                                     [ProcR4]>;
 420
 421 // FIXME: R4F has currently the same ProcessorModel as A8.
 422 def : ProcessorModel<"cortex-r4f",  CortexA8Model,
 423                                     [ProcR4,
 424                                      FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
 425                                      FeatureVFP3, FeatureD16]>;
 426
 427 // FIXME: R5 has currently the same ProcessorModel as A8.
 428 def : ProcessorModel<"cortex-r5",   CortexA8Model,
 429                                     [ProcR5, HasV7Ops, FeatureDB,
 430                                      FeatureVFP3, FeatureDSPThumb2,
 431                                      FeatureHasRAS,
 432                                      FeatureD16, FeatureRClass]>;
 433
 434 // FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5.
 435 def : ProcessorModel<"cortex-r7",   CortexA8Model,
 436                                     [ProcR5, HasV7Ops, FeatureDB,
 437                                      FeatureVFP3, FeatureDSPThumb2,
 438                                      FeatureHasRAS, FeatureVFPOnlySP,
 439                                      FeatureD16, FeatureMP, FeatureRClass]>;
 440
 441 // V7M Processors.
 442 def : ProcNoItin<"cortex-m3",       [HasV7Ops,
 443                                      FeatureThumb2, FeatureNoARM, FeatureDB,
 444                                      FeatureHWDiv, FeatureMClass]>;
 445 def : ProcNoItin<"sc300",           [HasV7Ops,
 446                                      FeatureThumb2, FeatureNoARM, FeatureDB,
 447                                      FeatureHWDiv, FeatureMClass]>;
 448
 449 // V7EM Processors.
 450 def : ProcNoItin<"cortex-m4",       [HasV7Ops,
 451                                      FeatureThumb2, FeatureNoARM, FeatureDB,
 452                                      FeatureHWDiv, FeatureDSPThumb2,
 453                                      FeatureT2XtPk, FeatureVFP4,
 454                                      FeatureVFPOnlySP, FeatureD16,
 455                                      FeatureMClass]>;
 456 def : ProcNoItin<"cortex-m7",       [HasV7Ops,
 457                                      FeatureThumb2, FeatureNoARM, FeatureDB,
 458                                      FeatureHWDiv, FeatureDSPThumb2,
 459                                      FeatureT2XtPk, FeatureFPARMv8,
 460                                      FeatureD16, FeatureMClass]>;
 461
 462
 463 // Swift uArch Processors.
 464 def : ProcessorModel<"swift",       SwiftModel,
 465                                     [ProcSwift, HasV7Ops, FeatureNEON,
 466                                      FeatureDB, FeatureDSPThumb2,
 467                                      FeatureHasRAS, FeatureAClass]>;
 468
 469 // V8 Processors
 470 def : ProcNoItin<"cortex-a53",      [ProcA53, HasV8Ops, FeatureAClass,
 471                                     FeatureDB, FeatureFPARMv8,
 472                                     FeatureNEON, FeatureDSPThumb2]>;
 473 def : ProcNoItin<"cortex-a57",      [ProcA57, HasV8Ops, FeatureAClass,
 474                                     FeatureDB, FeatureFPARMv8,
 475                                     FeatureNEON, FeatureDSPThumb2]>;
 476 // FIXME: Cortex-A72 is currently modelled as an Cortex-A57.
 477 def : ProcNoItin<"cortex-a72",      [ProcA57, HasV8Ops, FeatureAClass,
 478                                     FeatureDB, FeatureFPARMv8,
 479                                     FeatureNEON, FeatureDSPThumb2]>;
 480
 481 // Cyclone is very similar to swift
 482 def : ProcessorModel<"cyclone",     SwiftModel,
 483                                     [ProcSwift, HasV8Ops, HasV7Ops,
 484                                      FeatureCrypto, FeatureFPARMv8,
 485                                      FeatureDB,FeatureDSPThumb2,
 486                                      FeatureHasRAS, FeatureZCZeroing]>;
 487
 488 //===----------------------------------------------------------------------===//
 489 // Register File Description
 490 //===----------------------------------------------------------------------===//
 491
 492 include "ARMRegisterInfo.td"
 493
 494 include "ARMCallingConv.td"
 495
 496 //===----------------------------------------------------------------------===//
 497 // Instruction Descriptions
 498 //===----------------------------------------------------------------------===//
 499
 500 include "ARMInstrInfo.td"
 501
 502 def ARMInstrInfo : InstrInfo;
 503
 504 //===----------------------------------------------------------------------===//
 505 // Declare the target which we are implementing
 506 //===----------------------------------------------------------------------===//
 507
 508 def ARMAsmWriter : AsmWriter {
 509   string AsmWriterClassName  = "InstPrinter";
 510   int PassSubtarget = 1;
 511   int Variant = 0;
 512   bit isMCAsmWriter = 1;
 513 }
 514
 515 def ARM : Target {
 516   // Pull in Instruction Info:
 517   let InstructionSet = ARMInstrInfo;
 518   let AssemblyWriters = [ARMAsmWriter];
 519 }