lib/Target/ARM/ARM.td

   1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Target-independent interfaces which we are implementing
  15 //===----------------------------------------------------------------------===//
  16
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // ARM Subtarget state.
  21 //
  22
  23 def ModeThumb  : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
  24                                   "Thumb mode">;
  25
  26 //===----------------------------------------------------------------------===//
  27 // ARM Subtarget features.
  28 //
  29
  30 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
  31                                    "Enable VFP2 instructions">;
  32 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
  33                                    "Enable VFP3 instructions",
  34                                    [FeatureVFP2]>;
  35 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
  36                                    "Enable NEON instructions",
  37                                    [FeatureVFP3]>;
  38 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
  39                                      "Enable Thumb2 instructions">;
  40 def FeatureNoARM  : SubtargetFeature<"noarm", "NoARM", "true",
  41                                      "Does not support ARM mode execution">;
  42 def FeatureFP16   : SubtargetFeature<"fp16", "HasFP16", "true",
  43                                      "Enable half-precision floating point">;
  44 def FeatureVFP4   : SubtargetFeature<"vfp4", "HasVFPv4", "true",
  45                                      "Enable VFP4 instructions",
  46                                      [FeatureVFP3, FeatureFP16]>;
  47 def FeatureD16    : SubtargetFeature<"d16", "HasD16", "true",
  48                                      "Restrict VFP3 to 16 double registers">;
  49 def FeatureHWDiv  : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
  50                                      "Enable divide instructions">;
  51 def FeatureHWDivARM  : SubtargetFeature<"hwdiv-arm",
  52                                         "HasHardwareDivideInARM", "true",
  53                                       "Enable divide instructions in ARM mode">;
  54 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
  55                                  "Enable Thumb2 extract and pack instructions">;
  56 def FeatureDB     : SubtargetFeature<"db", "HasDataBarrier", "true",
  57                                    "Has data barrier (dmb / dsb) instructions">;
  58 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
  59                                          "FP compare + branch is slow">;
  60 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
  61                           "Floating point unit supports single precision only">;
  62
  63 // Some processors have FP multiply-accumulate instructions that don't
  64 // play nicely with other VFP / NEON instructions, and it's generally better
  65 // to just not use them.
  66 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
  67                                          "Disable VFP / NEON MAC instructions">;
  68
  69 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
  70 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
  71                                        "HasVMLxForwarding", "true",
  72                                        "Has multiplier accumulator forwarding">;
  73
  74 // Some processors benefit from using NEON instructions for scalar
  75 // single-precision FP operations.
  76 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
  77                                         "true",
  78                                         "Use NEON for single precision FP">;
  79
  80 // Disable 32-bit to 16-bit narrowing for experimentation.
  81 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
  82                                              "Prefer 32-bit Thumb instrs">;
  83
  84 /// Some instructions update CPSR partially, which can add false dependency for
  85 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
  86 /// mapped to a separate physical register. Avoid partial CPSR update for these
  87 /// processors.
  88 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
  89                                                "AvoidCPSRPartialUpdate", "true",
  90                                  "Avoid CPSR partial update for OOO execution">;
  91
  92 def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
  93                                             "AvoidMOVsShifterOperand", "true",
  94                                 "Avoid movs instructions with shifter operand">;
  95
  96 // Some processors perform return stack prediction. CodeGen should avoid issue
  97 // "normal" call instructions to callees which do not return.
  98 def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true",
  99                                      "Has return address stack">;
 100
 101 /// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
 102 def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
 103                                  "Supports v7 DSP instructions in Thumb2">;
 104
 105 // Multiprocessing extension.
 106 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
 107                                  "Supports Multiprocessing extension">;
 108
 109 // M-series ISA?
 110 def FeatureMClass : SubtargetFeature<"mclass", "IsMClass", "true",
 111                                      "Is microcontroller profile ('M' series)">;
 112
 113 // ARM ISAs.
 114 def HasV4TOps   : SubtargetFeature<"v4t", "HasV4TOps", "true",
 115                                    "Support ARM v4T instructions">;
 116 def HasV5TOps   : SubtargetFeature<"v5t", "HasV5TOps", "true",
 117                                    "Support ARM v5T instructions",
 118                                    [HasV4TOps]>;
 119 def HasV5TEOps  : SubtargetFeature<"v5te", "HasV5TEOps", "true",
 120                              "Support ARM v5TE, v5TEj, and v5TExp instructions",
 121                                    [HasV5TOps]>;
 122 def HasV6Ops    : SubtargetFeature<"v6", "HasV6Ops", "true",
 123                                    "Support ARM v6 instructions",
 124                                    [HasV5TEOps]>;
 125 def HasV6T2Ops  : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
 126                                    "Support ARM v6t2 instructions",
 127                                    [HasV6Ops, FeatureThumb2]>;
 128 def HasV7Ops    : SubtargetFeature<"v7", "HasV7Ops", "true",
 129                                    "Support ARM v7 instructions",
 130                                    [HasV6T2Ops]>;
 131
 132 //===----------------------------------------------------------------------===//
 133 // ARM Processors supported.
 134 //
 135
 136 include "ARMSchedule.td"
 137
 138 // ARM processor families.
 139 def ProcA5      : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
 140                                    "Cortex-A5 ARM processors",
 141                                    [FeatureSlowFPBrcc, FeatureNEONForFP,
 142                                     FeatureHasSlowFPVMLx, FeatureVMLxForwarding,
 143                                     FeatureT2XtPk]>;
 144 def ProcA8      : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
 145                                    "Cortex-A8 ARM processors",
 146                                    [FeatureSlowFPBrcc, FeatureNEONForFP,
 147                                     FeatureHasSlowFPVMLx, FeatureVMLxForwarding,
 148                                     FeatureT2XtPk]>;
 149 def ProcA9      : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
 150                                    "Cortex-A9 ARM processors",
 151                                    [FeatureVMLxForwarding,
 152                                     FeatureT2XtPk, FeatureFP16,
 153                                     FeatureAvoidPartialCPSR]>;
 154 def ProcSwift   : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
 155                                    "Swift ARM processors",
 156                                    [FeatureNEONForFP, FeatureT2XtPk,
 157                                     FeatureVFP4, FeatureMP, FeatureHWDiv,
 158                                     FeatureHWDivARM, FeatureAvoidPartialCPSR,
 159                                     FeatureAvoidMOVsShOp,
 160                                     FeatureHasSlowFPVMLx]>;
 161
 162 // FIXME: It has not been determined if A15 has these features.
 163 def ProcA15      : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
 164                                    "Cortex-A15 ARM processors",
 165                                    [FeatureT2XtPk, FeatureFP16,
 166                                     FeatureAvoidPartialCPSR]>;
 167
 168 class ProcNoItin<string Name, list<SubtargetFeature> Features>
 169  : Processor<Name, NoItineraries, Features>;
 170
 171 // V4 Processors.
 172 def : ProcNoItin<"generic",         []>;
 173 def : ProcNoItin<"arm8",            []>;
 174 def : ProcNoItin<"arm810",          []>;
 175 def : ProcNoItin<"strongarm",       []>;
 176 def : ProcNoItin<"strongarm110",    []>;
 177 def : ProcNoItin<"strongarm1100",   []>;
 178 def : ProcNoItin<"strongarm1110",   []>;
 179
 180 // V4T Processors.
 181 def : ProcNoItin<"arm7tdmi",        [HasV4TOps]>;
 182 def : ProcNoItin<"arm7tdmi-s",      [HasV4TOps]>;
 183 def : ProcNoItin<"arm710t",         [HasV4TOps]>;
 184 def : ProcNoItin<"arm720t",         [HasV4TOps]>;
 185 def : ProcNoItin<"arm9",            [HasV4TOps]>;
 186 def : ProcNoItin<"arm9tdmi",        [HasV4TOps]>;
 187 def : ProcNoItin<"arm920",          [HasV4TOps]>;
 188 def : ProcNoItin<"arm920t",         [HasV4TOps]>;
 189 def : ProcNoItin<"arm922t",         [HasV4TOps]>;
 190 def : ProcNoItin<"arm940t",         [HasV4TOps]>;
 191 def : ProcNoItin<"ep9312",          [HasV4TOps]>;
 192
 193 // V5T Processors.
 194 def : ProcNoItin<"arm10tdmi",       [HasV5TOps]>;
 195 def : ProcNoItin<"arm1020t",        [HasV5TOps]>;
 196
 197 // V5TE Processors.
 198 def : ProcNoItin<"arm9e",           [HasV5TEOps]>;
 199 def : ProcNoItin<"arm926ej-s",      [HasV5TEOps]>;
 200 def : ProcNoItin<"arm946e-s",       [HasV5TEOps]>;
 201 def : ProcNoItin<"arm966e-s",       [HasV5TEOps]>;
 202 def : ProcNoItin<"arm968e-s",       [HasV5TEOps]>;
 203 def : ProcNoItin<"arm10e",          [HasV5TEOps]>;
 204 def : ProcNoItin<"arm1020e",        [HasV5TEOps]>;
 205 def : ProcNoItin<"arm1022e",        [HasV5TEOps]>;
 206 def : ProcNoItin<"xscale",          [HasV5TEOps]>;
 207 def : ProcNoItin<"iwmmxt",          [HasV5TEOps]>;
 208
 209 // V6 Processors.
 210 def : Processor<"arm1136j-s",       ARMV6Itineraries, [HasV6Ops]>;
 211 def : Processor<"arm1136jf-s",      ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
 212                                                        FeatureHasSlowFPVMLx]>;
 213 def : Processor<"arm1176jz-s",      ARMV6Itineraries, [HasV6Ops]>;
 214 def : Processor<"arm1176jzf-s",     ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
 215                                                        FeatureHasSlowFPVMLx]>;
 216 def : Processor<"mpcorenovfp",      ARMV6Itineraries, [HasV6Ops]>;
 217 def : Processor<"mpcore",           ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
 218                                                        FeatureHasSlowFPVMLx]>;
 219
 220 // V6M Processors.
 221 def : Processor<"cortex-m0",        ARMV6Itineraries, [HasV6Ops, FeatureNoARM,
 222                                                        FeatureDB, FeatureMClass]>;
 223
 224 // V6T2 Processors.
 225 def : Processor<"arm1156t2-s",      ARMV6Itineraries, [HasV6T2Ops,
 226                                                        FeatureDSPThumb2]>;
 227 def : Processor<"arm1156t2f-s",     ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
 228                                                        FeatureHasSlowFPVMLx,
 229                                                        FeatureDSPThumb2]>;
 230
 231 // V7a Processors.
 232 // FIXME: A5 has currently the same Schedule model as A8
 233 def : ProcessorModel<"cortex-a5",   CortexA8Model,
 234                                     [ProcA5, HasV7Ops, FeatureNEON, FeatureDB,
 235                                      FeatureVFP4, FeatureDSPThumb2,
 236                                      FeatureHasRAS]>;
 237 def : ProcessorModel<"cortex-a8",   CortexA8Model,
 238                                     [ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
 239                                      FeatureDSPThumb2, FeatureHasRAS]>;
 240 def : ProcessorModel<"cortex-a9",   CortexA9Model,
 241                                     [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
 242                                      FeatureDSPThumb2, FeatureHasRAS]>;
 243 def : ProcessorModel<"cortex-a9-mp", CortexA9Model,
 244                                     [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
 245                                      FeatureDSPThumb2, FeatureMP,
 246                                      FeatureHasRAS]>;
 247 // FIXME: A15 has currently the same ProcessorModel as A9.
 248 def : ProcessorModel<"cortex-a15",   CortexA9Model,
 249                                     [ProcA15, HasV7Ops, FeatureNEON, FeatureDB,
 250                                      FeatureDSPThumb2, FeatureHasRAS]>;
 251
 252 // V7M Processors.
 253 def : ProcNoItin<"cortex-m3",       [HasV7Ops,
 254                                      FeatureThumb2, FeatureNoARM, FeatureDB,
 255                                      FeatureHWDiv, FeatureMClass]>;
 256
 257 // V7EM Processors.
 258 def : ProcNoItin<"cortex-m4",       [HasV7Ops,
 259                                      FeatureThumb2, FeatureNoARM, FeatureDB,
 260                                      FeatureHWDiv, FeatureDSPThumb2,
 261                                      FeatureT2XtPk, FeatureVFP4,
 262                                      FeatureVFPOnlySP, FeatureMClass]>;
 263
 264 // Swift uArch Processors.
 265 def : ProcessorModel<"swift",       SwiftModel,
 266                                     [ProcSwift, HasV7Ops, FeatureNEON,
 267                                      FeatureDB, FeatureDSPThumb2,
 268                                      FeatureHasRAS]>;
 269
 270 //===----------------------------------------------------------------------===//
 271 // Register File Description
 272 //===----------------------------------------------------------------------===//
 273
 274 include "ARMRegisterInfo.td"
 275
 276 include "ARMCallingConv.td"
 277
 278 //===----------------------------------------------------------------------===//
 279 // Instruction Descriptions
 280 //===----------------------------------------------------------------------===//
 281
 282 include "ARMInstrInfo.td"
 283
 284 def ARMInstrInfo : InstrInfo;
 285
 286
 287 //===----------------------------------------------------------------------===//
 288 // Assembly printer
 289 //===----------------------------------------------------------------------===//
 290 // ARM Uses the MC printer for asm output, so make sure the TableGen
 291 // AsmWriter bits get associated with the correct class.
 292 def ARMAsmWriter : AsmWriter {
 293   string AsmWriterClassName  = "InstPrinter";
 294   bit isMCAsmWriter = 1;
 295 }
 296
 297 //===----------------------------------------------------------------------===//
 298 // Declare the target which we are implementing
 299 //===----------------------------------------------------------------------===//
 300
 301 def ARM : Target {
 302   // Pull in Instruction Info:
 303   let InstructionSet = ARMInstrInfo;
 304
 305   let AssemblyWriters = [ARMAsmWriter];
 306 }