lib/Target/ARM/ARM.td

   1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Target-independent interfaces which we are implementing
  15 //===----------------------------------------------------------------------===//
  16
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // ARM Helper classes.
  21 //
  22
  23 class ProcNoItin<string Name, list<SubtargetFeature> Features>
  24  : Processor<Name, NoItineraries, Features>;
  25
  26 class Architecture<string fname, string aname, list<SubtargetFeature> features >
  27   : SubtargetFeature<fname, "ARMArch", aname,
  28                      !strconcat(aname, " architecture"), features>;
  29
  30 //===----------------------------------------------------------------------===//
  31 // ARM Subtarget state.
  32 //
  33
  34 def ModeThumb  : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
  35                                   "Thumb mode">;
  36
  37 def ModeSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
  38                                      "Use software floating point features.">;
  39
  40 //===----------------------------------------------------------------------===//
  41 // ARM Subtarget features.
  42 //
  43
  44 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
  45                                    "Enable VFP2 instructions">;
  46 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
  47                                    "Enable VFP3 instructions",
  48                                    [FeatureVFP2]>;
  49 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
  50                                    "Enable NEON instructions",
  51                                    [FeatureVFP3]>;
  52 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
  53                                      "Enable Thumb2 instructions">;
  54 def FeatureNoARM  : SubtargetFeature<"noarm", "NoARM", "true",
  55                                      "Does not support ARM mode execution",
  56                                      [ModeThumb]>;
  57 def FeatureFP16   : SubtargetFeature<"fp16", "HasFP16", "true",
  58                                      "Enable half-precision floating point">;
  59 def FeatureVFP4   : SubtargetFeature<"vfp4", "HasVFPv4", "true",
  60                                      "Enable VFP4 instructions",
  61                                      [FeatureVFP3, FeatureFP16]>;
  62 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8",
  63                                    "true", "Enable ARMv8 FP",
  64                                    [FeatureVFP4]>;
  65 def FeatureD16    : SubtargetFeature<"d16", "HasD16", "true",
  66                                      "Restrict FP to 16 double registers">;
  67 def FeatureHWDiv  : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
  68                                      "Enable divide instructions">;
  69 def FeatureHWDivARM  : SubtargetFeature<"hwdiv-arm",
  70                                         "HasHardwareDivideInARM", "true",
  71                                       "Enable divide instructions in ARM mode">;
  72 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
  73                                  "Enable Thumb2 extract and pack instructions">;
  74 def FeatureDB     : SubtargetFeature<"db", "HasDataBarrier", "true",
  75                                    "Has data barrier (dmb / dsb) instructions">;
  76 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
  77                                          "FP compare + branch is slow">;
  78 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
  79                           "Floating point unit supports single precision only">;
  80 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
  81                            "Enable support for Performance Monitor extensions">;
  82 def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
  83                           "Enable support for TrustZone security extensions">;
  84 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
  85                           "Enable support for Cryptography extensions",
  86                           [FeatureNEON]>;
  87 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
  88                           "Enable support for CRC instructions">;
  89
  90 // Cyclone has preferred instructions for zeroing VFP registers, which can
  91 // execute in 0 cycles.
  92 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
  93                                         "Has zero-cycle zeroing instructions">;
  94
  95 // Some processors have FP multiply-accumulate instructions that don't
  96 // play nicely with other VFP / NEON instructions, and it's generally better
  97 // to just not use them.
  98 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
  99                                          "Disable VFP / NEON MAC instructions">;
 100
 101 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
 102 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
 103                                        "HasVMLxForwarding", "true",
 104                                        "Has multiplier accumulator forwarding">;
 105
 106 // Some processors benefit from using NEON instructions for scalar
 107 // single-precision FP operations.
 108 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
 109                                         "true",
 110                                         "Use NEON for single precision FP">;
 111
 112 // Disable 32-bit to 16-bit narrowing for experimentation.
 113 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
 114                                              "Prefer 32-bit Thumb instrs">;
 115
 116 /// Some instructions update CPSR partially, which can add false dependency for
 117 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
 118 /// mapped to a separate physical register. Avoid partial CPSR update for these
 119 /// processors.
 120 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
 121                                                "AvoidCPSRPartialUpdate", "true",
 122                                  "Avoid CPSR partial update for OOO execution">;
 123
 124 def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
 125                                             "AvoidMOVsShifterOperand", "true",
 126                                 "Avoid movs instructions with shifter operand">;
 127
 128 // Some processors perform return stack prediction. CodeGen should avoid issue
 129 // "normal" call instructions to callees which do not return.
 130 def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true",
 131                                      "Has return address stack">;
 132
 133 /// DSP extension.
 134 def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true",
 135                               "Supports DSP instructions in ARM and/or Thumb2">;
 136
 137 // Multiprocessing extension.
 138 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
 139                                  "Supports Multiprocessing extension">;
 140
 141 // Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
 142 def FeatureVirtualization : SubtargetFeature<"virtualization",
 143                                  "HasVirtualization", "true",
 144                                  "Supports Virtualization extension",
 145                                  [FeatureHWDiv, FeatureHWDivARM]>;
 146
 147 // M-series ISA
 148 def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
 149                                      "Is microcontroller profile ('M' series)">;
 150
 151 // R-series ISA
 152 def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
 153                                      "Is realtime profile ('R' series)">;
 154
 155 // A-series ISA
 156 def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
 157                                      "Is application profile ('A' series)">;
 158
 159 // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
 160 // See ARMInstrInfo.td for details.
 161 def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
 162                                        "NaCl trap">;
 163
 164 def FeatureStrictAlign : SubtargetFeature<"strict-align",
 165                                           "StrictAlign", "true",
 166                                           "Disallow all unaligned memory "
 167                                           "access">;
 168
 169 def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true",
 170                                         "Generate calls via indirect call "
 171                                         "instructions">;
 172
 173 def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
 174                                         "Reserve R9, making it unavailable as "
 175                                         "GPR">;
 176
 177 def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true",
 178                                      "Don't use movt/movw pairs for 32-bit "
 179                                      "imms">;
 180
 181
 182 //===----------------------------------------------------------------------===//
 183 // ARM ISAa.
 184 //
 185
 186 def HasV4TOps   : SubtargetFeature<"v4t", "HasV4TOps", "true",
 187                                    "Support ARM v4T instructions">;
 188 def HasV5TOps   : SubtargetFeature<"v5t", "HasV5TOps", "true",
 189                                    "Support ARM v5T instructions",
 190                                    [HasV4TOps]>;
 191 def HasV5TEOps  : SubtargetFeature<"v5te", "HasV5TEOps", "true",
 192                              "Support ARM v5TE, v5TEj, and v5TExp instructions",
 193                                    [HasV5TOps]>;
 194 def HasV6Ops    : SubtargetFeature<"v6", "HasV6Ops", "true",
 195                                    "Support ARM v6 instructions",
 196                                    [HasV5TEOps]>;
 197 def HasV6MOps   : SubtargetFeature<"v6m", "HasV6MOps", "true",
 198                                    "Support ARM v6M instructions",
 199                                    [HasV6Ops]>;
 200 def HasV6KOps   : SubtargetFeature<"v6k", "HasV6KOps", "true",
 201                                    "Support ARM v6k instructions",
 202                                    [HasV6Ops]>;
 203 def HasV6T2Ops  : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
 204                                    "Support ARM v6t2 instructions",
 205                                    [HasV6MOps, HasV6KOps, FeatureThumb2]>;
 206 def HasV7Ops    : SubtargetFeature<"v7", "HasV7Ops", "true",
 207                                    "Support ARM v7 instructions",
 208                                    [HasV6T2Ops, FeaturePerfMon]>;
 209 def HasV8Ops    : SubtargetFeature<"v8", "HasV8Ops", "true",
 210                                    "Support ARM v8 instructions",
 211                                    [HasV7Ops]>;
 212 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
 213                                    "Support ARM v8.1a instructions",
 214                                    [HasV8Ops]>;
 215
 216
 217 //===----------------------------------------------------------------------===//
 218 // ARM Processor subtarget features.
 219 //
 220
 221 def ProcA5      : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
 222                                    "Cortex-A5 ARM processors", []>;
 223 def ProcA7      : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7",
 224                                    "Cortex-A7 ARM processors", []>;
 225 def ProcA8      : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
 226                                    "Cortex-A8 ARM processors", []>;
 227 def ProcA9      : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
 228                                    "Cortex-A9 ARM processors", []>;
 229 def ProcA12     : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12",
 230                                    "Cortex-A12 ARM processors", []>;
 231 def ProcA15     : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
 232                                    "Cortex-A15 ARM processors", []>;
 233 def ProcA17     : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17",
 234                                    "Cortex-A17 ARM processors", []>;
 235 def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
 236                                    "Cortex-A53 ARM processors", []>;
 237 def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
 238                                    "Cortex-A57 ARM processors", []>;
 239 def ProcA72     : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
 240                                    "Cortex-A72 ARM processors", []>;
 241
 242 def ProcKrait   : SubtargetFeature<"krait", "ARMProcFamily", "Krait",
 243                                    "Qualcomm ARM processors", []>;
 244 def ProcSwift   : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
 245                                    "Swift ARM processors", []>;
 246
 247
 248 def ProcR4      : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4",
 249                                     "Cortex-R4 ARM processors", []>;
 250 def ProcR5      : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
 251                                    "Cortex-R5 ARM processors", []>;
 252 def ProcR7      : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7",
 253                                    "Cortex-R7 ARM processors", []>;
 254
 255
 256 //===----------------------------------------------------------------------===//
 257 // ARM schedules.
 258 //
 259
 260 include "ARMSchedule.td"
 261
 262
 263 //===----------------------------------------------------------------------===//
 264 // ARM architectures
 265 //
 266
 267 def ARMv2     : Architecture<"armv2",     "ARMv2",    []>;
 268
 269 def ARMv2a    : Architecture<"armv2a",    "ARMv2a",   []>;
 270
 271 def ARMv3     : Architecture<"armv3",     "ARMv3",    []>;
 272
 273 def ARMv3m    : Architecture<"armv3m",    "ARMv3m",   []>;
 274
 275 def ARMv4     : Architecture<"armv4",     "ARMv4",    []>;
 276
 277 def ARMv4t    : Architecture<"armv4t",    "ARMv4t",   [HasV4TOps]>;
 278
 279 def ARMv5t    : Architecture<"armv5t",    "ARMv5t",   [HasV5TOps]>;
 280
 281 def ARMv5te   : Architecture<"armv5te",   "ARMv5te",  [HasV5TEOps]>;
 282
 283 def ARMv5tej  : Architecture<"armv5tej",  "ARMv5tej", [HasV5TEOps]>;
 284
 285 def ARMv6     : Architecture<"armv6",     "ARMv6",    [HasV6Ops]>;
 286
 287 def ARMv6t2   : Architecture<"armv6t2",   "ARMv6t2",  [HasV6T2Ops,
 288                                                        FeatureDSP]>;
 289
 290 def ARMv6k    : Architecture<"armv6k",    "ARMv6k",   [HasV6KOps]>;
 291
 292 def ARMv6kz   : Architecture<"armv6kz",   "ARMv6kz",  [HasV6KOps,
 293                                                        FeatureTrustZone]>;
 294
 295 def ARMv6m    : Architecture<"armv6-m",   "ARMv6m",   [HasV6MOps,
 296                                                        FeatureNoARM,
 297                                                        FeatureDB,
 298                                                        FeatureMClass]>;
 299
 300 def ARMv6sm   : Architecture<"armv6s-m",  "ARMv6sm",  [HasV6MOps,
 301                                                        FeatureNoARM,
 302                                                        FeatureDB,
 303                                                        FeatureMClass]>;
 304
 305 def ARMv7a    : Architecture<"armv7-a",   "ARMv7a",   [HasV7Ops,
 306                                                        FeatureNEON,
 307                                                        FeatureDB,
 308                                                        FeatureDSP,
 309                                                        FeatureAClass]>;
 310
 311 def ARMv7r    : Architecture<"armv7-r",   "ARMv7r",   [HasV7Ops,
 312                                                        FeatureDB,
 313                                                        FeatureDSP,
 314                                                        FeatureHWDiv,
 315                                                        FeatureRClass]>;
 316
 317 def ARMv7m    : Architecture<"armv7-m",   "ARMv7m",   [HasV7Ops,
 318                                                        FeatureThumb2,
 319                                                        FeatureNoARM,
 320                                                        FeatureDB,
 321                                                        FeatureHWDiv,
 322                                                        FeatureMClass]>;
 323
 324 def ARMv7em   : Architecture<"armv7e-m",  "ARMv7em",  [HasV7Ops,
 325                                                        FeatureThumb2,
 326                                                        FeatureNoARM,
 327                                                        FeatureDB,
 328                                                        FeatureHWDiv,
 329                                                        FeatureMClass,
 330                                                        FeatureDSP,
 331                                                        FeatureT2XtPk]>;
 332
 333 def ARMv8a    : Architecture<"armv8-a",   "ARMv8a",   [HasV8Ops,
 334                                                        FeatureAClass,
 335                                                        FeatureDB,
 336                                                        FeatureFPARMv8,
 337                                                        FeatureNEON,
 338                                                        FeatureDSP,
 339                                                        FeatureTrustZone,
 340                                                        FeatureMP,
 341                                                        FeatureVirtualization,
 342                                                        FeatureCrypto,
 343                                                        FeatureCRC]>;
 344
 345 def ARMv81a   : Architecture<"armv8.1-a", "ARMv81a",  [HasV8_1aOps,
 346                                                        FeatureAClass,
 347                                                        FeatureDB,
 348                                                        FeatureFPARMv8,
 349                                                        FeatureNEON,
 350                                                        FeatureDSP,
 351                                                        FeatureTrustZone,
 352                                                        FeatureMP,
 353                                                        FeatureVirtualization,
 354                                                        FeatureCrypto,
 355                                                        FeatureCRC]>;
 356
 357 // Aliases
 358 def IWMMXT   : Architecture<"iwmmxt",      "ARMv5te",  [ARMv5te]>;
 359 def IWMMXT2  : Architecture<"iwmmxt2",     "ARMv5te",  [ARMv5te]>;
 360 def XScale   : Architecture<"xscale",      "ARMv5te",  [ARMv5te]>;
 361 def ARMv6j   : Architecture<"armv6j",      "ARMv7a",   [ARMv6]>;
 362 def ARMv7k   : Architecture<"armv7k",      "ARMv7a",   [ARMv7a]>;
 363 def ARMv7s   : Architecture<"armv7s",      "ARMv7a",   [ARMv7a]>;
 364
 365
 366 //===----------------------------------------------------------------------===//
 367 // ARM processors
 368 //
 369
 370 // Dummy CPU, used to target architectures
 371 def : ProcNoItin<"generic",                             []>;
 372
 373 def : ProcNoItin<"arm8",                                [ARMv4]>;
 374 def : ProcNoItin<"arm810",                              [ARMv4]>;
 375 def : ProcNoItin<"strongarm",                           [ARMv4]>;
 376 def : ProcNoItin<"strongarm110",                        [ARMv4]>;
 377 def : ProcNoItin<"strongarm1100",                       [ARMv4]>;
 378 def : ProcNoItin<"strongarm1110",                       [ARMv4]>;
 379
 380 def : ProcNoItin<"arm7tdmi",                            [ARMv4t]>;
 381 def : ProcNoItin<"arm7tdmi-s",                          [ARMv4t]>;
 382 def : ProcNoItin<"arm710t",                             [ARMv4t]>;
 383 def : ProcNoItin<"arm720t",                             [ARMv4t]>;
 384 def : ProcNoItin<"arm9",                                [ARMv4t]>;
 385 def : ProcNoItin<"arm9tdmi",                            [ARMv4t]>;
 386 def : ProcNoItin<"arm920",                              [ARMv4t]>;
 387 def : ProcNoItin<"arm920t",                             [ARMv4t]>;
 388 def : ProcNoItin<"arm922t",                             [ARMv4t]>;
 389 def : ProcNoItin<"arm940t",                             [ARMv4t]>;
 390 def : ProcNoItin<"ep9312",                              [ARMv4t]>;
 391
 392 def : ProcNoItin<"arm10tdmi",                           [ARMv5t]>;
 393 def : ProcNoItin<"arm1020t",                            [ARMv5t]>;
 394
 395 def : ProcNoItin<"arm9e",                               [ARMv5te]>;
 396 def : ProcNoItin<"arm926ej-s",                          [ARMv5te]>;
 397 def : ProcNoItin<"arm946e-s",                           [ARMv5te]>;
 398 def : ProcNoItin<"arm966e-s",                           [ARMv5te]>;
 399 def : ProcNoItin<"arm968e-s",                           [ARMv5te]>;
 400 def : ProcNoItin<"arm10e",                              [ARMv5te]>;
 401 def : ProcNoItin<"arm1020e",                            [ARMv5te]>;
 402 def : ProcNoItin<"arm1022e",                            [ARMv5te]>;
 403 def : ProcNoItin<"xscale",                              [ARMv5te]>;
 404 def : ProcNoItin<"iwmmxt",                              [ARMv5te]>;
 405
 406 def : Processor<"arm1136j-s",       ARMV6Itineraries,   [ARMv6]>;
 407 def : Processor<"arm1136jf-s",      ARMV6Itineraries,   [ARMv6,
 408                                                          FeatureVFP2,
 409                                                          FeatureHasSlowFPVMLx]>;
 410
 411 def : Processor<"cortex-m0",        ARMV6Itineraries,   [ARMv6m]>;
 412 def : Processor<"cortex-m0plus",    ARMV6Itineraries,   [ARMv6m]>;
 413 def : Processor<"cortex-m1",        ARMV6Itineraries,   [ARMv6m]>;
 414 def : Processor<"sc000",            ARMV6Itineraries,   [ARMv6m]>;
 415
 416 def : Processor<"arm1176jz-s",      ARMV6Itineraries,   [ARMv6kz]>;
 417 def : Processor<"arm1176jzf-s",     ARMV6Itineraries,   [ARMv6kz,
 418                                                          FeatureVFP2,
 419                                                          FeatureHasSlowFPVMLx]>;
 420
 421 def : Processor<"mpcorenovfp",      ARMV6Itineraries,   [ARMv6k]>;
 422 def : Processor<"mpcore",           ARMV6Itineraries,   [ARMv6k,
 423                                                          FeatureVFP2,
 424                                                          FeatureHasSlowFPVMLx]>;
 425
 426 def : Processor<"arm1156t2-s",      ARMV6Itineraries,   [ARMv6t2]>;
 427 def : Processor<"arm1156t2f-s",     ARMV6Itineraries,   [ARMv6t2,
 428                                                          FeatureVFP2,
 429                                                          FeatureHasSlowFPVMLx]>;
 430
 431 // FIXME: A5 has currently the same Schedule model as A8
 432 def : ProcessorModel<"cortex-a5",   CortexA8Model,      [ARMv7a, ProcA5,
 433                                                          FeatureHasRAS,
 434                                                          FeatureTrustZone,
 435                                                          FeatureSlowFPBrcc,
 436                                                          FeatureHasSlowFPVMLx,
 437                                                          FeatureVMLxForwarding,
 438                                                          FeatureT2XtPk,
 439                                                          FeatureMP,
 440                                                          FeatureVFP4]>;
 441
 442 def : ProcessorModel<"cortex-a7",   CortexA8Model,      [ARMv7a, ProcA7,
 443                                                          FeatureHasRAS,
 444                                                          FeatureTrustZone,
 445                                                          FeatureSlowFPBrcc,
 446                                                          FeatureHasSlowFPVMLx,
 447                                                          FeatureVMLxForwarding,
 448                                                          FeatureT2XtPk,
 449                                                          FeatureMP,
 450                                                          FeatureVFP4,
 451                                                          FeatureHWDiv,
 452                                                          FeatureHWDivARM,
 453                                                          FeatureVirtualization]>;
 454
 455 def : ProcessorModel<"cortex-a8",   CortexA8Model,      [ARMv7a, ProcA8,
 456                                                          FeatureHasRAS,
 457                                                          FeatureTrustZone,
 458                                                          FeatureSlowFPBrcc,
 459                                                          FeatureHasSlowFPVMLx,
 460                                                          FeatureVMLxForwarding,
 461                                                          FeatureT2XtPk]>;
 462
 463 def : ProcessorModel<"cortex-a9",   CortexA9Model,      [ARMv7a, ProcA9,
 464                                                          FeatureHasRAS,
 465                                                          FeatureTrustZone,
 466                                                          FeatureVMLxForwarding,
 467                                                          FeatureT2XtPk,
 468                                                          FeatureFP16,
 469                                                          FeatureAvoidPartialCPSR,
 470                                                          FeatureMP]>;
 471
 472 // FIXME: A12 has currently the same Schedule model as A9
 473 def : ProcessorModel<"cortex-a12",  CortexA9Model,      [ARMv7a, ProcA12,
 474                                                          FeatureHasRAS,
 475                                                          FeatureTrustZone,
 476                                                          FeatureVMLxForwarding,
 477                                                          FeatureT2XtPk,
 478                                                          FeatureVFP4,
 479                                                          FeatureHWDiv,
 480                                                          FeatureHWDivARM,
 481                                                          FeatureAvoidPartialCPSR,
 482                                                          FeatureVirtualization,
 483                                                          FeatureMP]>;
 484
 485 // FIXME: A15 has currently the same Schedule model as A9.
 486 def : ProcessorModel<"cortex-a15",  CortexA9Model,      [ARMv7a, ProcA15,
 487                                                          FeatureHasRAS,
 488                                                          FeatureTrustZone,
 489                                                          FeatureT2XtPk,
 490                                                          FeatureVFP4,
 491                                                          FeatureMP,
 492                                                          FeatureHWDiv,
 493                                                          FeatureHWDivARM,
 494                                                          FeatureAvoidPartialCPSR,
 495                                                          FeatureVirtualization]>;
 496
 497 // FIXME: A17 has currently the same Schedule model as A9
 498 def : ProcessorModel<"cortex-a17",  CortexA9Model,      [ARMv7a, ProcA17,
 499                                                          FeatureHasRAS,
 500                                                          FeatureTrustZone,
 501                                                          FeatureMP,
 502                                                          FeatureVMLxForwarding,
 503                                                          FeatureT2XtPk,
 504                                                          FeatureVFP4,
 505                                                          FeatureHWDiv,
 506                                                          FeatureHWDivARM,
 507                                                          FeatureAvoidPartialCPSR,
 508                                                          FeatureVirtualization]>;
 509
 510 // FIXME: krait has currently the same Schedule model as A9
 511 // FIXME: krait has currently the same features as A9 plus VFP4 and hardware
 512 //        division features.
 513 def : ProcessorModel<"krait",       CortexA9Model,      [ARMv7a, ProcKrait,
 514                                                          FeatureHasRAS,
 515                                                          FeatureVMLxForwarding,
 516                                                          FeatureT2XtPk,
 517                                                          FeatureFP16,
 518                                                          FeatureAvoidPartialCPSR,
 519                                                          FeatureVFP4,
 520                                                          FeatureHWDiv,
 521                                                          FeatureHWDivARM]>;
 522
 523 def : ProcessorModel<"swift",       SwiftModel,         [ARMv7a, ProcSwift,
 524                                                          FeatureHasRAS,
 525                                                          FeatureNEONForFP,
 526                                                          FeatureT2XtPk,
 527                                                          FeatureVFP4,
 528                                                          FeatureMP,
 529                                                          FeatureHWDiv,
 530                                                          FeatureHWDivARM,
 531                                                          FeatureAvoidPartialCPSR,
 532                                                          FeatureAvoidMOVsShOp,
 533                                                          FeatureHasSlowFPVMLx]>;
 534
 535 // FIXME: R4 has currently the same ProcessorModel as A8.
 536 def : ProcessorModel<"cortex-r4",   CortexA8Model,      [ARMv7r, ProcR4,
 537                                                          FeatureHasRAS,
 538                                                          FeatureAvoidPartialCPSR,
 539                                                          FeatureT2XtPk]>;
 540
 541 // FIXME: R4F has currently the same ProcessorModel as A8.
 542 def : ProcessorModel<"cortex-r4f",  CortexA8Model,      [ARMv7r, ProcR4,
 543                                                          FeatureHasRAS,
 544                                                          FeatureSlowFPBrcc,
 545                                                          FeatureHasSlowFPVMLx,
 546                                                          FeatureVFP3,
 547                                                          FeatureD16,
 548                                                          FeatureAvoidPartialCPSR,
 549                                                          FeatureT2XtPk]>;
 550
 551 // FIXME: R5 has currently the same ProcessorModel as A8.
 552 def : ProcessorModel<"cortex-r5",   CortexA8Model,      [ARMv7r, ProcR5,
 553                                                          FeatureHasRAS,
 554                                                          FeatureVFP3,
 555                                                          FeatureD16,
 556                                                          FeatureSlowFPBrcc,
 557                                                          FeatureHWDivARM,
 558                                                          FeatureHasSlowFPVMLx,
 559                                                          FeatureAvoidPartialCPSR,
 560                                                          FeatureT2XtPk]>;
 561
 562 // FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5.
 563 def : ProcessorModel<"cortex-r7",   CortexA8Model,      [ARMv7r, ProcR7,
 564                                                          FeatureHasRAS,
 565                                                          FeatureVFP3,
 566                                                          FeatureVFPOnlySP,
 567                                                          FeatureD16,
 568                                                          FeatureMP,
 569                                                          FeatureSlowFPBrcc,
 570                                                          FeatureHWDivARM,
 571                                                          FeatureHasSlowFPVMLx,
 572                                                          FeatureAvoidPartialCPSR,
 573                                                          FeatureT2XtPk]>;
 574
 575 def : ProcNoItin<"cortex-m3",                           [ARMv7m]>;
 576 def : ProcNoItin<"sc300",                               [ARMv7m]>;
 577
 578 def : ProcNoItin<"cortex-m4",                           [ARMv7em,
 579                                                          FeatureVFP4,
 580                                                          FeatureVFPOnlySP,
 581                                                          FeatureD16]>;
 582
 583 def : ProcNoItin<"cortex-m7",                           [ARMv7em,
 584                                                          FeatureFPARMv8,
 585                                                          FeatureD16]>;
 586
 587
 588 def : ProcNoItin<"cortex-a53",                          [ARMv8a, ProcA53,
 589                                                          FeatureHWDiv,
 590                                                          FeatureHWDivARM,
 591                                                          FeatureT2XtPk,
 592                                                          FeatureCrypto,
 593                                                          FeatureCRC]>;
 594
 595 def : ProcNoItin<"cortex-a57",                          [ARMv8a, ProcA57,
 596                                                          FeatureHWDiv,
 597                                                          FeatureHWDivARM,
 598                                                          FeatureT2XtPk,
 599                                                          FeatureCrypto,
 600                                                          FeatureCRC]>;
 601
 602 def : ProcNoItin<"cortex-a72",                          [ARMv8a, ProcA72,
 603                                                          FeatureHWDiv,
 604                                                          FeatureHWDivARM,
 605                                                          FeatureT2XtPk,
 606                                                          FeatureCrypto,
 607                                                          FeatureCRC]>;
 608
 609 // Cyclone is very similar to swift
 610 def : ProcessorModel<"cyclone",     SwiftModel,         [ARMv8a, ProcSwift,
 611                                                          FeatureHasRAS,
 612                                                          FeatureNEONForFP,
 613                                                          FeatureT2XtPk,
 614                                                          FeatureVFP4,
 615                                                          FeatureMP,
 616                                                          FeatureHWDiv,
 617                                                          FeatureHWDivARM,
 618                                                          FeatureAvoidPartialCPSR,
 619                                                          FeatureAvoidMOVsShOp,
 620                                                          FeatureHasSlowFPVMLx,
 621                                                          FeatureCrypto,
 622                                                          FeatureZCZeroing]>;
 623
 624
 625 //===----------------------------------------------------------------------===//
 626 // Register File Description
 627 //===----------------------------------------------------------------------===//
 628
 629 include "ARMRegisterInfo.td"
 630
 631 include "ARMCallingConv.td"
 632
 633 //===----------------------------------------------------------------------===//
 634 // Instruction Descriptions
 635 //===----------------------------------------------------------------------===//
 636
 637 include "ARMInstrInfo.td"
 638
 639 def ARMInstrInfo : InstrInfo;
 640
 641 //===----------------------------------------------------------------------===//
 642 // Declare the target which we are implementing
 643 //===----------------------------------------------------------------------===//
 644
 645 def ARMAsmWriter : AsmWriter {
 646   string AsmWriterClassName  = "InstPrinter";
 647   int PassSubtarget = 1;
 648   int Variant = 0;
 649   bit isMCAsmWriter = 1;
 650 }
 651
 652 def ARMAsmParserVariant : AsmParserVariant {
 653   int Variant = 0;
 654   string Name = "ARM";
 655   string BreakCharacters = ".";
 656 }
 657
 658 def ARM : Target {
 659   // Pull in Instruction Info:
 660   let InstructionSet = ARMInstrInfo;
 661   let AssemblyWriters = [ARMAsmWriter];
 662   let AssemblyParserVariants = [ARMAsmParserVariant];
 663 }