1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // ARM Subtarget state.
23 def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
26 //===----------------------------------------------------------------------===//
27 // ARM Subtarget features.
30 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
31 "Enable VFP2 instructions">;
32 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
33 "Enable VFP3 instructions",
35 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
36 "Enable NEON instructions",
38 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
39 "Enable Thumb2 instructions">;
40 def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
41 "Does not support ARM mode execution">;
42 def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
43 "Enable half-precision floating point">;
44 def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true",
45 "Enable VFP4 instructions",
46 [FeatureVFP3, FeatureFP16]>;
47 def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true",
48 "Restrict VFP3 to 16 double registers">;
49 def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
50 "Enable divide instructions">;
51 def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm",
52 "HasHardwareDivideInARM", "true",
53 "Enable divide instructions in ARM mode">;
54 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
55 "Enable Thumb2 extract and pack instructions">;
56 def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
57 "Has data barrier (dmb / dsb) instructions">;
58 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
59 "FP compare + branch is slow">;
60 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
61 "Floating point unit supports single precision only">;
63 // Some processors have FP multiply-accumulate instructions that don't
64 // play nicely with other VFP / NEON instructions, and it's generally better
65 // to just not use them.
66 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
67 "Disable VFP / NEON MAC instructions">;
69 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
70 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
71 "HasVMLxForwarding", "true",
72 "Has multiplier accumulator forwarding">;
74 // Some processors benefit from using NEON instructions for scalar
75 // single-precision FP operations.
76 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
78 "Use NEON for single precision FP">;
80 // Disable 32-bit to 16-bit narrowing for experimentation.
81 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
82 "Prefer 32-bit Thumb instrs">;
84 /// Some instructions update CPSR partially, which can add false dependency for
85 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
86 /// mapped to a separate physical register. Avoid partial CPSR update for these
88 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
89 "AvoidCPSRPartialUpdate", "true",
90 "Avoid CPSR partial update for OOO execution">;
92 def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
93 "AvoidMOVsShifterOperand", "true",
94 "Avoid movs instructions with shifter operand">;
96 // Some processors perform return stack prediction. CodeGen should avoid issue
97 // "normal" call instructions to callees which do not return.
98 def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true",
99 "Has return address stack">;
101 /// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
102 def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
103 "Supports v7 DSP instructions in Thumb2">;
105 // Multiprocessing extension.
106 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
107 "Supports Multiprocessing extension">;
110 def FeatureMClass : SubtargetFeature<"mclass", "IsMClass", "true",
111 "Is microcontroller profile ('M' series)">;
114 def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
115 "Support ARM v4T instructions">;
116 def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true",
117 "Support ARM v5T instructions",
119 def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",
120 "Support ARM v5TE, v5TEj, and v5TExp instructions",
122 def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
123 "Support ARM v6 instructions",
125 def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
126 "Support ARM v6t2 instructions",
127 [HasV6Ops, FeatureThumb2]>;
128 def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
129 "Support ARM v7 instructions",
132 //===----------------------------------------------------------------------===//
133 // ARM Processors supported.
136 include "ARMSchedule.td"
138 // ARM processor families.
139 def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
140 "Cortex-A5 ARM processors",
141 [FeatureSlowFPBrcc, FeatureNEONForFP,
142 FeatureHasSlowFPVMLx, FeatureVMLxForwarding,
144 def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
145 "Cortex-A8 ARM processors",
146 [FeatureSlowFPBrcc, FeatureNEONForFP,
147 FeatureHasSlowFPVMLx, FeatureVMLxForwarding,
149 def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
150 "Cortex-A9 ARM processors",
151 [FeatureVMLxForwarding,
152 FeatureT2XtPk, FeatureFP16,
153 FeatureAvoidPartialCPSR]>;
154 def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
155 "Swift ARM processors",
156 [FeatureNEONForFP, FeatureT2XtPk,
157 FeatureVFP4, FeatureMP, FeatureHWDiv,
158 FeatureHWDivARM, FeatureAvoidPartialCPSR,
159 FeatureAvoidMOVsShOp,
160 FeatureHasSlowFPVMLx]>;
162 // FIXME: It has not been determined if A15 has these features.
163 def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
164 "Cortex-A15 ARM processors",
165 [FeatureT2XtPk, FeatureFP16,
166 FeatureAvoidPartialCPSR]>;
167 def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
168 "Cortex-R5 ARM processors",
169 [FeatureSlowFPBrcc, FeatureHWDivARM,
170 FeatureHasSlowFPVMLx,
171 FeatureAvoidPartialCPSR,
174 class ProcNoItin<string Name, list<SubtargetFeature> Features>
175 : Processor<Name, NoItineraries, Features>;
178 def : ProcNoItin<"generic", []>;
179 def : ProcNoItin<"arm8", []>;
180 def : ProcNoItin<"arm810", []>;
181 def : ProcNoItin<"strongarm", []>;
182 def : ProcNoItin<"strongarm110", []>;
183 def : ProcNoItin<"strongarm1100", []>;
184 def : ProcNoItin<"strongarm1110", []>;
187 def : ProcNoItin<"arm7tdmi", [HasV4TOps]>;
188 def : ProcNoItin<"arm7tdmi-s", [HasV4TOps]>;
189 def : ProcNoItin<"arm710t", [HasV4TOps]>;
190 def : ProcNoItin<"arm720t", [HasV4TOps]>;
191 def : ProcNoItin<"arm9", [HasV4TOps]>;
192 def : ProcNoItin<"arm9tdmi", [HasV4TOps]>;
193 def : ProcNoItin<"arm920", [HasV4TOps]>;
194 def : ProcNoItin<"arm920t", [HasV4TOps]>;
195 def : ProcNoItin<"arm922t", [HasV4TOps]>;
196 def : ProcNoItin<"arm940t", [HasV4TOps]>;
197 def : ProcNoItin<"ep9312", [HasV4TOps]>;
200 def : ProcNoItin<"arm10tdmi", [HasV5TOps]>;
201 def : ProcNoItin<"arm1020t", [HasV5TOps]>;
204 def : ProcNoItin<"arm9e", [HasV5TEOps]>;
205 def : ProcNoItin<"arm926ej-s", [HasV5TEOps]>;
206 def : ProcNoItin<"arm946e-s", [HasV5TEOps]>;
207 def : ProcNoItin<"arm966e-s", [HasV5TEOps]>;
208 def : ProcNoItin<"arm968e-s", [HasV5TEOps]>;
209 def : ProcNoItin<"arm10e", [HasV5TEOps]>;
210 def : ProcNoItin<"arm1020e", [HasV5TEOps]>;
211 def : ProcNoItin<"arm1022e", [HasV5TEOps]>;
212 def : ProcNoItin<"xscale", [HasV5TEOps]>;
213 def : ProcNoItin<"iwmmxt", [HasV5TEOps]>;
216 def : Processor<"arm1136j-s", ARMV6Itineraries, [HasV6Ops]>;
217 def : Processor<"arm1136jf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
218 FeatureHasSlowFPVMLx]>;
219 def : Processor<"arm1176jz-s", ARMV6Itineraries, [HasV6Ops]>;
220 def : Processor<"arm1176jzf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
221 FeatureHasSlowFPVMLx]>;
222 def : Processor<"mpcorenovfp", ARMV6Itineraries, [HasV6Ops]>;
223 def : Processor<"mpcore", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
224 FeatureHasSlowFPVMLx]>;
227 def : Processor<"cortex-m0", ARMV6Itineraries, [HasV6Ops, FeatureNoARM,
228 FeatureDB, FeatureMClass]>;
231 def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops,
233 def : Processor<"arm1156t2f-s", ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
234 FeatureHasSlowFPVMLx,
238 // FIXME: A5 has currently the same Schedule model as A8
239 def : ProcessorModel<"cortex-a5", CortexA8Model,
240 [ProcA5, HasV7Ops, FeatureNEON, FeatureDB,
241 FeatureVFP4, FeatureDSPThumb2,
243 def : ProcessorModel<"cortex-a8", CortexA8Model,
244 [ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
245 FeatureDSPThumb2, FeatureHasRAS]>;
246 def : ProcessorModel<"cortex-a9", CortexA9Model,
247 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
248 FeatureDSPThumb2, FeatureHasRAS]>;
249 def : ProcessorModel<"cortex-a9-mp", CortexA9Model,
250 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
251 FeatureDSPThumb2, FeatureMP,
253 // FIXME: A15 has currently the same ProcessorModel as A9.
254 def : ProcessorModel<"cortex-a15", CortexA9Model,
255 [ProcA15, HasV7Ops, FeatureNEON, FeatureDB,
256 FeatureDSPThumb2, FeatureHasRAS]>;
257 // FIXME: R5 has currently the same ProcessorModel as A8.
258 def : ProcessorModel<"cortex-r5", CortexA8Model,
259 [ProcR5, HasV7Ops, FeatureDB,
260 FeatureVFP3, FeatureDSPThumb2,
264 def : ProcNoItin<"cortex-m3", [HasV7Ops,
265 FeatureThumb2, FeatureNoARM, FeatureDB,
266 FeatureHWDiv, FeatureMClass]>;
269 def : ProcNoItin<"cortex-m4", [HasV7Ops,
270 FeatureThumb2, FeatureNoARM, FeatureDB,
271 FeatureHWDiv, FeatureDSPThumb2,
272 FeatureT2XtPk, FeatureVFP4,
273 FeatureVFPOnlySP, FeatureMClass]>;
275 // Swift uArch Processors.
276 def : ProcessorModel<"swift", SwiftModel,
277 [ProcSwift, HasV7Ops, FeatureNEON,
278 FeatureDB, FeatureDSPThumb2,
281 //===----------------------------------------------------------------------===//
282 // Register File Description
283 //===----------------------------------------------------------------------===//
285 include "ARMRegisterInfo.td"
287 include "ARMCallingConv.td"
289 //===----------------------------------------------------------------------===//
290 // Instruction Descriptions
291 //===----------------------------------------------------------------------===//
293 include "ARMInstrInfo.td"
295 def ARMInstrInfo : InstrInfo;
298 //===----------------------------------------------------------------------===//
300 //===----------------------------------------------------------------------===//
301 // ARM Uses the MC printer for asm output, so make sure the TableGen
302 // AsmWriter bits get associated with the correct class.
303 def ARMAsmWriter : AsmWriter {
304 string AsmWriterClassName = "InstPrinter";
305 bit isMCAsmWriter = 1;
308 //===----------------------------------------------------------------------===//
309 // Declare the target which we are implementing
310 //===----------------------------------------------------------------------===//
313 // Pull in Instruction Info:
314 let InstructionSet = ARMInstrInfo;
316 let AssemblyWriters = [ARMAsmWriter];