1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // ARM Helper classes.
23 class ProcNoItin<string Name, list<SubtargetFeature> Features>
24 : Processor<Name, NoItineraries, Features>;
26 class Architecture<string fname, string aname, list<SubtargetFeature> features >
27 : SubtargetFeature<fname, "ARMArch", aname,
28 !strconcat(aname, " architecture"), features>;
30 //===----------------------------------------------------------------------===//
31 // ARM Subtarget state.
34 def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
37 def ModeSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
38 "Use software floating point features.">;
40 //===----------------------------------------------------------------------===//
41 // ARM Subtarget features.
44 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
45 "Enable VFP2 instructions">;
46 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
47 "Enable VFP3 instructions",
49 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
50 "Enable NEON instructions",
52 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
53 "Enable Thumb2 instructions">;
54 def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
55 "Does not support ARM mode execution",
57 def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
58 "Enable half-precision floating point">;
59 def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true",
60 "Enable VFP4 instructions",
61 [FeatureVFP3, FeatureFP16]>;
62 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8",
63 "true", "Enable ARMv8 FP",
65 def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
66 "Enable full half-precision floating point",
68 def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true",
69 "Restrict FP to 16 double registers">;
70 def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
71 "Enable divide instructions">;
72 def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm",
73 "HasHardwareDivideInARM", "true",
74 "Enable divide instructions in ARM mode">;
75 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
76 "Enable Thumb2 extract and pack instructions">;
77 def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
78 "Has data barrier (dmb / dsb) instructions">;
79 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
80 "FP compare + branch is slow">;
81 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
82 "Floating point unit supports single precision only">;
83 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
84 "Enable support for Performance Monitor extensions">;
85 def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
86 "Enable support for TrustZone security extensions">;
87 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
88 "Enable support for Cryptography extensions",
90 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
91 "Enable support for CRC instructions">;
93 // Cyclone has preferred instructions for zeroing VFP registers, which can
94 // execute in 0 cycles.
95 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
96 "Has zero-cycle zeroing instructions">;
98 // Some processors have FP multiply-accumulate instructions that don't
99 // play nicely with other VFP / NEON instructions, and it's generally better
100 // to just not use them.
101 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
102 "Disable VFP / NEON MAC instructions">;
104 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
105 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
106 "HasVMLxForwarding", "true",
107 "Has multiplier accumulator forwarding">;
109 // Some processors benefit from using NEON instructions for scalar
110 // single-precision FP operations.
111 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
113 "Use NEON for single precision FP">;
115 // Disable 32-bit to 16-bit narrowing for experimentation.
116 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
117 "Prefer 32-bit Thumb instrs">;
119 /// Some instructions update CPSR partially, which can add false dependency for
120 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
121 /// mapped to a separate physical register. Avoid partial CPSR update for these
123 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
124 "AvoidCPSRPartialUpdate", "true",
125 "Avoid CPSR partial update for OOO execution">;
127 def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
128 "AvoidMOVsShifterOperand", "true",
129 "Avoid movs instructions with shifter operand">;
131 // Some processors perform return stack prediction. CodeGen should avoid issue
132 // "normal" call instructions to callees which do not return.
133 def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true",
134 "Has return address stack">;
137 def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true",
138 "Supports DSP instructions in ARM and/or Thumb2">;
140 // Multiprocessing extension.
141 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
142 "Supports Multiprocessing extension">;
144 // Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
145 def FeatureVirtualization : SubtargetFeature<"virtualization",
146 "HasVirtualization", "true",
147 "Supports Virtualization extension",
148 [FeatureHWDiv, FeatureHWDivARM]>;
151 def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
152 "Is microcontroller profile ('M' series)">;
155 def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
156 "Is realtime profile ('R' series)">;
159 def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
160 "Is application profile ('A' series)">;
162 // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
163 // See ARMInstrInfo.td for details.
164 def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
167 def FeatureStrictAlign : SubtargetFeature<"strict-align",
168 "StrictAlign", "true",
169 "Disallow all unaligned memory "
172 def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true",
173 "Generate calls via indirect call "
176 def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
177 "Reserve R9, making it unavailable as "
180 def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true",
181 "Don't use movt/movw pairs for 32-bit "
185 //===----------------------------------------------------------------------===//
189 def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
190 "Support ARM v4T instructions">;
191 def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true",
192 "Support ARM v5T instructions",
194 def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",
195 "Support ARM v5TE, v5TEj, and v5TExp instructions",
197 def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
198 "Support ARM v6 instructions",
200 def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true",
201 "Support ARM v6M instructions",
203 def HasV6KOps : SubtargetFeature<"v6k", "HasV6KOps", "true",
204 "Support ARM v6k instructions",
206 def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
207 "Support ARM v6t2 instructions",
208 [HasV6MOps, HasV6KOps, FeatureThumb2]>;
209 def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
210 "Support ARM v7 instructions",
211 [HasV6T2Ops, FeaturePerfMon]>;
212 def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true",
213 "Support ARM v8 instructions",
215 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
216 "Support ARM v8.1a instructions",
218 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
219 "Support ARM v8.2a instructions",
223 //===----------------------------------------------------------------------===//
224 // ARM Processor subtarget features.
227 def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
228 "Cortex-A5 ARM processors", []>;
229 def ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7",
230 "Cortex-A7 ARM processors", []>;
231 def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
232 "Cortex-A8 ARM processors", []>;
233 def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
234 "Cortex-A9 ARM processors", []>;
235 def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12",
236 "Cortex-A12 ARM processors", []>;
237 def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
238 "Cortex-A15 ARM processors", []>;
239 def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17",
240 "Cortex-A17 ARM processors", []>;
241 def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
242 "Cortex-A35 ARM processors", []>;
243 def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
244 "Cortex-A53 ARM processors", []>;
245 def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
246 "Cortex-A57 ARM processors", []>;
247 def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
248 "Cortex-A72 ARM processors", []>;
250 def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait",
251 "Qualcomm ARM processors", []>;
252 def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
253 "Swift ARM processors", []>;
256 def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4",
257 "Cortex-R4 ARM processors", []>;
258 def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
259 "Cortex-R5 ARM processors", []>;
260 def ProcR7 : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7",
261 "Cortex-R7 ARM processors", []>;
264 //===----------------------------------------------------------------------===//
268 include "ARMSchedule.td"
271 //===----------------------------------------------------------------------===//
275 def ARMv2 : Architecture<"armv2", "ARMv2", []>;
277 def ARMv2a : Architecture<"armv2a", "ARMv2a", []>;
279 def ARMv3 : Architecture<"armv3", "ARMv3", []>;
281 def ARMv3m : Architecture<"armv3m", "ARMv3m", []>;
283 def ARMv4 : Architecture<"armv4", "ARMv4", []>;
285 def ARMv4t : Architecture<"armv4t", "ARMv4t", [HasV4TOps]>;
287 def ARMv5t : Architecture<"armv5t", "ARMv5t", [HasV5TOps]>;
289 def ARMv5te : Architecture<"armv5te", "ARMv5te", [HasV5TEOps]>;
291 def ARMv5tej : Architecture<"armv5tej", "ARMv5tej", [HasV5TEOps]>;
293 def ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops]>;
295 def ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops,
298 def ARMv6k : Architecture<"armv6k", "ARMv6k", [HasV6KOps]>;
300 def ARMv6kz : Architecture<"armv6kz", "ARMv6kz", [HasV6KOps,
303 def ARMv6m : Architecture<"armv6-m", "ARMv6m", [HasV6MOps,
308 def ARMv6sm : Architecture<"armv6s-m", "ARMv6sm", [HasV6MOps,
313 def ARMv7a : Architecture<"armv7-a", "ARMv7a", [HasV7Ops,
319 def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops,
325 def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops,
332 def ARMv7em : Architecture<"armv7e-m", "ARMv7em", [HasV7Ops,
341 def ARMv8a : Architecture<"armv8-a", "ARMv8a", [HasV8Ops,
349 FeatureVirtualization,
353 def ARMv81a : Architecture<"armv8.1-a", "ARMv81a", [HasV8_1aOps,
361 FeatureVirtualization,
365 def ARMv82a : Architecture<"armv8.2-a", "ARMv82a", [HasV8_2aOps,
373 FeatureVirtualization,
378 def IWMMXT : Architecture<"iwmmxt", "ARMv5te", [ARMv5te]>;
379 def IWMMXT2 : Architecture<"iwmmxt2", "ARMv5te", [ARMv5te]>;
380 def XScale : Architecture<"xscale", "ARMv5te", [ARMv5te]>;
381 def ARMv6j : Architecture<"armv6j", "ARMv7a", [ARMv6]>;
382 def ARMv7k : Architecture<"armv7k", "ARMv7a", [ARMv7a]>;
383 def ARMv7s : Architecture<"armv7s", "ARMv7a", [ARMv7a]>;
386 //===----------------------------------------------------------------------===//
390 // Dummy CPU, used to target architectures
391 def : ProcNoItin<"generic", []>;
393 def : ProcNoItin<"arm8", [ARMv4]>;
394 def : ProcNoItin<"arm810", [ARMv4]>;
395 def : ProcNoItin<"strongarm", [ARMv4]>;
396 def : ProcNoItin<"strongarm110", [ARMv4]>;
397 def : ProcNoItin<"strongarm1100", [ARMv4]>;
398 def : ProcNoItin<"strongarm1110", [ARMv4]>;
400 def : ProcNoItin<"arm7tdmi", [ARMv4t]>;
401 def : ProcNoItin<"arm7tdmi-s", [ARMv4t]>;
402 def : ProcNoItin<"arm710t", [ARMv4t]>;
403 def : ProcNoItin<"arm720t", [ARMv4t]>;
404 def : ProcNoItin<"arm9", [ARMv4t]>;
405 def : ProcNoItin<"arm9tdmi", [ARMv4t]>;
406 def : ProcNoItin<"arm920", [ARMv4t]>;
407 def : ProcNoItin<"arm920t", [ARMv4t]>;
408 def : ProcNoItin<"arm922t", [ARMv4t]>;
409 def : ProcNoItin<"arm940t", [ARMv4t]>;
410 def : ProcNoItin<"ep9312", [ARMv4t]>;
412 def : ProcNoItin<"arm10tdmi", [ARMv5t]>;
413 def : ProcNoItin<"arm1020t", [ARMv5t]>;
415 def : ProcNoItin<"arm9e", [ARMv5te]>;
416 def : ProcNoItin<"arm926ej-s", [ARMv5te]>;
417 def : ProcNoItin<"arm946e-s", [ARMv5te]>;
418 def : ProcNoItin<"arm966e-s", [ARMv5te]>;
419 def : ProcNoItin<"arm968e-s", [ARMv5te]>;
420 def : ProcNoItin<"arm10e", [ARMv5te]>;
421 def : ProcNoItin<"arm1020e", [ARMv5te]>;
422 def : ProcNoItin<"arm1022e", [ARMv5te]>;
423 def : ProcNoItin<"xscale", [ARMv5te]>;
424 def : ProcNoItin<"iwmmxt", [ARMv5te]>;
426 def : Processor<"arm1136j-s", ARMV6Itineraries, [ARMv6]>;
427 def : Processor<"arm1136jf-s", ARMV6Itineraries, [ARMv6,
429 FeatureHasSlowFPVMLx]>;
431 def : Processor<"cortex-m0", ARMV6Itineraries, [ARMv6m]>;
432 def : Processor<"cortex-m0plus", ARMV6Itineraries, [ARMv6m]>;
433 def : Processor<"cortex-m1", ARMV6Itineraries, [ARMv6m]>;
434 def : Processor<"sc000", ARMV6Itineraries, [ARMv6m]>;
436 def : Processor<"arm1176jz-s", ARMV6Itineraries, [ARMv6kz]>;
437 def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ARMv6kz,
439 FeatureHasSlowFPVMLx]>;
441 def : Processor<"mpcorenovfp", ARMV6Itineraries, [ARMv6k]>;
442 def : Processor<"mpcore", ARMV6Itineraries, [ARMv6k,
444 FeatureHasSlowFPVMLx]>;
446 def : Processor<"arm1156t2-s", ARMV6Itineraries, [ARMv6t2]>;
447 def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ARMv6t2,
449 FeatureHasSlowFPVMLx]>;
451 // FIXME: A5 has currently the same Schedule model as A8
452 def : ProcessorModel<"cortex-a5", CortexA8Model, [ARMv7a, ProcA5,
456 FeatureHasSlowFPVMLx,
457 FeatureVMLxForwarding,
462 def : ProcessorModel<"cortex-a7", CortexA8Model, [ARMv7a, ProcA7,
466 FeatureHasSlowFPVMLx,
467 FeatureVMLxForwarding,
473 FeatureVirtualization]>;
475 def : ProcessorModel<"cortex-a8", CortexA8Model, [ARMv7a, ProcA8,
479 FeatureHasSlowFPVMLx,
480 FeatureVMLxForwarding,
483 def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9,
486 FeatureVMLxForwarding,
489 FeatureAvoidPartialCPSR,
492 // FIXME: A12 has currently the same Schedule model as A9
493 def : ProcessorModel<"cortex-a12", CortexA9Model, [ARMv7a, ProcA12,
496 FeatureVMLxForwarding,
501 FeatureAvoidPartialCPSR,
502 FeatureVirtualization,
505 // FIXME: A15 has currently the same Schedule model as A9.
506 def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15,
514 FeatureAvoidPartialCPSR,
515 FeatureVirtualization]>;
517 // FIXME: A17 has currently the same Schedule model as A9
518 def : ProcessorModel<"cortex-a17", CortexA9Model, [ARMv7a, ProcA17,
522 FeatureVMLxForwarding,
527 FeatureAvoidPartialCPSR,
528 FeatureVirtualization]>;
530 // FIXME: krait has currently the same Schedule model as A9
531 // FIXME: krait has currently the same features as A9 plus VFP4 and hardware
532 // division features.
533 def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait,
535 FeatureVMLxForwarding,
538 FeatureAvoidPartialCPSR,
543 def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift,
551 FeatureAvoidPartialCPSR,
552 FeatureAvoidMOVsShOp,
553 FeatureHasSlowFPVMLx]>;
555 // FIXME: R4 has currently the same ProcessorModel as A8.
556 def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4,
558 FeatureAvoidPartialCPSR,
561 // FIXME: R4F has currently the same ProcessorModel as A8.
562 def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4,
565 FeatureHasSlowFPVMLx,
568 FeatureAvoidPartialCPSR,
571 // FIXME: R5 has currently the same ProcessorModel as A8.
572 def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5,
578 FeatureHasSlowFPVMLx,
579 FeatureAvoidPartialCPSR,
582 // FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5.
583 def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7,
592 FeatureHasSlowFPVMLx,
593 FeatureAvoidPartialCPSR,
596 def : ProcNoItin<"cortex-m3", [ARMv7m]>;
597 def : ProcNoItin<"sc300", [ARMv7m]>;
599 def : ProcNoItin<"cortex-m4", [ARMv7em,
604 def : ProcNoItin<"cortex-m7", [ARMv7em,
609 def : ProcNoItin<"cortex-a35", [ARMv8a, ProcA35,
616 def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53,
623 def : ProcNoItin<"cortex-a57", [ARMv8a, ProcA57,
630 def : ProcNoItin<"cortex-a72", [ARMv8a, ProcA72,
637 // Cyclone is very similar to swift
638 def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift,
646 FeatureAvoidPartialCPSR,
647 FeatureAvoidMOVsShOp,
648 FeatureHasSlowFPVMLx,
653 //===----------------------------------------------------------------------===//
654 // Register File Description
655 //===----------------------------------------------------------------------===//
657 include "ARMRegisterInfo.td"
659 include "ARMCallingConv.td"
661 //===----------------------------------------------------------------------===//
662 // Instruction Descriptions
663 //===----------------------------------------------------------------------===//
665 include "ARMInstrInfo.td"
667 def ARMInstrInfo : InstrInfo;
669 //===----------------------------------------------------------------------===//
670 // Declare the target which we are implementing
671 //===----------------------------------------------------------------------===//
673 def ARMAsmWriter : AsmWriter {
674 string AsmWriterClassName = "InstPrinter";
675 int PassSubtarget = 1;
677 bit isMCAsmWriter = 1;
680 def ARMAsmParserVariant : AsmParserVariant {
683 string BreakCharacters = ".";
687 // Pull in Instruction Info:
688 let InstructionSet = ARMInstrInfo;
689 let AssemblyWriters = [ARMAsmWriter];
690 let AssemblyParserVariants = [ARMAsmParserVariant];