lib/Target/ARM/ARM.td

   1 //===- ARM.td - Describe the ARM Target Machine -----------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Target-independent interfaces which we are implementing
  15 //===----------------------------------------------------------------------===//
  16
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // ARM Subtarget features.
  21 //
  22
  23 def ArchV4T     : SubtargetFeature<"v4t", "ARMArchVersion", "V4T",
  24                                    "ARM v4T">;
  25 def ArchV5T     : SubtargetFeature<"v5t", "ARMArchVersion", "V5T",
  26                                    "ARM v5T">;
  27 def ArchV5TE    : SubtargetFeature<"v5te", "ARMArchVersion", "V5TE",
  28                                    "ARM v5TE, v5TEj, v5TExp">;
  29 def ArchV6      : SubtargetFeature<"v6", "ARMArchVersion", "V6",
  30                                    "ARM v6">;
  31 def ArchV6T2    : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2",
  32                                    "ARM v6t2">;
  33 def ArchV7A     : SubtargetFeature<"v7a", "ARMArchVersion", "V7A",
  34                                    "ARM v7A">;
  35 def FeatureVFP2 : SubtargetFeature<"vfp2", "ARMFPUType", "VFPv2",
  36                                    "Enable VFP2 instructions">;
  37 def FeatureVFP3 : SubtargetFeature<"vfp3", "ARMFPUType", "VFPv3",
  38                                    "Enable VFP3 instructions">;
  39 def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON",
  40                                    "Enable NEON instructions">;
  41 def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2",
  42                                      "Enable Thumb2 instructions">;
  43
  44 //===----------------------------------------------------------------------===//
  45 // ARM Processors supported.
  46 //
  47
  48 include "ARMSchedule.td"
  49
  50 class ProcNoItin<string Name, list<SubtargetFeature> Features>
  51  : Processor<Name, GenericItineraries, Features>;
  52
  53 // V4 Processors.
  54 def : ProcNoItin<"generic",         []>;
  55 def : ProcNoItin<"arm8",            []>;
  56 def : ProcNoItin<"arm810",          []>;
  57 def : ProcNoItin<"strongarm",       []>;
  58 def : ProcNoItin<"strongarm110",    []>;
  59 def : ProcNoItin<"strongarm1100",   []>;
  60 def : ProcNoItin<"strongarm1110",   []>;
  61
  62 // V4T Processors.
  63 def : ProcNoItin<"arm7tdmi",        [ArchV4T]>;
  64 def : ProcNoItin<"arm7tdmi-s",      [ArchV4T]>;
  65 def : ProcNoItin<"arm710t",         [ArchV4T]>;
  66 def : ProcNoItin<"arm720t",         [ArchV4T]>;
  67 def : ProcNoItin<"arm9",            [ArchV4T]>;
  68 def : ProcNoItin<"arm9tdmi",        [ArchV4T]>;
  69 def : ProcNoItin<"arm920",          [ArchV4T]>;
  70 def : ProcNoItin<"arm920t",         [ArchV4T]>;
  71 def : ProcNoItin<"arm922t",         [ArchV4T]>;
  72 def : ProcNoItin<"arm940t",         [ArchV4T]>;
  73 def : ProcNoItin<"ep9312",          [ArchV4T]>;
  74
  75 // V5T Processors.
  76 def : ProcNoItin<"arm10tdmi",       [ArchV5T]>;
  77 def : ProcNoItin<"arm1020t",        [ArchV5T]>;
  78
  79 // V5TE Processors.
  80 def : ProcNoItin<"arm9e",           [ArchV5TE]>;
  81 def : ProcNoItin<"arm926ej-s",      [ArchV5TE]>;
  82 def : ProcNoItin<"arm946e-s",       [ArchV5TE]>;
  83 def : ProcNoItin<"arm966e-s",       [ArchV5TE]>;
  84 def : ProcNoItin<"arm968e-s",       [ArchV5TE]>;
  85 def : ProcNoItin<"arm10e",          [ArchV5TE]>;
  86 def : ProcNoItin<"arm1020e",        [ArchV5TE]>;
  87 def : ProcNoItin<"arm1022e",        [ArchV5TE]>;
  88 def : ProcNoItin<"xscale",          [ArchV5TE]>;
  89 def : ProcNoItin<"iwmmxt",          [ArchV5TE]>;
  90
  91 // V6 Processors.
  92 def : Processor<"arm1136j-s",       V6Itineraries,
  93                 [ArchV6]>;
  94 def : Processor<"arm1136jf-s",      V6Itineraries,
  95                 [ArchV6, FeatureVFP2]>;
  96 def : Processor<"arm1176jz-s",      V6Itineraries,
  97                 [ArchV6]>;
  98 def : Processor<"arm1176jzf-s",     V6Itineraries,
  99                 [ArchV6, FeatureVFP2]>;
 100 def : Processor<"mpcorenovfp",      V6Itineraries,
 101                 [ArchV6]>;
 102 def : Processor<"mpcore",           V6Itineraries,
 103                 [ArchV6, FeatureVFP2]>;
 104
 105 // V6T2 Processors.
 106 def : Processor<"arm1156t2-s",     V6Itineraries,
 107                 [ArchV6T2, FeatureThumb2]>;
 108 def : Processor<"arm1156t2f-s",    V6Itineraries,
 109                 [ArchV6T2, FeatureThumb2, FeatureVFP2]>;
 110
 111 // V7 Processors.
 112 def : ProcNoItin<"cortex-a8",       [ArchV7A, FeatureThumb2, FeatureNEON]>;
 113 def : ProcNoItin<"cortex-a9",       [ArchV7A, FeatureThumb2, FeatureNEON]>;
 114
 115 //===----------------------------------------------------------------------===//
 116 // Register File Description
 117 //===----------------------------------------------------------------------===//
 118
 119 include "ARMRegisterInfo.td"
 120
 121 include "ARMCallingConv.td"
 122
 123 //===----------------------------------------------------------------------===//
 124 // Instruction Descriptions
 125 //===----------------------------------------------------------------------===//
 126
 127 include "ARMInstrInfo.td"
 128
 129 def ARMInstrInfo : InstrInfo {
 130   // Define how we want to layout our target-specific information field.
 131   let TSFlagsFields = ["AddrModeBits",
 132                        "SizeFlag",
 133                        "IndexModeBits",
 134                        "Form",
 135                        "isUnaryDataProc"];
 136   let TSFlagsShifts = [0,
 137                        4,
 138                        7,
 139                        9,
 140                        15];
 141 }
 142
 143 //===----------------------------------------------------------------------===//
 144 // Declare the target which we are implementing
 145 //===----------------------------------------------------------------------===//
 146
 147 def ARM : Target {
 148   // Pull in Instruction Info:
 149   let InstructionSet = ARMInstrInfo;
 150 }