1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is the parent TargetLowering class for hardware code gen targets.
12 //===----------------------------------------------------------------------===//
14 #include "AMDGPUISelLowering.h"
15 #include "AMDILIntrinsicInfo.h"
16 #include "AMDGPUUtil.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
22 AMDILTargetLowering(TM)
24 // We need to custom lower some of the intrinsics
25 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
27 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
28 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
30 // Library functions. These default to Expand, but we have instructions
32 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
33 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
34 setOperationAction(ISD::FRINT, MVT::f32, Legal);
36 setOperationAction(ISD::UDIV, MVT::i32, Expand);
37 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
38 setOperationAction(ISD::UREM, MVT::i32, Expand);
41 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
44 switch (Op.getOpcode()) {
45 default: return AMDILTargetLowering::LowerOperation(Op, DAG);
46 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
47 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
48 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
52 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
53 SelectionDAG &DAG) const
55 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
56 DebugLoc DL = Op.getDebugLoc();
57 EVT VT = Op.getValueType();
59 switch (IntrinsicID) {
61 case AMDGPUIntrinsic::AMDIL_abs:
62 return LowerIntrinsicIABS(Op, DAG);
63 case AMDGPUIntrinsic::AMDIL_exp:
64 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
65 case AMDGPUIntrinsic::AMDIL_fabs:
66 return DAG.getNode(ISD::FABS, DL, VT, Op.getOperand(1));
67 case AMDGPUIntrinsic::AMDGPU_lrp:
68 return LowerIntrinsicLRP(Op, DAG);
69 case AMDGPUIntrinsic::AMDIL_fraction:
70 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
71 case AMDGPUIntrinsic::AMDIL_mad:
72 return DAG.getNode(AMDILISD::MAD, DL, VT, Op.getOperand(1),
73 Op.getOperand(2), Op.getOperand(3));
74 case AMDGPUIntrinsic::AMDIL_max:
75 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
77 case AMDGPUIntrinsic::AMDGPU_imax:
78 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
80 case AMDGPUIntrinsic::AMDGPU_umax:
81 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
83 case AMDGPUIntrinsic::AMDIL_min:
84 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1),
86 case AMDGPUIntrinsic::AMDGPU_imin:
87 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
89 case AMDGPUIntrinsic::AMDGPU_umin:
90 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
92 case AMDGPUIntrinsic::AMDIL_round_nearest:
93 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
94 case AMDGPUIntrinsic::AMDIL_round_posinf:
95 return DAG.getNode(ISD::FCEIL, DL, VT, Op.getOperand(1));
99 ///IABS(a) = SMAX(sub(0, a), a)
100 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
101 SelectionDAG &DAG) const
104 DebugLoc DL = Op.getDebugLoc();
105 EVT VT = Op.getValueType();
106 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
109 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
112 /// Linear Interpolation
113 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
114 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
115 SelectionDAG &DAG) const
117 DebugLoc DL = Op.getDebugLoc();
118 EVT VT = Op.getValueType();
119 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
120 DAG.getConstantFP(1.0f, MVT::f32),
122 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
124 return DAG.getNode(AMDILISD::MAD, DL, VT, Op.getOperand(1),
129 SDValue AMDGPUTargetLowering::LowerSELECT_CC(SDValue Op,
130 SelectionDAG &DAG) const
132 DebugLoc DL = Op.getDebugLoc();
133 EVT VT = Op.getValueType();
135 SDValue LHS = Op.getOperand(0);
136 SDValue RHS = Op.getOperand(1);
137 SDValue True = Op.getOperand(2);
138 SDValue False = Op.getOperand(3);
139 SDValue CC = Op.getOperand(4);
140 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
143 // LHS and RHS are guaranteed to be the same value type
144 EVT CompareVT = LHS.getValueType();
146 // We need all the operands of SELECT_CC to have the same value type, so if
147 // necessary we need to convert LHS and RHS to be the same type True and
148 // False. True and False are guaranteed to have the same type as this
151 if (CompareVT != VT) {
152 ISD::NodeType ConversionOp = ISD::DELETED_NODE;
153 if (VT == MVT::f32 && CompareVT == MVT::i32) {
154 if (isUnsignedIntSetCC(CCOpcode)) {
155 ConversionOp = ISD::UINT_TO_FP;
157 ConversionOp = ISD::SINT_TO_FP;
159 } else if (VT == MVT::i32 && CompareVT == MVT::f32) {
160 ConversionOp = ISD::FP_TO_SINT;
162 // I don't think there will be any other type pairings.
163 assert(!"Unhandled operand type parings in SELECT_CC");
165 // XXX Check the value of LHS and RHS and avoid creating sequences like
167 LHS = DAG.getNode(ConversionOp, DL, VT, LHS);
168 RHS = DAG.getNode(ConversionOp, DL, VT, RHS);
171 // If True is a hardware TRUE value and False is a hardware FALSE value or
172 // vice-versa we can handle this with a native instruction (SET* instructions).
173 if ((isHWTrueValue(True) && isHWFalseValue(False))) {
174 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
177 // XXX If True is a hardware TRUE value and False is a hardware FALSE value,
178 // we can handle this with a native instruction, but we need to swap true
179 // and false and change the conditional.
180 if (isHWTrueValue(False) && isHWFalseValue(True)) {
183 // XXX Check if we can lower this to a SELECT or if it is supported by a native
184 // operation. (The code below does this but we don't have the Instruction
185 // selection patterns to do this yet.
187 if (isZero(LHS) || isZero(RHS)) {
188 SDValue Cond = (isZero(LHS) ? RHS : LHS);
199 // We can lower to select
206 return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False);
208 // Supported by a native operation (CNDGE, CNDGT)
209 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
214 // If we make it this for it means we have no native instructions to handle
215 // this SELECT_CC, so we must lower it.
216 SDValue HWTrue, HWFalse;
218 if (VT == MVT::f32) {
219 HWTrue = DAG.getConstantFP(1.0f, VT);
220 HWFalse = DAG.getConstantFP(0.0f, VT);
221 } else if (VT == MVT::i32) {
222 HWTrue = DAG.getConstant(-1, VT);
223 HWFalse = DAG.getConstant(0, VT);
226 assert(!"Unhandled value type in LowerSELECT_CC");
229 // Lower this unsupported SELECT_CC into a combination of two supported
230 // SELECT_CC operations.
231 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, HWTrue, HWFalse, CC);
233 return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False);
237 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
238 SelectionDAG &DAG) const
240 DebugLoc DL = Op.getDebugLoc();
241 EVT VT = Op.getValueType();
243 SDValue Num = Op.getOperand(0);
244 SDValue Den = Op.getOperand(1);
246 SmallVector<SDValue, 8> Results;
248 // RCP = URECIP(Den) = 2^32 / Den + e
249 // e is rounding error.
250 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
252 // RCP_LO = umulo(RCP, Den) */
253 SDValue RCP_LO = DAG.getNode(ISD::UMULO, DL, VT, RCP, Den);
255 // RCP_HI = mulhu (RCP, Den) */
256 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
258 // NEG_RCP_LO = -RCP_LO
259 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
262 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
263 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
266 // Calculate the rounding error from the URECIP instruction
267 // E = mulhu(ABS_RCP_LO, RCP)
268 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
271 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
274 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
276 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
277 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
280 // Quotient = mulhu(Tmp0, Num)
281 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
283 // Num_S_Remainder = Quotient * Den
284 SDValue Num_S_Remainder = DAG.getNode(ISD::UMULO, DL, VT, Quotient, Den);
286 // Remainder = Num - Num_S_Remainder
287 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
289 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
290 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
291 DAG.getConstant(-1, VT),
292 DAG.getConstant(0, VT),
294 // Remainder_GE_Zero = (Remainder >= 0 ? -1 : 0)
295 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Remainder,
296 DAG.getConstant(0, VT),
297 DAG.getConstant(-1, VT),
298 DAG.getConstant(0, VT),
300 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
301 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
304 // Calculate Division result:
306 // Quotient_A_One = Quotient + 1
307 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
308 DAG.getConstant(1, VT));
310 // Quotient_S_One = Quotient - 1
311 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
312 DAG.getConstant(1, VT));
314 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
315 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
316 Quotient, Quotient_A_One, ISD::SETEQ);
318 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
319 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
320 Quotient_S_One, Div, ISD::SETEQ);
322 // Calculate Rem result:
324 // Remainder_S_Den = Remainder - Den
325 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
327 // Remainder_A_Den = Remainder + Den
328 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
330 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
331 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
332 Remainder, Remainder_S_Den, ISD::SETEQ);
334 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
335 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
336 Remainder_A_Den, Rem, ISD::SETEQ);
338 DAG.ReplaceAllUsesWith(Op.getValue(0).getNode(), &Div);
339 DAG.ReplaceAllUsesWith(Op.getValue(1).getNode(), &Rem);
344 //===----------------------------------------------------------------------===//
346 //===----------------------------------------------------------------------===//
348 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const
350 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
351 return CFP->isExactlyValue(1.0);
353 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
354 return C->isAllOnesValue();
359 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const
361 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
362 return CFP->getValueAPF().isZero();
364 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
365 return C->isNullValue();
370 void AMDGPUTargetLowering::addLiveIn(MachineInstr * MI,
371 MachineFunction * MF, MachineRegisterInfo & MRI,
372 const TargetInstrInfo * TII, unsigned reg) const
374 AMDGPU::utilAddLiveIn(MF, MRI, TII, reg, MI->getOperand(0).getReg());
377 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
379 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const
382 default: return AMDILTargetLowering::getTargetNodeName(Opcode);
384 NODE_NAME_CASE(FRACT)
391 NODE_NAME_CASE(URECIP)