lib/Target/AMDGPU/AMDGPU.td

   1 //===-- AMDGPU.td - AMDGPU Tablegen files ------------------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 include "llvm/Target/Target.td"
  11
  12 //===----------------------------------------------------------------------===//
  13 // Subtarget Features
  14 //===----------------------------------------------------------------------===//
  15
  16 // Debugging Features
  17
  18 def FeatureDumpCode : SubtargetFeature <"DumpCode",
  19         "DumpCode",
  20         "true",
  21         "Dump MachineInstrs in the CodeEmitter">;
  22
  23 def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
  24         "DumpCode",
  25         "true",
  26         "Dump MachineInstrs in the CodeEmitter">;
  27
  28 def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
  29         "EnableIRStructurizer",
  30         "false",
  31         "Disable IR Structurizer">;
  32
  33 def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
  34         "EnablePromoteAlloca",
  35         "true",
  36         "Enable promote alloca pass">;
  37
  38 // Target features
  39
  40 def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
  41         "EnableIfCvt",
  42         "false",
  43         "Disable the if conversion pass">;
  44
  45 def FeatureFP64 : SubtargetFeature<"fp64",
  46         "FP64",
  47         "true",
  48         "Enable double precision operations">;
  49
  50 def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
  51         "FP64Denormals",
  52         "true",
  53         "Enable double precision denormal handling",
  54         [FeatureFP64]>;
  55
  56 def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
  57         "FastFMAF32",
  58         "true",
  59         "Assuming f32 fma is at least as fast as mul + add",
  60         []>;
  61
  62 // Some instructions do not support denormals despite this flag. Using
  63 // fp32 denormals also causes instructions to run at the double
  64 // precision rate for the device.
  65 def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
  66         "FP32Denormals",
  67         "true",
  68         "Enable single precision denormal handling">;
  69
  70 def Feature64BitPtr : SubtargetFeature<"64BitPtr",
  71         "Is64bit",
  72         "true",
  73         "Specify if 64-bit addressing should be used">;
  74
  75 def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
  76         "R600ALUInst",
  77         "false",
  78         "Older version of ALU instructions encoding">;
  79
  80 def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
  81         "HasVertexCache",
  82         "true",
  83         "Specify use of dedicated vertex cache">;
  84
  85 def FeatureCaymanISA : SubtargetFeature<"caymanISA",
  86         "CaymanISA",
  87         "true",
  88         "Use Cayman ISA">;
  89
  90 def FeatureCFALUBug : SubtargetFeature<"cfalubug",
  91         "CFALUBug",
  92         "true",
  93         "GPU has CF_ALU bug">;
  94
  95 // XXX - This should probably be removed once enabled by default
  96 def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
  97         "EnableLoadStoreOpt",
  98         "true",
  99         "Enable SI load/store optimizer pass">;
 100
 101 // Performance debugging feature. Allow using DS instruction immediate
 102 // offsets even if the base pointer can't be proven to be base. On SI,
 103 // base pointer values that won't give the same result as a 16-bit add
 104 // are not safe to fold, but this will override the conservative test
 105 // for the base pointer.
 106 def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <"unsafe-ds-offset-folding",
 107         "EnableUnsafeDSOffsetFolding",
 108         "true",
 109         "Force using DS instruction immediate offsets on SI">;
 110
 111 def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
 112         "FlatAddressSpace",
 113         "true",
 114         "Support flat address space">;
 115
 116 def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
 117         "EnableVGPRSpilling",
 118         "true",
 119         "Enable spilling of VGPRs to scratch memory">;
 120
 121 def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
 122         "SGPRInitBug",
 123         "true",
 124         "VI SGPR initilization bug requiring a fixed SGPR allocation size">;
 125
 126 class SubtargetFeatureFetchLimit <string Value> :
 127                           SubtargetFeature <"fetch"#Value,
 128         "TexVTXClauseSize",
 129         Value,
 130         "Limit the maximum number of fetches in a clause to "#Value>;
 131
 132 def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
 133 def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
 134
 135 class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
 136         "wavefrontsize"#Value,
 137         "WavefrontSize",
 138         !cast<string>(Value),
 139         "The number of threads per wavefront">;
 140
 141 def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
 142 def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
 143 def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
 144
 145 class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
 146       "ldsbankcount"#Value,
 147       "LDSBankCount",
 148       !cast<string>(Value),
 149       "The number of LDS banks per compute unit.">;
 150
 151 def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
 152 def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
 153
 154 class SubtargetFeatureISAVersion <int Major, int Minor, int Stepping>
 155                                  : SubtargetFeature <
 156       "isaver"#Major#"."#Minor#"."#Stepping,
 157       "IsaVersion",
 158       "ISAVersion"#Major#"_"#Minor#"_"#Stepping,
 159       "Instruction set version number"
 160 >;
 161
 162 def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0>;
 163 def FeatureISAVersion7_0_1 : SubtargetFeatureISAVersion <7,0,1>;
 164 def FeatureISAVersion8_0_0 : SubtargetFeatureISAVersion <8,0,0>;
 165 def FeatureISAVersion8_0_1 : SubtargetFeatureISAVersion <8,0,1>;
 166
 167 class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
 168         "localmemorysize"#Value,
 169         "LocalMemorySize",
 170         !cast<string>(Value),
 171         "The size of local memory in bytes">;
 172
 173 def FeatureGCN : SubtargetFeature<"gcn",
 174         "IsGCN",
 175         "true",
 176         "GCN or newer GPU">;
 177
 178 def FeatureGCN1Encoding : SubtargetFeature<"gcn1-encoding",
 179         "GCN1Encoding",
 180         "true",
 181         "Encoding format for SI and CI">;
 182
 183 def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
 184         "GCN3Encoding",
 185         "true",
 186         "Encoding format for VI">;
 187
 188 def FeatureCIInsts : SubtargetFeature<"ci-insts",
 189         "CIInsts",
 190         "true",
 191         "Additional intstructions for CI+">;
 192
 193 // Dummy feature used to disable assembler instructions.
 194 def FeatureDisable : SubtargetFeature<"",
 195                                       "FeatureDisable","true",
 196                                       "Dummy feature to disable assembler"
 197                                       " instructions">;
 198
 199 class SubtargetFeatureGeneration <string Value,
 200                                   list<SubtargetFeature> Implies> :
 201         SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
 202                           Value#" GPU generation", Implies>;
 203
 204 def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
 205 def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
 206 def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
 207
 208 def FeatureR600 : SubtargetFeatureGeneration<"R600",
 209         [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]>;
 210
 211 def FeatureR700 : SubtargetFeatureGeneration<"R700",
 212         [FeatureFetchLimit16, FeatureLocalMemorySize0]>;
 213
 214 def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
 215         [FeatureFetchLimit16, FeatureLocalMemorySize32768]>;
 216
 217 def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
 218         [FeatureFetchLimit16, FeatureWavefrontSize64,
 219          FeatureLocalMemorySize32768]
 220 >;
 221
 222 def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
 223         [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize32768,
 224          FeatureWavefrontSize64, FeatureGCN, FeatureGCN1Encoding,
 225          FeatureLDSBankCount32]>;
 226
 227 def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
 228         [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
 229          FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
 230          FeatureGCN1Encoding, FeatureCIInsts]>;
 231
 232 def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
 233         [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
 234          FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
 235          FeatureGCN3Encoding, FeatureCIInsts, FeatureLDSBankCount32]>;
 236
 237 //===----------------------------------------------------------------------===//
 238
 239 def AMDGPUInstrInfo : InstrInfo {
 240   let guessInstructionProperties = 1;
 241   let noNamedPositionallyEncodedOperands = 1;
 242 }
 243
 244 def AMDGPUAsmParser : AsmParser {
 245   // Some of the R600 registers have the same name, so this crashes.
 246   // For example T0_XYZW and T0_XY both have the asm name T0.
 247   let ShouldEmitMatchRegisterName = 0;
 248 }
 249
 250 def AMDGPU : Target {
 251   // Pull in Instruction Info:
 252   let InstructionSet = AMDGPUInstrInfo;
 253   let AssemblyParsers = [AMDGPUAsmParser];
 254 }
 255
 256 // Dummy Instruction itineraries for pseudo instructions
 257 def ALU_NULL : FuncUnit;
 258 def NullALU : InstrItinClass;
 259
 260 //===----------------------------------------------------------------------===//
 261 // Predicate helper class
 262 //===----------------------------------------------------------------------===//
 263
 264 def TruePredicate : Predicate<"true">;
 265 def isSICI : Predicate<
 266   "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
 267   "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
 268 >, AssemblerPredicate<"FeatureGCN1Encoding">;
 269
 270 class PredicateControl {
 271   Predicate SubtargetPredicate;
 272   Predicate SIAssemblerPredicate = isSICI;
 273   list<Predicate> AssemblerPredicates = [];
 274   Predicate AssemblerPredicate = TruePredicate;
 275   list<Predicate> OtherPredicates = [];
 276   list<Predicate> Predicates = !listconcat([SubtargetPredicate, AssemblerPredicate],
 277                                             AssemblerPredicates,
 278                                             OtherPredicates);
 279 }
 280
 281 // Include AMDGPU TD files
 282 include "R600Schedule.td"
 283 include "SISchedule.td"
 284 include "Processors.td"
 285 include "AMDGPUInstrInfo.td"
 286 include "AMDGPUIntrinsics.td"
 287 include "AMDGPURegisterInfo.td"
 288 include "AMDGPUInstructions.td"
 289 include "AMDGPUCallingConv.td"