lib/Target/AArch64/Utils/AArch64BaseInfo.cpp

   1 //===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file provides basic encoding and assembly information for AArch64.
  11 //
  12 //===----------------------------------------------------------------------===//
  13 #include "AArch64BaseInfo.h"
  14 #include "llvm/ADT/APFloat.h"
  15 #include "llvm/ADT/SmallVector.h"
  16 #include "llvm/ADT/StringExtras.h"
  17 #include "llvm/Support/Regex.h"
  18
  19 using namespace llvm;
  20
  21 StringRef AArch64NamedImmMapper::toString(uint32_t Value,
  22           const FeatureBitset& FeatureBits, bool &Valid) const {
  23   for (unsigned i = 0; i < NumMappings; ++i) {
  24     if (Mappings[i].isValueEqual(Value, FeatureBits)) {
  25       Valid = true;
  26       return Mappings[i].Name;
  27     }
  28   }
  29
  30   Valid = false;
  31   return StringRef();
  32 }
  33
  34 uint32_t AArch64NamedImmMapper::fromString(StringRef Name,
  35          const FeatureBitset& FeatureBits, bool &Valid) const {
  36   std::string LowerCaseName = Name.lower();
  37   for (unsigned i = 0; i < NumMappings; ++i) {
  38     if (Mappings[i].isNameEqual(LowerCaseName, FeatureBits)) {
  39       Valid = true;
  40       return Mappings[i].Value;
  41     }
  42   }
  43
  44   Valid = false;
  45   return -1;
  46 }
  47
  48 bool AArch64NamedImmMapper::validImm(uint32_t Value) const {
  49   return Value < TooBigImm;
  50 }
  51
  52 const AArch64NamedImmMapper::Mapping AArch64AT::ATMapper::ATMappings[] = {
  53   {"s1e1r", S1E1R, {}},
  54   {"s1e2r", S1E2R, {}},
  55   {"s1e3r", S1E3R, {}},
  56   {"s1e1w", S1E1W, {}},
  57   {"s1e2w", S1E2W, {}},
  58   {"s1e3w", S1E3W, {}},
  59   {"s1e0r", S1E0R, {}},
  60   {"s1e0w", S1E0W, {}},
  61   {"s12e1r", S12E1R, {}},
  62   {"s12e1w", S12E1W, {}},
  63   {"s12e0r", S12E0R, {}},
  64   {"s12e0w", S12E0W, {}},
  65 };
  66
  67 AArch64AT::ATMapper::ATMapper()
  68   : AArch64NamedImmMapper(ATMappings, 0) {}
  69
  70 const AArch64NamedImmMapper::Mapping AArch64DB::DBarrierMapper::DBarrierMappings[] = {
  71   {"oshld", OSHLD, {}},
  72   {"oshst", OSHST, {}},
  73   {"osh", OSH, {}},
  74   {"nshld", NSHLD, {}},
  75   {"nshst", NSHST, {}},
  76   {"nsh", NSH, {}},
  77   {"ishld", ISHLD, {}},
  78   {"ishst", ISHST, {}},
  79   {"ish", ISH, {}},
  80   {"ld", LD, {}},
  81   {"st", ST, {}},
  82   {"sy", SY, {}}
  83 };
  84
  85 AArch64DB::DBarrierMapper::DBarrierMapper()
  86   : AArch64NamedImmMapper(DBarrierMappings, 16u) {}
  87
  88 const AArch64NamedImmMapper::Mapping AArch64DC::DCMapper::DCMappings[] = {
  89   {"zva", ZVA, {}},
  90   {"ivac", IVAC, {}},
  91   {"isw", ISW, {}},
  92   {"cvac", CVAC, {}},
  93   {"csw", CSW, {}},
  94   {"cvau", CVAU, {}},
  95   {"civac", CIVAC, {}},
  96   {"cisw", CISW, {}}
  97 };
  98
  99 AArch64DC::DCMapper::DCMapper()
 100   : AArch64NamedImmMapper(DCMappings, 0) {}
 101
 102 const AArch64NamedImmMapper::Mapping AArch64IC::ICMapper::ICMappings[] = {
 103   {"ialluis",  IALLUIS, {}},
 104   {"iallu", IALLU, {}},
 105   {"ivau", IVAU, {}}
 106 };
 107
 108 AArch64IC::ICMapper::ICMapper()
 109   : AArch64NamedImmMapper(ICMappings, 0) {}
 110
 111 const AArch64NamedImmMapper::Mapping AArch64ISB::ISBMapper::ISBMappings[] = {
 112   {"sy",  SY, {}},
 113 };
 114
 115 AArch64ISB::ISBMapper::ISBMapper()
 116   : AArch64NamedImmMapper(ISBMappings, 16) {}
 117
 118 const AArch64NamedImmMapper::Mapping AArch64PRFM::PRFMMapper::PRFMMappings[] = {
 119   {"pldl1keep", PLDL1KEEP, {}},
 120   {"pldl1strm", PLDL1STRM, {}},
 121   {"pldl2keep", PLDL2KEEP, {}},
 122   {"pldl2strm", PLDL2STRM, {}},
 123   {"pldl3keep", PLDL3KEEP, {}},
 124   {"pldl3strm", PLDL3STRM, {}},
 125   {"plil1keep", PLIL1KEEP, {}},
 126   {"plil1strm", PLIL1STRM, {}},
 127   {"plil2keep", PLIL2KEEP, {}},
 128   {"plil2strm", PLIL2STRM, {}},
 129   {"plil3keep", PLIL3KEEP, {}},
 130   {"plil3strm", PLIL3STRM, {}},
 131   {"pstl1keep", PSTL1KEEP, {}},
 132   {"pstl1strm", PSTL1STRM, {}},
 133   {"pstl2keep", PSTL2KEEP, {}},
 134   {"pstl2strm", PSTL2STRM, {}},
 135   {"pstl3keep", PSTL3KEEP, {}},
 136   {"pstl3strm", PSTL3STRM, {}}
 137 };
 138
 139 AArch64PRFM::PRFMMapper::PRFMMapper()
 140   : AArch64NamedImmMapper(PRFMMappings, 32) {}
 141
 142 const AArch64NamedImmMapper::Mapping AArch64PState::PStateMapper::PStateMappings[] = {
 143   {"spsel", SPSel, {}},
 144   {"daifset", DAIFSet, {}},
 145   {"daifclr", DAIFClr, {}},
 146
 147   // v8.1a "Privileged Access Never" extension-specific PStates
 148   {"pan", PAN, {AArch64::HasV8_1aOps}},
 149
 150   // v8.2a
 151   {"uao", UAO, {AArch64::HasV8_2aOps}},
 152 };
 153
 154 AArch64PState::PStateMapper::PStateMapper()
 155   : AArch64NamedImmMapper(PStateMappings, 0) {}
 156
 157 const AArch64NamedImmMapper::Mapping AArch64PSBHint::PSBHintMapper::PSBHintMappings[] = {
 158   // v8.2a "Statistical Profiling" extension-specific PSB operand
 159   {"csync", CSync, {AArch64::FeatureSPE}},
 160 };
 161
 162 AArch64PSBHint::PSBHintMapper::PSBHintMapper()
 163   : AArch64NamedImmMapper(PSBHintMappings, 0) {}
 164
 165 const AArch64NamedImmMapper::Mapping AArch64SysReg::MRSMapper::MRSMappings[] = {
 166   {"mdccsr_el0", MDCCSR_EL0, {}},
 167   {"dbgdtrrx_el0", DBGDTRRX_EL0, {}},
 168   {"mdrar_el1", MDRAR_EL1, {}},
 169   {"oslsr_el1", OSLSR_EL1, {}},
 170   {"dbgauthstatus_el1", DBGAUTHSTATUS_EL1, {}},
 171   {"pmceid0_el0", PMCEID0_EL0, {}},
 172   {"pmceid1_el0", PMCEID1_EL0, {}},
 173   {"midr_el1", MIDR_EL1, {}},
 174   {"ccsidr_el1", CCSIDR_EL1, {}},
 175   {"clidr_el1", CLIDR_EL1, {}},
 176   {"ctr_el0", CTR_EL0, {}},
 177   {"mpidr_el1", MPIDR_EL1, {}},
 178   {"revidr_el1", REVIDR_EL1, {}},
 179   {"aidr_el1", AIDR_EL1, {}},
 180   {"dczid_el0", DCZID_EL0, {}},
 181   {"id_pfr0_el1", ID_PFR0_EL1, {}},
 182   {"id_pfr1_el1", ID_PFR1_EL1, {}},
 183   {"id_dfr0_el1", ID_DFR0_EL1, {}},
 184   {"id_afr0_el1", ID_AFR0_EL1, {}},
 185   {"id_mmfr0_el1", ID_MMFR0_EL1, {}},
 186   {"id_mmfr1_el1", ID_MMFR1_EL1, {}},
 187   {"id_mmfr2_el1", ID_MMFR2_EL1, {}},
 188   {"id_mmfr3_el1", ID_MMFR3_EL1, {}},
 189   {"id_mmfr4_el1", ID_MMFR4_EL1, {}},
 190   {"id_isar0_el1", ID_ISAR0_EL1, {}},
 191   {"id_isar1_el1", ID_ISAR1_EL1, {}},
 192   {"id_isar2_el1", ID_ISAR2_EL1, {}},
 193   {"id_isar3_el1", ID_ISAR3_EL1, {}},
 194   {"id_isar4_el1", ID_ISAR4_EL1, {}},
 195   {"id_isar5_el1", ID_ISAR5_EL1, {}},
 196   {"id_aa64pfr0_el1", ID_A64PFR0_EL1, {}},
 197   {"id_aa64pfr1_el1", ID_A64PFR1_EL1, {}},
 198   {"id_aa64dfr0_el1", ID_A64DFR0_EL1, {}},
 199   {"id_aa64dfr1_el1", ID_A64DFR1_EL1, {}},
 200   {"id_aa64afr0_el1", ID_A64AFR0_EL1, {}},
 201   {"id_aa64afr1_el1", ID_A64AFR1_EL1, {}},
 202   {"id_aa64isar0_el1", ID_A64ISAR0_EL1, {}},
 203   {"id_aa64isar1_el1", ID_A64ISAR1_EL1, {}},
 204   {"id_aa64mmfr0_el1", ID_A64MMFR0_EL1, {}},
 205   {"id_aa64mmfr1_el1", ID_A64MMFR1_EL1, {}},
 206   {"id_aa64mmfr2_el1", ID_A64MMFR2_EL1, {AArch64::HasV8_2aOps}},
 207   {"mvfr0_el1", MVFR0_EL1, {}},
 208   {"mvfr1_el1", MVFR1_EL1, {}},
 209   {"mvfr2_el1", MVFR2_EL1, {}},
 210   {"rvbar_el1", RVBAR_EL1, {}},
 211   {"rvbar_el2", RVBAR_EL2, {}},
 212   {"rvbar_el3", RVBAR_EL3, {}},
 213   {"isr_el1", ISR_EL1, {}},
 214   {"cntpct_el0", CNTPCT_EL0, {}},
 215   {"cntvct_el0", CNTVCT_EL0, {}},
 216
 217   // Trace registers
 218   {"trcstatr", TRCSTATR, {}},
 219   {"trcidr8", TRCIDR8, {}},
 220   {"trcidr9", TRCIDR9, {}},
 221   {"trcidr10", TRCIDR10, {}},
 222   {"trcidr11", TRCIDR11, {}},
 223   {"trcidr12", TRCIDR12, {}},
 224   {"trcidr13", TRCIDR13, {}},
 225   {"trcidr0", TRCIDR0, {}},
 226   {"trcidr1", TRCIDR1, {}},
 227   {"trcidr2", TRCIDR2, {}},
 228   {"trcidr3", TRCIDR3, {}},
 229   {"trcidr4", TRCIDR4, {}},
 230   {"trcidr5", TRCIDR5, {}},
 231   {"trcidr6", TRCIDR6, {}},
 232   {"trcidr7", TRCIDR7, {}},
 233   {"trcoslsr", TRCOSLSR, {}},
 234   {"trcpdsr", TRCPDSR, {}},
 235   {"trcdevaff0", TRCDEVAFF0, {}},
 236   {"trcdevaff1", TRCDEVAFF1, {}},
 237   {"trclsr", TRCLSR, {}},
 238   {"trcauthstatus", TRCAUTHSTATUS, {}},
 239   {"trcdevarch", TRCDEVARCH, {}},
 240   {"trcdevid", TRCDEVID, {}},
 241   {"trcdevtype", TRCDEVTYPE, {}},
 242   {"trcpidr4", TRCPIDR4, {}},
 243   {"trcpidr5", TRCPIDR5, {}},
 244   {"trcpidr6", TRCPIDR6, {}},
 245   {"trcpidr7", TRCPIDR7, {}},
 246   {"trcpidr0", TRCPIDR0, {}},
 247   {"trcpidr1", TRCPIDR1, {}},
 248   {"trcpidr2", TRCPIDR2, {}},
 249   {"trcpidr3", TRCPIDR3, {}},
 250   {"trccidr0", TRCCIDR0, {}},
 251   {"trccidr1", TRCCIDR1, {}},
 252   {"trccidr2", TRCCIDR2, {}},
 253   {"trccidr3", TRCCIDR3, {}},
 254
 255   // GICv3 registers
 256   {"icc_iar1_el1", ICC_IAR1_EL1, {}},
 257   {"icc_iar0_el1", ICC_IAR0_EL1, {}},
 258   {"icc_hppir1_el1", ICC_HPPIR1_EL1, {}},
 259   {"icc_hppir0_el1", ICC_HPPIR0_EL1, {}},
 260   {"icc_rpr_el1", ICC_RPR_EL1, {}},
 261   {"ich_vtr_el2", ICH_VTR_EL2, {}},
 262   {"ich_eisr_el2", ICH_EISR_EL2, {}},
 263   {"ich_elsr_el2", ICH_ELSR_EL2, {}},
 264
 265   // v8.1a "Limited Ordering Regions" extension-specific system registers
 266   {"lorid_el1", LORID_EL1, {AArch64::HasV8_1aOps}},
 267 };
 268
 269 AArch64SysReg::MRSMapper::MRSMapper() {
 270     InstMappings = &MRSMappings[0];
 271     NumInstMappings = llvm::array_lengthof(MRSMappings);
 272 }
 273
 274 const AArch64NamedImmMapper::Mapping AArch64SysReg::MSRMapper::MSRMappings[] = {
 275   {"dbgdtrtx_el0", DBGDTRTX_EL0, {}},
 276   {"oslar_el1", OSLAR_EL1, {}},
 277   {"pmswinc_el0", PMSWINC_EL0, {}},
 278
 279   // Trace registers
 280   {"trcoslar", TRCOSLAR, {}},
 281   {"trclar", TRCLAR, {}},
 282
 283   // GICv3 registers
 284   {"icc_eoir1_el1", ICC_EOIR1_EL1, {}},
 285   {"icc_eoir0_el1", ICC_EOIR0_EL1, {}},
 286   {"icc_dir_el1", ICC_DIR_EL1, {}},
 287   {"icc_sgi1r_el1", ICC_SGI1R_EL1, {}},
 288   {"icc_asgi1r_el1", ICC_ASGI1R_EL1, {}},
 289   {"icc_sgi0r_el1", ICC_SGI0R_EL1, {}},
 290 };
 291
 292 AArch64SysReg::MSRMapper::MSRMapper() {
 293     InstMappings = &MSRMappings[0];
 294     NumInstMappings = llvm::array_lengthof(MSRMappings);
 295 }
 296
 297
 298 const AArch64NamedImmMapper::Mapping AArch64SysReg::SysRegMapper::SysRegMappings[] = {
 299   {"osdtrrx_el1", OSDTRRX_EL1, {}},
 300   {"osdtrtx_el1",  OSDTRTX_EL1, {}},
 301   {"teecr32_el1", TEECR32_EL1, {}},
 302   {"mdccint_el1", MDCCINT_EL1, {}},
 303   {"mdscr_el1", MDSCR_EL1, {}},
 304   {"dbgdtr_el0", DBGDTR_EL0, {}},
 305   {"oseccr_el1", OSECCR_EL1, {}},
 306   {"dbgvcr32_el2", DBGVCR32_EL2, {}},
 307   {"dbgbvr0_el1", DBGBVR0_EL1, {}},
 308   {"dbgbvr1_el1", DBGBVR1_EL1, {}},
 309   {"dbgbvr2_el1", DBGBVR2_EL1, {}},
 310   {"dbgbvr3_el1", DBGBVR3_EL1, {}},
 311   {"dbgbvr4_el1", DBGBVR4_EL1, {}},
 312   {"dbgbvr5_el1", DBGBVR5_EL1, {}},
 313   {"dbgbvr6_el1", DBGBVR6_EL1, {}},
 314   {"dbgbvr7_el1", DBGBVR7_EL1, {}},
 315   {"dbgbvr8_el1", DBGBVR8_EL1, {}},
 316   {"dbgbvr9_el1", DBGBVR9_EL1, {}},
 317   {"dbgbvr10_el1", DBGBVR10_EL1, {}},
 318   {"dbgbvr11_el1", DBGBVR11_EL1, {}},
 319   {"dbgbvr12_el1", DBGBVR12_EL1, {}},
 320   {"dbgbvr13_el1", DBGBVR13_EL1, {}},
 321   {"dbgbvr14_el1", DBGBVR14_EL1, {}},
 322   {"dbgbvr15_el1", DBGBVR15_EL1, {}},
 323   {"dbgbcr0_el1", DBGBCR0_EL1, {}},
 324   {"dbgbcr1_el1", DBGBCR1_EL1, {}},
 325   {"dbgbcr2_el1", DBGBCR2_EL1, {}},
 326   {"dbgbcr3_el1", DBGBCR3_EL1, {}},
 327   {"dbgbcr4_el1", DBGBCR4_EL1, {}},
 328   {"dbgbcr5_el1", DBGBCR5_EL1, {}},
 329   {"dbgbcr6_el1", DBGBCR6_EL1, {}},
 330   {"dbgbcr7_el1", DBGBCR7_EL1, {}},
 331   {"dbgbcr8_el1", DBGBCR8_EL1, {}},
 332   {"dbgbcr9_el1", DBGBCR9_EL1, {}},
 333   {"dbgbcr10_el1", DBGBCR10_EL1, {}},
 334   {"dbgbcr11_el1", DBGBCR11_EL1, {}},
 335   {"dbgbcr12_el1", DBGBCR12_EL1, {}},
 336   {"dbgbcr13_el1", DBGBCR13_EL1, {}},
 337   {"dbgbcr14_el1", DBGBCR14_EL1, {}},
 338   {"dbgbcr15_el1", DBGBCR15_EL1, {}},
 339   {"dbgwvr0_el1", DBGWVR0_EL1, {}},
 340   {"dbgwvr1_el1", DBGWVR1_EL1, {}},
 341   {"dbgwvr2_el1", DBGWVR2_EL1, {}},
 342   {"dbgwvr3_el1", DBGWVR3_EL1, {}},
 343   {"dbgwvr4_el1", DBGWVR4_EL1, {}},
 344   {"dbgwvr5_el1", DBGWVR5_EL1, {}},
 345   {"dbgwvr6_el1", DBGWVR6_EL1, {}},
 346   {"dbgwvr7_el1", DBGWVR7_EL1, {}},
 347   {"dbgwvr8_el1", DBGWVR8_EL1, {}},
 348   {"dbgwvr9_el1", DBGWVR9_EL1, {}},
 349   {"dbgwvr10_el1", DBGWVR10_EL1, {}},
 350   {"dbgwvr11_el1", DBGWVR11_EL1, {}},
 351   {"dbgwvr12_el1", DBGWVR12_EL1, {}},
 352   {"dbgwvr13_el1", DBGWVR13_EL1, {}},
 353   {"dbgwvr14_el1", DBGWVR14_EL1, {}},
 354   {"dbgwvr15_el1", DBGWVR15_EL1, {}},
 355   {"dbgwcr0_el1", DBGWCR0_EL1, {}},
 356   {"dbgwcr1_el1", DBGWCR1_EL1, {}},
 357   {"dbgwcr2_el1", DBGWCR2_EL1, {}},
 358   {"dbgwcr3_el1", DBGWCR3_EL1, {}},
 359   {"dbgwcr4_el1", DBGWCR4_EL1, {}},
 360   {"dbgwcr5_el1", DBGWCR5_EL1, {}},
 361   {"dbgwcr6_el1", DBGWCR6_EL1, {}},
 362   {"dbgwcr7_el1", DBGWCR7_EL1, {}},
 363   {"dbgwcr8_el1", DBGWCR8_EL1, {}},
 364   {"dbgwcr9_el1", DBGWCR9_EL1, {}},
 365   {"dbgwcr10_el1", DBGWCR10_EL1, {}},
 366   {"dbgwcr11_el1", DBGWCR11_EL1, {}},
 367   {"dbgwcr12_el1", DBGWCR12_EL1, {}},
 368   {"dbgwcr13_el1", DBGWCR13_EL1, {}},
 369   {"dbgwcr14_el1", DBGWCR14_EL1, {}},
 370   {"dbgwcr15_el1", DBGWCR15_EL1, {}},
 371   {"teehbr32_el1", TEEHBR32_EL1, {}},
 372   {"osdlr_el1", OSDLR_EL1, {}},
 373   {"dbgprcr_el1", DBGPRCR_EL1, {}},
 374   {"dbgclaimset_el1", DBGCLAIMSET_EL1, {}},
 375   {"dbgclaimclr_el1", DBGCLAIMCLR_EL1, {}},
 376   {"csselr_el1", CSSELR_EL1, {}},
 377   {"vpidr_el2", VPIDR_EL2, {}},
 378   {"vmpidr_el2", VMPIDR_EL2, {}},
 379   {"sctlr_el1", SCTLR_EL1, {}},
 380   {"sctlr_el2", SCTLR_EL2, {}},
 381   {"sctlr_el3", SCTLR_EL3, {}},
 382   {"actlr_el1", ACTLR_EL1, {}},
 383   {"actlr_el2", ACTLR_EL2, {}},
 384   {"actlr_el3", ACTLR_EL3, {}},
 385   {"cpacr_el1", CPACR_EL1, {}},
 386   {"hcr_el2", HCR_EL2, {}},
 387   {"scr_el3", SCR_EL3, {}},
 388   {"mdcr_el2", MDCR_EL2, {}},
 389   {"sder32_el3", SDER32_EL3, {}},
 390   {"cptr_el2", CPTR_EL2, {}},
 391   {"cptr_el3", CPTR_EL3, {}},
 392   {"hstr_el2", HSTR_EL2, {}},
 393   {"hacr_el2", HACR_EL2, {}},
 394   {"mdcr_el3", MDCR_EL3, {}},
 395   {"ttbr0_el1", TTBR0_EL1, {}},
 396   {"ttbr0_el2", TTBR0_EL2, {}},
 397   {"ttbr0_el3", TTBR0_EL3, {}},
 398   {"ttbr1_el1", TTBR1_EL1, {}},
 399   {"tcr_el1", TCR_EL1, {}},
 400   {"tcr_el2", TCR_EL2, {}},
 401   {"tcr_el3", TCR_EL3, {}},
 402   {"vttbr_el2", VTTBR_EL2, {}},
 403   {"vtcr_el2", VTCR_EL2, {}},
 404   {"dacr32_el2", DACR32_EL2, {}},
 405   {"spsr_el1", SPSR_EL1, {}},
 406   {"spsr_el2", SPSR_EL2, {}},
 407   {"spsr_el3", SPSR_EL3, {}},
 408   {"elr_el1", ELR_EL1, {}},
 409   {"elr_el2", ELR_EL2, {}},
 410   {"elr_el3", ELR_EL3, {}},
 411   {"sp_el0", SP_EL0, {}},
 412   {"sp_el1", SP_EL1, {}},
 413   {"sp_el2", SP_EL2, {}},
 414   {"spsel", SPSel, {}},
 415   {"nzcv", NZCV, {}},
 416   {"daif", DAIF, {}},
 417   {"currentel", CurrentEL, {}},
 418   {"spsr_irq", SPSR_irq, {}},
 419   {"spsr_abt", SPSR_abt, {}},
 420   {"spsr_und", SPSR_und, {}},
 421   {"spsr_fiq", SPSR_fiq, {}},
 422   {"fpcr", FPCR, {}},
 423   {"fpsr", FPSR, {}},
 424   {"dspsr_el0", DSPSR_EL0, {}},
 425   {"dlr_el0", DLR_EL0, {}},
 426   {"ifsr32_el2", IFSR32_EL2, {}},
 427   {"afsr0_el1", AFSR0_EL1, {}},
 428   {"afsr0_el2", AFSR0_EL2, {}},
 429   {"afsr0_el3", AFSR0_EL3, {}},
 430   {"afsr1_el1", AFSR1_EL1, {}},
 431   {"afsr1_el2", AFSR1_EL2, {}},
 432   {"afsr1_el3", AFSR1_EL3, {}},
 433   {"esr_el1", ESR_EL1, {}},
 434   {"esr_el2", ESR_EL2, {}},
 435   {"esr_el3", ESR_EL3, {}},
 436   {"fpexc32_el2", FPEXC32_EL2, {}},
 437   {"far_el1", FAR_EL1, {}},
 438   {"far_el2", FAR_EL2, {}},
 439   {"far_el3", FAR_EL3, {}},
 440   {"hpfar_el2", HPFAR_EL2, {}},
 441   {"par_el1", PAR_EL1, {}},
 442   {"pmcr_el0", PMCR_EL0, {}},
 443   {"pmcntenset_el0", PMCNTENSET_EL0, {}},
 444   {"pmcntenclr_el0", PMCNTENCLR_EL0, {}},
 445   {"pmovsclr_el0", PMOVSCLR_EL0, {}},
 446   {"pmselr_el0", PMSELR_EL0, {}},
 447   {"pmccntr_el0", PMCCNTR_EL0, {}},
 448   {"pmxevtyper_el0", PMXEVTYPER_EL0, {}},
 449   {"pmxevcntr_el0", PMXEVCNTR_EL0, {}},
 450   {"pmuserenr_el0", PMUSERENR_EL0, {}},
 451   {"pmintenset_el1", PMINTENSET_EL1, {}},
 452   {"pmintenclr_el1", PMINTENCLR_EL1, {}},
 453   {"pmovsset_el0", PMOVSSET_EL0, {}},
 454   {"mair_el1", MAIR_EL1, {}},
 455   {"mair_el2", MAIR_EL2, {}},
 456   {"mair_el3", MAIR_EL3, {}},
 457   {"amair_el1", AMAIR_EL1, {}},
 458   {"amair_el2", AMAIR_EL2, {}},
 459   {"amair_el3", AMAIR_EL3, {}},
 460   {"vbar_el1", VBAR_EL1, {}},
 461   {"vbar_el2", VBAR_EL2, {}},
 462   {"vbar_el3", VBAR_EL3, {}},
 463   {"rmr_el1", RMR_EL1, {}},
 464   {"rmr_el2", RMR_EL2, {}},
 465   {"rmr_el3", RMR_EL3, {}},
 466   {"contextidr_el1", CONTEXTIDR_EL1, {}},
 467   {"tpidr_el0", TPIDR_EL0, {}},
 468   {"tpidr_el2", TPIDR_EL2, {}},
 469   {"tpidr_el3", TPIDR_EL3, {}},
 470   {"tpidrro_el0", TPIDRRO_EL0, {}},
 471   {"tpidr_el1", TPIDR_EL1, {}},
 472   {"cntfrq_el0", CNTFRQ_EL0, {}},
 473   {"cntvoff_el2", CNTVOFF_EL2, {}},
 474   {"cntkctl_el1", CNTKCTL_EL1, {}},
 475   {"cnthctl_el2", CNTHCTL_EL2, {}},
 476   {"cntp_tval_el0", CNTP_TVAL_EL0, {}},
 477   {"cnthp_tval_el2", CNTHP_TVAL_EL2, {}},
 478   {"cntps_tval_el1", CNTPS_TVAL_EL1, {}},
 479   {"cntp_ctl_el0", CNTP_CTL_EL0, {}},
 480   {"cnthp_ctl_el2", CNTHP_CTL_EL2, {}},
 481   {"cntps_ctl_el1", CNTPS_CTL_EL1, {}},
 482   {"cntp_cval_el0", CNTP_CVAL_EL0, {}},
 483   {"cnthp_cval_el2", CNTHP_CVAL_EL2, {}},
 484   {"cntps_cval_el1", CNTPS_CVAL_EL1, {}},
 485   {"cntv_tval_el0", CNTV_TVAL_EL0, {}},
 486   {"cntv_ctl_el0", CNTV_CTL_EL0, {}},
 487   {"cntv_cval_el0", CNTV_CVAL_EL0, {}},
 488   {"pmevcntr0_el0", PMEVCNTR0_EL0, {}},
 489   {"pmevcntr1_el0", PMEVCNTR1_EL0, {}},
 490   {"pmevcntr2_el0", PMEVCNTR2_EL0, {}},
 491   {"pmevcntr3_el0", PMEVCNTR3_EL0, {}},
 492   {"pmevcntr4_el0", PMEVCNTR4_EL0, {}},
 493   {"pmevcntr5_el0", PMEVCNTR5_EL0, {}},
 494   {"pmevcntr6_el0", PMEVCNTR6_EL0, {}},
 495   {"pmevcntr7_el0", PMEVCNTR7_EL0, {}},
 496   {"pmevcntr8_el0", PMEVCNTR8_EL0, {}},
 497   {"pmevcntr9_el0", PMEVCNTR9_EL0, {}},
 498   {"pmevcntr10_el0", PMEVCNTR10_EL0, {}},
 499   {"pmevcntr11_el0", PMEVCNTR11_EL0, {}},
 500   {"pmevcntr12_el0", PMEVCNTR12_EL0, {}},
 501   {"pmevcntr13_el0", PMEVCNTR13_EL0, {}},
 502   {"pmevcntr14_el0", PMEVCNTR14_EL0, {}},
 503   {"pmevcntr15_el0", PMEVCNTR15_EL0, {}},
 504   {"pmevcntr16_el0", PMEVCNTR16_EL0, {}},
 505   {"pmevcntr17_el0", PMEVCNTR17_EL0, {}},
 506   {"pmevcntr18_el0", PMEVCNTR18_EL0, {}},
 507   {"pmevcntr19_el0", PMEVCNTR19_EL0, {}},
 508   {"pmevcntr20_el0", PMEVCNTR20_EL0, {}},
 509   {"pmevcntr21_el0", PMEVCNTR21_EL0, {}},
 510   {"pmevcntr22_el0", PMEVCNTR22_EL0, {}},
 511   {"pmevcntr23_el0", PMEVCNTR23_EL0, {}},
 512   {"pmevcntr24_el0", PMEVCNTR24_EL0, {}},
 513   {"pmevcntr25_el0", PMEVCNTR25_EL0, {}},
 514   {"pmevcntr26_el0", PMEVCNTR26_EL0, {}},
 515   {"pmevcntr27_el0", PMEVCNTR27_EL0, {}},
 516   {"pmevcntr28_el0", PMEVCNTR28_EL0, {}},
 517   {"pmevcntr29_el0", PMEVCNTR29_EL0, {}},
 518   {"pmevcntr30_el0", PMEVCNTR30_EL0, {}},
 519   {"pmccfiltr_el0", PMCCFILTR_EL0, {}},
 520   {"pmevtyper0_el0", PMEVTYPER0_EL0, {}},
 521   {"pmevtyper1_el0", PMEVTYPER1_EL0, {}},
 522   {"pmevtyper2_el0", PMEVTYPER2_EL0, {}},
 523   {"pmevtyper3_el0", PMEVTYPER3_EL0, {}},
 524   {"pmevtyper4_el0", PMEVTYPER4_EL0, {}},
 525   {"pmevtyper5_el0", PMEVTYPER5_EL0, {}},
 526   {"pmevtyper6_el0", PMEVTYPER6_EL0, {}},
 527   {"pmevtyper7_el0", PMEVTYPER7_EL0, {}},
 528   {"pmevtyper8_el0", PMEVTYPER8_EL0, {}},
 529   {"pmevtyper9_el0", PMEVTYPER9_EL0, {}},
 530   {"pmevtyper10_el0", PMEVTYPER10_EL0, {}},
 531   {"pmevtyper11_el0", PMEVTYPER11_EL0, {}},
 532   {"pmevtyper12_el0", PMEVTYPER12_EL0, {}},
 533   {"pmevtyper13_el0", PMEVTYPER13_EL0, {}},
 534   {"pmevtyper14_el0", PMEVTYPER14_EL0, {}},
 535   {"pmevtyper15_el0", PMEVTYPER15_EL0, {}},
 536   {"pmevtyper16_el0", PMEVTYPER16_EL0, {}},
 537   {"pmevtyper17_el0", PMEVTYPER17_EL0, {}},
 538   {"pmevtyper18_el0", PMEVTYPER18_EL0, {}},
 539   {"pmevtyper19_el0", PMEVTYPER19_EL0, {}},
 540   {"pmevtyper20_el0", PMEVTYPER20_EL0, {}},
 541   {"pmevtyper21_el0", PMEVTYPER21_EL0, {}},
 542   {"pmevtyper22_el0", PMEVTYPER22_EL0, {}},
 543   {"pmevtyper23_el0", PMEVTYPER23_EL0, {}},
 544   {"pmevtyper24_el0", PMEVTYPER24_EL0, {}},
 545   {"pmevtyper25_el0", PMEVTYPER25_EL0, {}},
 546   {"pmevtyper26_el0", PMEVTYPER26_EL0, {}},
 547   {"pmevtyper27_el0", PMEVTYPER27_EL0, {}},
 548   {"pmevtyper28_el0", PMEVTYPER28_EL0, {}},
 549   {"pmevtyper29_el0", PMEVTYPER29_EL0, {}},
 550   {"pmevtyper30_el0", PMEVTYPER30_EL0, {}},
 551
 552   // Trace registers
 553   {"trcprgctlr", TRCPRGCTLR, {}},
 554   {"trcprocselr", TRCPROCSELR, {}},
 555   {"trcconfigr", TRCCONFIGR, {}},
 556   {"trcauxctlr", TRCAUXCTLR, {}},
 557   {"trceventctl0r", TRCEVENTCTL0R, {}},
 558   {"trceventctl1r", TRCEVENTCTL1R, {}},
 559   {"trcstallctlr", TRCSTALLCTLR, {}},
 560   {"trctsctlr", TRCTSCTLR, {}},
 561   {"trcsyncpr", TRCSYNCPR, {}},
 562   {"trcccctlr", TRCCCCTLR, {}},
 563   {"trcbbctlr", TRCBBCTLR, {}},
 564   {"trctraceidr", TRCTRACEIDR, {}},
 565   {"trcqctlr", TRCQCTLR, {}},
 566   {"trcvictlr", TRCVICTLR, {}},
 567   {"trcviiectlr", TRCVIIECTLR, {}},
 568   {"trcvissctlr", TRCVISSCTLR, {}},
 569   {"trcvipcssctlr", TRCVIPCSSCTLR, {}},
 570   {"trcvdctlr", TRCVDCTLR, {}},
 571   {"trcvdsacctlr", TRCVDSACCTLR, {}},
 572   {"trcvdarcctlr", TRCVDARCCTLR, {}},
 573   {"trcseqevr0", TRCSEQEVR0, {}},
 574   {"trcseqevr1", TRCSEQEVR1, {}},
 575   {"trcseqevr2", TRCSEQEVR2, {}},
 576   {"trcseqrstevr", TRCSEQRSTEVR, {}},
 577   {"trcseqstr", TRCSEQSTR, {}},
 578   {"trcextinselr", TRCEXTINSELR, {}},
 579   {"trccntrldvr0", TRCCNTRLDVR0, {}},
 580   {"trccntrldvr1", TRCCNTRLDVR1, {}},
 581   {"trccntrldvr2", TRCCNTRLDVR2, {}},
 582   {"trccntrldvr3", TRCCNTRLDVR3, {}},
 583   {"trccntctlr0", TRCCNTCTLR0, {}},
 584   {"trccntctlr1", TRCCNTCTLR1, {}},
 585   {"trccntctlr2", TRCCNTCTLR2, {}},
 586   {"trccntctlr3", TRCCNTCTLR3, {}},
 587   {"trccntvr0", TRCCNTVR0, {}},
 588   {"trccntvr1", TRCCNTVR1, {}},
 589   {"trccntvr2", TRCCNTVR2, {}},
 590   {"trccntvr3", TRCCNTVR3, {}},
 591   {"trcimspec0", TRCIMSPEC0, {}},
 592   {"trcimspec1", TRCIMSPEC1, {}},
 593   {"trcimspec2", TRCIMSPEC2, {}},
 594   {"trcimspec3", TRCIMSPEC3, {}},
 595   {"trcimspec4", TRCIMSPEC4, {}},
 596   {"trcimspec5", TRCIMSPEC5, {}},
 597   {"trcimspec6", TRCIMSPEC6, {}},
 598   {"trcimspec7", TRCIMSPEC7, {}},
 599   {"trcrsctlr2", TRCRSCTLR2, {}},
 600   {"trcrsctlr3", TRCRSCTLR3, {}},
 601   {"trcrsctlr4", TRCRSCTLR4, {}},
 602   {"trcrsctlr5", TRCRSCTLR5, {}},
 603   {"trcrsctlr6", TRCRSCTLR6, {}},
 604   {"trcrsctlr7", TRCRSCTLR7, {}},
 605   {"trcrsctlr8", TRCRSCTLR8, {}},
 606   {"trcrsctlr9", TRCRSCTLR9, {}},
 607   {"trcrsctlr10", TRCRSCTLR10, {}},
 608   {"trcrsctlr11", TRCRSCTLR11, {}},
 609   {"trcrsctlr12", TRCRSCTLR12, {}},
 610   {"trcrsctlr13", TRCRSCTLR13, {}},
 611   {"trcrsctlr14", TRCRSCTLR14, {}},
 612   {"trcrsctlr15", TRCRSCTLR15, {}},
 613   {"trcrsctlr16", TRCRSCTLR16, {}},
 614   {"trcrsctlr17", TRCRSCTLR17, {}},
 615   {"trcrsctlr18", TRCRSCTLR18, {}},
 616   {"trcrsctlr19", TRCRSCTLR19, {}},
 617   {"trcrsctlr20", TRCRSCTLR20, {}},
 618   {"trcrsctlr21", TRCRSCTLR21, {}},
 619   {"trcrsctlr22", TRCRSCTLR22, {}},
 620   {"trcrsctlr23", TRCRSCTLR23, {}},
 621   {"trcrsctlr24", TRCRSCTLR24, {}},
 622   {"trcrsctlr25", TRCRSCTLR25, {}},
 623   {"trcrsctlr26", TRCRSCTLR26, {}},
 624   {"trcrsctlr27", TRCRSCTLR27, {}},
 625   {"trcrsctlr28", TRCRSCTLR28, {}},
 626   {"trcrsctlr29", TRCRSCTLR29, {}},
 627   {"trcrsctlr30", TRCRSCTLR30, {}},
 628   {"trcrsctlr31", TRCRSCTLR31, {}},
 629   {"trcssccr0", TRCSSCCR0, {}},
 630   {"trcssccr1", TRCSSCCR1, {}},
 631   {"trcssccr2", TRCSSCCR2, {}},
 632   {"trcssccr3", TRCSSCCR3, {}},
 633   {"trcssccr4", TRCSSCCR4, {}},
 634   {"trcssccr5", TRCSSCCR5, {}},
 635   {"trcssccr6", TRCSSCCR6, {}},
 636   {"trcssccr7", TRCSSCCR7, {}},
 637   {"trcsscsr0", TRCSSCSR0, {}},
 638   {"trcsscsr1", TRCSSCSR1, {}},
 639   {"trcsscsr2", TRCSSCSR2, {}},
 640   {"trcsscsr3", TRCSSCSR3, {}},
 641   {"trcsscsr4", TRCSSCSR4, {}},
 642   {"trcsscsr5", TRCSSCSR5, {}},
 643   {"trcsscsr6", TRCSSCSR6, {}},
 644   {"trcsscsr7", TRCSSCSR7, {}},
 645   {"trcsspcicr0", TRCSSPCICR0, {}},
 646   {"trcsspcicr1", TRCSSPCICR1, {}},
 647   {"trcsspcicr2", TRCSSPCICR2, {}},
 648   {"trcsspcicr3", TRCSSPCICR3, {}},
 649   {"trcsspcicr4", TRCSSPCICR4, {}},
 650   {"trcsspcicr5", TRCSSPCICR5, {}},
 651   {"trcsspcicr6", TRCSSPCICR6, {}},
 652   {"trcsspcicr7", TRCSSPCICR7, {}},
 653   {"trcpdcr", TRCPDCR, {}},
 654   {"trcacvr0", TRCACVR0, {}},
 655   {"trcacvr1", TRCACVR1, {}},
 656   {"trcacvr2", TRCACVR2, {}},
 657   {"trcacvr3", TRCACVR3, {}},
 658   {"trcacvr4", TRCACVR4, {}},
 659   {"trcacvr5", TRCACVR5, {}},
 660   {"trcacvr6", TRCACVR6, {}},
 661   {"trcacvr7", TRCACVR7, {}},
 662   {"trcacvr8", TRCACVR8, {}},
 663   {"trcacvr9", TRCACVR9, {}},
 664   {"trcacvr10", TRCACVR10, {}},
 665   {"trcacvr11", TRCACVR11, {}},
 666   {"trcacvr12", TRCACVR12, {}},
 667   {"trcacvr13", TRCACVR13, {}},
 668   {"trcacvr14", TRCACVR14, {}},
 669   {"trcacvr15", TRCACVR15, {}},
 670   {"trcacatr0", TRCACATR0, {}},
 671   {"trcacatr1", TRCACATR1, {}},
 672   {"trcacatr2", TRCACATR2, {}},
 673   {"trcacatr3", TRCACATR3, {}},
 674   {"trcacatr4", TRCACATR4, {}},
 675   {"trcacatr5", TRCACATR5, {}},
 676   {"trcacatr6", TRCACATR6, {}},
 677   {"trcacatr7", TRCACATR7, {}},
 678   {"trcacatr8", TRCACATR8, {}},
 679   {"trcacatr9", TRCACATR9, {}},
 680   {"trcacatr10", TRCACATR10, {}},
 681   {"trcacatr11", TRCACATR11, {}},
 682   {"trcacatr12", TRCACATR12, {}},
 683   {"trcacatr13", TRCACATR13, {}},
 684   {"trcacatr14", TRCACATR14, {}},
 685   {"trcacatr15", TRCACATR15, {}},
 686   {"trcdvcvr0", TRCDVCVR0, {}},
 687   {"trcdvcvr1", TRCDVCVR1, {}},
 688   {"trcdvcvr2", TRCDVCVR2, {}},
 689   {"trcdvcvr3", TRCDVCVR3, {}},
 690   {"trcdvcvr4", TRCDVCVR4, {}},
 691   {"trcdvcvr5", TRCDVCVR5, {}},
 692   {"trcdvcvr6", TRCDVCVR6, {}},
 693   {"trcdvcvr7", TRCDVCVR7, {}},
 694   {"trcdvcmr0", TRCDVCMR0, {}},
 695   {"trcdvcmr1", TRCDVCMR1, {}},
 696   {"trcdvcmr2", TRCDVCMR2, {}},
 697   {"trcdvcmr3", TRCDVCMR3, {}},
 698   {"trcdvcmr4", TRCDVCMR4, {}},
 699   {"trcdvcmr5", TRCDVCMR5, {}},
 700   {"trcdvcmr6", TRCDVCMR6, {}},
 701   {"trcdvcmr7", TRCDVCMR7, {}},
 702   {"trccidcvr0", TRCCIDCVR0, {}},
 703   {"trccidcvr1", TRCCIDCVR1, {}},
 704   {"trccidcvr2", TRCCIDCVR2, {}},
 705   {"trccidcvr3", TRCCIDCVR3, {}},
 706   {"trccidcvr4", TRCCIDCVR4, {}},
 707   {"trccidcvr5", TRCCIDCVR5, {}},
 708   {"trccidcvr6", TRCCIDCVR6, {}},
 709   {"trccidcvr7", TRCCIDCVR7, {}},
 710   {"trcvmidcvr0", TRCVMIDCVR0, {}},
 711   {"trcvmidcvr1", TRCVMIDCVR1, {}},
 712   {"trcvmidcvr2", TRCVMIDCVR2, {}},
 713   {"trcvmidcvr3", TRCVMIDCVR3, {}},
 714   {"trcvmidcvr4", TRCVMIDCVR4, {}},
 715   {"trcvmidcvr5", TRCVMIDCVR5, {}},
 716   {"trcvmidcvr6", TRCVMIDCVR6, {}},
 717   {"trcvmidcvr7", TRCVMIDCVR7, {}},
 718   {"trccidcctlr0", TRCCIDCCTLR0, {}},
 719   {"trccidcctlr1", TRCCIDCCTLR1, {}},
 720   {"trcvmidcctlr0", TRCVMIDCCTLR0, {}},
 721   {"trcvmidcctlr1", TRCVMIDCCTLR1, {}},
 722   {"trcitctrl", TRCITCTRL, {}},
 723   {"trcclaimset", TRCCLAIMSET, {}},
 724   {"trcclaimclr", TRCCLAIMCLR, {}},
 725
 726   // GICv3 registers
 727   {"icc_bpr1_el1", ICC_BPR1_EL1, {}},
 728   {"icc_bpr0_el1", ICC_BPR0_EL1, {}},
 729   {"icc_pmr_el1", ICC_PMR_EL1, {}},
 730   {"icc_ctlr_el1", ICC_CTLR_EL1, {}},
 731   {"icc_ctlr_el3", ICC_CTLR_EL3, {}},
 732   {"icc_sre_el1", ICC_SRE_EL1, {}},
 733   {"icc_sre_el2", ICC_SRE_EL2, {}},
 734   {"icc_sre_el3", ICC_SRE_EL3, {}},
 735   {"icc_igrpen0_el1", ICC_IGRPEN0_EL1, {}},
 736   {"icc_igrpen1_el1", ICC_IGRPEN1_EL1, {}},
 737   {"icc_igrpen1_el3", ICC_IGRPEN1_EL3, {}},
 738   {"icc_seien_el1", ICC_SEIEN_EL1, {}},
 739   {"icc_ap0r0_el1", ICC_AP0R0_EL1, {}},
 740   {"icc_ap0r1_el1", ICC_AP0R1_EL1, {}},
 741   {"icc_ap0r2_el1", ICC_AP0R2_EL1, {}},
 742   {"icc_ap0r3_el1", ICC_AP0R3_EL1, {}},
 743   {"icc_ap1r0_el1", ICC_AP1R0_EL1, {}},
 744   {"icc_ap1r1_el1", ICC_AP1R1_EL1, {}},
 745   {"icc_ap1r2_el1", ICC_AP1R2_EL1, {}},
 746   {"icc_ap1r3_el1", ICC_AP1R3_EL1, {}},
 747   {"ich_ap0r0_el2", ICH_AP0R0_EL2, {}},
 748   {"ich_ap0r1_el2", ICH_AP0R1_EL2, {}},
 749   {"ich_ap0r2_el2", ICH_AP0R2_EL2, {}},
 750   {"ich_ap0r3_el2", ICH_AP0R3_EL2, {}},
 751   {"ich_ap1r0_el2", ICH_AP1R0_EL2, {}},
 752   {"ich_ap1r1_el2", ICH_AP1R1_EL2, {}},
 753   {"ich_ap1r2_el2", ICH_AP1R2_EL2, {}},
 754   {"ich_ap1r3_el2", ICH_AP1R3_EL2, {}},
 755   {"ich_hcr_el2", ICH_HCR_EL2, {}},
 756   {"ich_misr_el2", ICH_MISR_EL2, {}},
 757   {"ich_vmcr_el2", ICH_VMCR_EL2, {}},
 758   {"ich_vseir_el2", ICH_VSEIR_EL2, {}},
 759   {"ich_lr0_el2", ICH_LR0_EL2, {}},
 760   {"ich_lr1_el2", ICH_LR1_EL2, {}},
 761   {"ich_lr2_el2", ICH_LR2_EL2, {}},
 762   {"ich_lr3_el2", ICH_LR3_EL2, {}},
 763   {"ich_lr4_el2", ICH_LR4_EL2, {}},
 764   {"ich_lr5_el2", ICH_LR5_EL2, {}},
 765   {"ich_lr6_el2", ICH_LR6_EL2, {}},
 766   {"ich_lr7_el2", ICH_LR7_EL2, {}},
 767   {"ich_lr8_el2", ICH_LR8_EL2, {}},
 768   {"ich_lr9_el2", ICH_LR9_EL2, {}},
 769   {"ich_lr10_el2", ICH_LR10_EL2, {}},
 770   {"ich_lr11_el2", ICH_LR11_EL2, {}},
 771   {"ich_lr12_el2", ICH_LR12_EL2, {}},
 772   {"ich_lr13_el2", ICH_LR13_EL2, {}},
 773   {"ich_lr14_el2", ICH_LR14_EL2, {}},
 774   {"ich_lr15_el2", ICH_LR15_EL2, {}},
 775
 776   // Cyclone registers
 777   {"cpm_ioacc_ctl_el3", CPM_IOACC_CTL_EL3, {AArch64::ProcCyclone}},
 778
 779   // v8.1a "Privileged Access Never" extension-specific system registers
 780   {"pan", PAN, {AArch64::HasV8_1aOps}},
 781
 782   // v8.1a "Limited Ordering Regions" extension-specific system registers
 783   {"lorsa_el1", LORSA_EL1, {AArch64::HasV8_1aOps}},
 784   {"lorea_el1", LOREA_EL1, {AArch64::HasV8_1aOps}},
 785   {"lorn_el1", LORN_EL1, {AArch64::HasV8_1aOps}},
 786   {"lorc_el1", LORC_EL1, {AArch64::HasV8_1aOps}},
 787
 788   // v8.1a "Virtualization host extensions" system registers
 789   {"ttbr1_el2", TTBR1_EL2, {AArch64::HasV8_1aOps}},
 790   {"contextidr_el2", CONTEXTIDR_EL2, {AArch64::HasV8_1aOps}},
 791   {"cnthv_tval_el2", CNTHV_TVAL_EL2, {AArch64::HasV8_1aOps}},
 792   {"cnthv_cval_el2", CNTHV_CVAL_EL2, {AArch64::HasV8_1aOps}},
 793   {"cnthv_ctl_el2", CNTHV_CTL_EL2, {AArch64::HasV8_1aOps}},
 794   {"sctlr_el12", SCTLR_EL12, {AArch64::HasV8_1aOps}},
 795   {"cpacr_el12", CPACR_EL12, {AArch64::HasV8_1aOps}},
 796   {"ttbr0_el12", TTBR0_EL12, {AArch64::HasV8_1aOps}},
 797   {"ttbr1_el12", TTBR1_EL12, {AArch64::HasV8_1aOps}},
 798   {"tcr_el12", TCR_EL12, {AArch64::HasV8_1aOps}},
 799   {"afsr0_el12", AFSR0_EL12, {AArch64::HasV8_1aOps}},
 800   {"afsr1_el12", AFSR1_EL12, {AArch64::HasV8_1aOps}},
 801   {"esr_el12", ESR_EL12, {AArch64::HasV8_1aOps}},
 802   {"far_el12", FAR_EL12, {AArch64::HasV8_1aOps}},
 803   {"mair_el12", MAIR_EL12, {AArch64::HasV8_1aOps}},
 804   {"amair_el12", AMAIR_EL12, {AArch64::HasV8_1aOps}},
 805   {"vbar_el12", VBAR_EL12, {AArch64::HasV8_1aOps}},
 806   {"contextidr_el12", CONTEXTIDR_EL12, {AArch64::HasV8_1aOps}},
 807   {"cntkctl_el12", CNTKCTL_EL12, {AArch64::HasV8_1aOps}},
 808   {"cntp_tval_el02", CNTP_TVAL_EL02, {AArch64::HasV8_1aOps}},
 809   {"cntp_ctl_el02", CNTP_CTL_EL02, {AArch64::HasV8_1aOps}},
 810   {"cntp_cval_el02", CNTP_CVAL_EL02, {AArch64::HasV8_1aOps}},
 811   {"cntv_tval_el02", CNTV_TVAL_EL02, {AArch64::HasV8_1aOps}},
 812   {"cntv_ctl_el02", CNTV_CTL_EL02, {AArch64::HasV8_1aOps}},
 813   {"cntv_cval_el02", CNTV_CVAL_EL02, {AArch64::HasV8_1aOps}},
 814   {"spsr_el12", SPSR_EL12, {AArch64::HasV8_1aOps}},
 815   {"elr_el12", ELR_EL12, {AArch64::HasV8_1aOps}},
 816
 817   // v8.2a registers
 818   {"uao",           UAO,           {AArch64::HasV8_2aOps}},
 819
 820   // v8.2a "Statistical Profiling extension" registers
 821   {"pmblimitr_el1", PMBLIMITR_EL1, {AArch64::FeatureSPE}},
 822   {"pmbptr_el1",    PMBPTR_EL1,    {AArch64::FeatureSPE}},
 823   {"pmbsr_el1",     PMBSR_EL1,     {AArch64::FeatureSPE}},
 824   {"pmbidr_el1",    PMBIDR_EL1,    {AArch64::FeatureSPE}},
 825   {"pmscr_el2",     PMSCR_EL2,     {AArch64::FeatureSPE}},
 826   {"pmscr_el12",    PMSCR_EL12,    {AArch64::FeatureSPE}},
 827   {"pmscr_el1",     PMSCR_EL1,     {AArch64::FeatureSPE}},
 828   {"pmsicr_el1",    PMSICR_EL1,    {AArch64::FeatureSPE}},
 829   {"pmsirr_el1",    PMSIRR_EL1,    {AArch64::FeatureSPE}},
 830   {"pmsfcr_el1",    PMSFCR_EL1,    {AArch64::FeatureSPE}},
 831   {"pmsevfr_el1",   PMSEVFR_EL1,   {AArch64::FeatureSPE}},
 832   {"pmslatfr_el1",  PMSLATFR_EL1,  {AArch64::FeatureSPE}},
 833   {"pmsidr_el1",    PMSIDR_EL1,    {AArch64::FeatureSPE}},
 834 };
 835
 836 uint32_t
 837 AArch64SysReg::SysRegMapper::fromString(StringRef Name,
 838     const FeatureBitset& FeatureBits, bool &Valid) const {
 839   std::string NameLower = Name.lower();
 840
 841   // First search the registers shared by all
 842   for (unsigned i = 0; i < array_lengthof(SysRegMappings); ++i) {
 843     if (SysRegMappings[i].isNameEqual(NameLower, FeatureBits)) {
 844       Valid = true;
 845       return SysRegMappings[i].Value;
 846     }
 847   }
 848
 849   // Now try the instruction-specific registers (either read-only or
 850   // write-only).
 851   for (unsigned i = 0; i < NumInstMappings; ++i) {
 852     if (InstMappings[i].isNameEqual(NameLower, FeatureBits)) {
 853       Valid = true;
 854       return InstMappings[i].Value;
 855     }
 856   }
 857
 858   // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name
 859   Regex GenericRegPattern("^s([0-3])_([0-7])_c([0-9]|1[0-5])_c([0-9]|1[0-5])_([0-7])$");
 860
 861   SmallVector<StringRef, 5> Ops;
 862   if (!GenericRegPattern.match(NameLower, &Ops)) {
 863     Valid = false;
 864     return -1;
 865   }
 866
 867   uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
 868   uint32_t Bits;
 869   Ops[1].getAsInteger(10, Op0);
 870   Ops[2].getAsInteger(10, Op1);
 871   Ops[3].getAsInteger(10, CRn);
 872   Ops[4].getAsInteger(10, CRm);
 873   Ops[5].getAsInteger(10, Op2);
 874   Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
 875
 876   Valid = true;
 877   return Bits;
 878 }
 879
 880 std::string
 881 AArch64SysReg::SysRegMapper::toString(uint32_t Bits,
 882                                       const FeatureBitset& FeatureBits) const {
 883   // First search the registers shared by all
 884   for (unsigned i = 0; i < array_lengthof(SysRegMappings); ++i) {
 885     if (SysRegMappings[i].isValueEqual(Bits, FeatureBits)) {
 886       return SysRegMappings[i].Name;
 887     }
 888   }
 889
 890   // Now try the instruction-specific registers (either read-only or
 891   // write-only).
 892   for (unsigned i = 0; i < NumInstMappings; ++i) {
 893     if (InstMappings[i].isValueEqual(Bits, FeatureBits)) {
 894       return InstMappings[i].Name;
 895     }
 896   }
 897
 898   assert(Bits < 0x10000);
 899   uint32_t Op0 = (Bits >> 14) & 0x3;
 900   uint32_t Op1 = (Bits >> 11) & 0x7;
 901   uint32_t CRn = (Bits >> 7) & 0xf;
 902   uint32_t CRm = (Bits >> 3) & 0xf;
 903   uint32_t Op2 = Bits & 0x7;
 904
 905   return "s" + utostr(Op0)+ "_" + utostr(Op1) + "_c" + utostr(CRn)
 906                + "_c" + utostr(CRm) + "_" + utostr(Op2);
 907 }
 908
 909 const AArch64NamedImmMapper::Mapping AArch64TLBI::TLBIMapper::TLBIMappings[] = {
 910   {"ipas2e1is", IPAS2E1IS, {}},
 911   {"ipas2le1is", IPAS2LE1IS, {}},
 912   {"vmalle1is", VMALLE1IS, {}},
 913   {"alle2is", ALLE2IS, {}},
 914   {"alle3is", ALLE3IS, {}},
 915   {"vae1is", VAE1IS, {}},
 916   {"vae2is", VAE2IS, {}},
 917   {"vae3is", VAE3IS, {}},
 918   {"aside1is", ASIDE1IS, {}},
 919   {"vaae1is", VAAE1IS, {}},
 920   {"alle1is", ALLE1IS, {}},
 921   {"vale1is", VALE1IS, {}},
 922   {"vale2is", VALE2IS, {}},
 923   {"vale3is", VALE3IS, {}},
 924   {"vmalls12e1is", VMALLS12E1IS, {}},
 925   {"vaale1is", VAALE1IS, {}},
 926   {"ipas2e1", IPAS2E1, {}},
 927   {"ipas2le1", IPAS2LE1, {}},
 928   {"vmalle1", VMALLE1, {}},
 929   {"alle2", ALLE2, {}},
 930   {"alle3", ALLE3, {}},
 931   {"vae1", VAE1, {}},
 932   {"vae2", VAE2, {}},
 933   {"vae3", VAE3, {}},
 934   {"aside1", ASIDE1, {}},
 935   {"vaae1", VAAE1, {}},
 936   {"alle1", ALLE1, {}},
 937   {"vale1", VALE1, {}},
 938   {"vale2", VALE2, {}},
 939   {"vale3", VALE3, {}},
 940   {"vmalls12e1", VMALLS12E1, {}},
 941   {"vaale1", VAALE1, {}}
 942 };
 943
 944 AArch64TLBI::TLBIMapper::TLBIMapper()
 945   : AArch64NamedImmMapper(TLBIMappings, 0) {}