lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp

   1 //===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions ---*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file provides AArch64 specific target descriptions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "AArch64MCTargetDesc.h"
  15 #include "AArch64ELFStreamer.h"
  16 #include "AArch64MCAsmInfo.h"
  17 #include "InstPrinter/AArch64InstPrinter.h"
  18 #include "llvm/MC/MCCodeGenInfo.h"
  19 #include "llvm/MC/MCInstrInfo.h"
  20 #include "llvm/MC/MCRegisterInfo.h"
  21 #include "llvm/MC/MCStreamer.h"
  22 #include "llvm/MC/MCSubtargetInfo.h"
  23 #include "llvm/Support/ErrorHandling.h"
  24 #include "llvm/Support/TargetRegistry.h"
  25
  26 using namespace llvm;
  27
  28 #define GET_INSTRINFO_MC_DESC
  29 #include "AArch64GenInstrInfo.inc"
  30
  31 #define GET_SUBTARGETINFO_MC_DESC
  32 #include "AArch64GenSubtargetInfo.inc"
  33
  34 #define GET_REGINFO_MC_DESC
  35 #include "AArch64GenRegisterInfo.inc"
  36
  37 static MCInstrInfo *createAArch64MCInstrInfo() {
  38   MCInstrInfo *X = new MCInstrInfo();
  39   InitAArch64MCInstrInfo(X);
  40   return X;
  41 }
  42
  43 static MCSubtargetInfo *createAArch64MCSubtargetInfo(const TargetTuple &TT,
  44                                                      StringRef CPU,
  45                                                      StringRef FS) {
  46   if (CPU.empty())
  47     CPU = "generic";
  48
  49   return createAArch64MCSubtargetInfoImpl(TT, CPU, FS);
  50 }
  51
  52 static MCRegisterInfo *createAArch64MCRegisterInfo(const TargetTuple &TT) {
  53   MCRegisterInfo *X = new MCRegisterInfo();
  54   InitAArch64MCRegisterInfo(X, AArch64::LR);
  55   return X;
  56 }
  57
  58 static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI,
  59                                          const TargetTuple &TT) {
  60   MCAsmInfo *MAI;
  61   if (TT.isOSBinFormatMachO())
  62     MAI = new AArch64MCAsmInfoDarwin();
  63   else {
  64     assert(TT.isOSBinFormatELF() && "Only expect Darwin or ELF");
  65     MAI = new AArch64MCAsmInfoELF(TT);
  66   }
  67
  68   // Initial state of the frame pointer is SP.
  69   unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true);
  70   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0);
  71   MAI->addInitialFrameState(Inst);
  72
  73   return MAI;
  74 }
  75
  76 static MCCodeGenInfo *createAArch64MCCodeGenInfo(const TargetTuple &TT,
  77                                                  Reloc::Model RM,
  78                                                  CodeModel::Model CM,
  79                                                  CodeGenOpt::Level OL) {
  80   assert((TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()) &&
  81          "Only expect Darwin and ELF targets");
  82
  83   if (CM == CodeModel::Default)
  84     CM = CodeModel::Small;
  85   // The default MCJIT memory managers make no guarantees about where they can
  86   // find an executable page; JITed code needs to be able to refer to globals
  87   // no matter how far away they are.
  88   else if (CM == CodeModel::JITDefault)
  89     CM = CodeModel::Large;
  90   else if (CM != CodeModel::Small && CM != CodeModel::Large)
  91     report_fatal_error(
  92         "Only small and large code models are allowed on AArch64");
  93
  94   // AArch64 Darwin is always PIC.
  95   if (TT.isOSDarwin())
  96     RM = Reloc::PIC_;
  97   // On ELF platforms the default static relocation model has a smart enough
  98   // linker to cope with referencing external symbols defined in a shared
  99   // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
 100   else if (RM == Reloc::Default || RM == Reloc::DynamicNoPIC)
 101     RM = Reloc::Static;
 102
 103   MCCodeGenInfo *X = new MCCodeGenInfo();
 104   X->initMCCodeGenInfo(RM, CM, OL);
 105   return X;
 106 }
 107
 108 static MCInstPrinter *createAArch64MCInstPrinter(const TargetTuple &TT,
 109                                                  unsigned SyntaxVariant,
 110                                                  const MCAsmInfo &MAI,
 111                                                  const MCInstrInfo &MII,
 112                                                  const MCRegisterInfo &MRI) {
 113   if (SyntaxVariant == 0)
 114     return new AArch64InstPrinter(MAI, MII, MRI);
 115   if (SyntaxVariant == 1)
 116     return new AArch64AppleInstPrinter(MAI, MII, MRI);
 117
 118   return nullptr;
 119 }
 120
 121 static MCStreamer *createELFStreamer(const TargetTuple &TT, MCContext &Ctx,
 122                                      MCAsmBackend &TAB, raw_pwrite_stream &OS,
 123                                      MCCodeEmitter *Emitter, bool RelaxAll) {
 124   return createAArch64ELFStreamer(Ctx, TAB, OS, Emitter, RelaxAll);
 125 }
 126
 127 static MCStreamer *createMachOStreamer(MCContext &Ctx, MCAsmBackend &TAB,
 128                                        raw_pwrite_stream &OS,
 129                                        MCCodeEmitter *Emitter, bool RelaxAll,
 130                                        bool DWARFMustBeAtTheEnd) {
 131   return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll,
 132                              DWARFMustBeAtTheEnd,
 133                              /*LabelSections*/ true);
 134 }
 135
 136 // Force static initialization.
 137 extern "C" void LLVMInitializeAArch64TargetMC() {
 138   for (Target *T :
 139        {&TheAArch64leTarget, &TheAArch64beTarget, &TheARM64Target}) {
 140     // Register the MC asm info.
 141     RegisterMCAsmInfoFn X(*T, createAArch64MCAsmInfo);
 142
 143     // Register the MC codegen info.
 144     TargetRegistry::RegisterMCCodeGenInfo(*T, createAArch64MCCodeGenInfo);
 145
 146     // Register the MC instruction info.
 147     TargetRegistry::RegisterMCInstrInfo(*T, createAArch64MCInstrInfo);
 148
 149     // Register the MC register info.
 150     TargetRegistry::RegisterMCRegInfo(*T, createAArch64MCRegisterInfo);
 151
 152     // Register the MC subtarget info.
 153     TargetRegistry::RegisterMCSubtargetInfo(*T, createAArch64MCSubtargetInfo);
 154
 155     // Register the MC Code Emitter
 156     TargetRegistry::RegisterMCCodeEmitter(*T, createAArch64MCCodeEmitter);
 157
 158     // Register the obj streamers.
 159     TargetRegistry::RegisterELFStreamer(*T, createELFStreamer);
 160     TargetRegistry::RegisterMachOStreamer(*T, createMachOStreamer);
 161
 162     // Register the obj target streamer.
 163     TargetRegistry::RegisterObjectTargetStreamer(
 164         *T, createAArch64ObjectTargetStreamer);
 165
 166     // Register the asm streamer.
 167     TargetRegistry::RegisterAsmTargetStreamer(*T,
 168                                               createAArch64AsmTargetStreamer);
 169     // Register the MCInstPrinter.
 170     TargetRegistry::RegisterMCInstPrinter(*T, createAArch64MCInstPrinter);
 171   }
 172
 173   // Register the asm backend.
 174   for (Target *T : {&TheAArch64leTarget, &TheARM64Target})
 175     TargetRegistry::RegisterMCAsmBackend(*T, createAArch64leAsmBackend);
 176   TargetRegistry::RegisterMCAsmBackend(TheAArch64beTarget,
 177                                        createAArch64beAsmBackend);
 178 }