1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 #include "AArch64TargetMachine.h"
15 #include "llvm/CodeGen/Passes.h"
16 #include "llvm/CodeGen/RegAllocRegistry.h"
17 #include "llvm/PassManager.h"
18 #include "llvm/Support/CommandLine.h"
19 #include "llvm/Support/TargetRegistry.h"
20 #include "llvm/Target/TargetOptions.h"
21 #include "llvm/Transforms/Scalar.h"
25 EnableCCMP("aarch64-ccmp", cl::desc("Enable the CCMP formation pass"),
26 cl::init(true), cl::Hidden);
28 static cl::opt<bool> EnableMCR("aarch64-mcr",
29 cl::desc("Enable the machine combiner pass"),
30 cl::init(true), cl::Hidden);
33 EnableStPairSuppress("aarch64-stp-suppress", cl::desc("Suppress STP for AArch64"),
34 cl::init(true), cl::Hidden);
37 EnableAdvSIMDScalar("aarch64-simd-scalar", cl::desc("Enable use of AdvSIMD scalar"
38 " integer instructions"), cl::init(false), cl::Hidden);
41 EnablePromoteConstant("aarch64-promote-const", cl::desc("Enable the promote "
42 "constant pass"), cl::init(true), cl::Hidden);
45 EnableCollectLOH("aarch64-collect-loh", cl::desc("Enable the pass that emits the"
46 " linker optimization hints (LOH)"), cl::init(true),
50 EnableDeadRegisterElimination("aarch64-dead-def-elimination", cl::Hidden,
51 cl::desc("Enable the pass that removes dead"
52 " definitons and replaces stores to"
53 " them with stores to the zero"
58 EnableLoadStoreOpt("aarch64-load-store-opt", cl::desc("Enable the load/store pair"
59 " optimization pass"), cl::init(true), cl::Hidden);
62 EnableAtomicTidy("aarch64-atomic-cfg-tidy", cl::Hidden,
63 cl::desc("Run SimplifyCFG after expanding atomic operations"
64 " to make use of cmpxchg flow-based information"),
68 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
69 cl::desc("Run early if-conversion"),
73 EnableCondOpt("aarch64-condopt",
74 cl::desc("Enable the condition optimizer pass"),
75 cl::init(true), cl::Hidden);
78 EnablePBQP("aarch64-pbqp", cl::Hidden,
79 cl::desc("Use PBQP register allocator (experimental)"),
82 extern "C" void LLVMInitializeAArch64Target() {
83 // Register the target.
84 RegisterTargetMachine<AArch64leTargetMachine> X(TheAArch64leTarget);
85 RegisterTargetMachine<AArch64beTargetMachine> Y(TheAArch64beTarget);
86 RegisterTargetMachine<AArch64leTargetMachine> Z(TheARM64Target);
89 /// TargetMachine ctor - Create an AArch64 architecture model.
91 AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
92 StringRef CPU, StringRef FS,
93 const TargetOptions &Options,
94 Reloc::Model RM, CodeModel::Model CM,
97 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
98 Subtarget(TT, CPU, FS, *this, LittleEndian),
102 if (EnablePBQP && Subtarget.isCortexA57() && OL != CodeGenOpt::None) {
104 RegisterRegAlloc::setDefault(createAArch64A57PBQPRegAlloc);
108 void AArch64leTargetMachine::anchor() { }
110 AArch64leTargetMachine::
111 AArch64leTargetMachine(const Target &T, StringRef TT,
112 StringRef CPU, StringRef FS, const TargetOptions &Options,
113 Reloc::Model RM, CodeModel::Model CM,
114 CodeGenOpt::Level OL)
115 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
117 void AArch64beTargetMachine::anchor() { }
119 AArch64beTargetMachine::
120 AArch64beTargetMachine(const Target &T, StringRef TT,
121 StringRef CPU, StringRef FS, const TargetOptions &Options,
122 Reloc::Model RM, CodeModel::Model CM,
123 CodeGenOpt::Level OL)
124 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
127 /// AArch64 Code Generator Pass Configuration Options.
128 class AArch64PassConfig : public TargetPassConfig {
130 AArch64PassConfig(AArch64TargetMachine *TM, PassManagerBase &PM)
131 : TargetPassConfig(TM, PM) {
132 substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
135 AArch64TargetMachine &getAArch64TargetMachine() const {
136 return getTM<AArch64TargetMachine>();
139 void addIRPasses() override;
140 bool addPreISel() override;
141 bool addInstSelector() override;
142 bool addILPOpts() override;
143 bool addPreRegAlloc() override;
144 bool addPostRegAlloc() override;
145 bool addPreSched2() override;
146 bool addPreEmitPass() override;
150 void AArch64TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
151 // Add first the target-independent BasicTTI pass, then our AArch64 pass. This
152 // allows the AArch64 pass to delegate to the target independent layer when
154 PM.add(createBasicTargetTransformInfoPass(this));
155 PM.add(createAArch64TargetTransformInfoPass(this));
158 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
159 return new AArch64PassConfig(this, PM);
162 void AArch64PassConfig::addIRPasses() {
163 // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
165 addPass(createAtomicExpandPass(TM));
167 // Cmpxchg instructions are often used with a subsequent comparison to
168 // determine whether it succeeded. We can exploit existing control-flow in
169 // ldrex/strex loops to simplify this, but it needs tidying up.
170 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
171 addPass(createCFGSimplificationPass());
173 TargetPassConfig::addIRPasses();
176 // Pass Pipeline Configuration
177 bool AArch64PassConfig::addPreISel() {
178 // Run promote constant before global merge, so that the promoted constants
179 // get a chance to be merged
180 if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
181 addPass(createAArch64PromoteConstantPass());
182 if (TM->getOptLevel() != CodeGenOpt::None)
183 addPass(createGlobalMergePass(TM));
184 if (TM->getOptLevel() != CodeGenOpt::None)
185 addPass(createAArch64AddressTypePromotionPass());
190 bool AArch64PassConfig::addInstSelector() {
191 addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
193 // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
194 // references to _TLS_MODULE_BASE_ as possible.
195 if (TM->getSubtarget<AArch64Subtarget>().isTargetELF() &&
196 getOptLevel() != CodeGenOpt::None)
197 addPass(createAArch64CleanupLocalDynamicTLSPass());
202 bool AArch64PassConfig::addILPOpts() {
204 addPass(createAArch64ConditionOptimizerPass());
206 addPass(createAArch64ConditionalCompares());
208 addPass(&MachineCombinerID);
209 if (EnableEarlyIfConversion)
210 addPass(&EarlyIfConverterID);
211 if (EnableStPairSuppress)
212 addPass(createAArch64StorePairSuppressPass());
216 bool AArch64PassConfig::addPreRegAlloc() {
217 // Use AdvSIMD scalar instructions whenever profitable.
218 if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
219 addPass(createAArch64AdvSIMDScalar());
220 // The AdvSIMD pass may produce copies that can be rewritten to
221 // be register coaleascer friendly.
222 addPass(&PeepholeOptimizerID);
227 bool AArch64PassConfig::addPostRegAlloc() {
228 // Change dead register definitions to refer to the zero register.
229 if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
230 addPass(createAArch64DeadRegisterDefinitions());
231 if (TM->getOptLevel() != CodeGenOpt::None &&
232 TM->getSubtarget<AArch64Subtarget>().isCortexA57() &&
233 !static_cast<const AArch64TargetMachine *>(TM)->isPBQPUsed())
234 // Improve performance for some FP/SIMD code for A57.
235 addPass(createAArch64A57FPLoadBalancing());
239 bool AArch64PassConfig::addPreSched2() {
240 // Expand some pseudo instructions to allow proper scheduling.
241 addPass(createAArch64ExpandPseudoPass());
242 // Use load/store pair instructions when possible.
243 if (TM->getOptLevel() != CodeGenOpt::None && EnableLoadStoreOpt)
244 addPass(createAArch64LoadStoreOptimizationPass());
248 bool AArch64PassConfig::addPreEmitPass() {
249 // Relax conditional branch instructions if they're otherwise out of
250 // range of their destination.
251 addPass(createAArch64BranchRelaxation());
252 if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
253 TM->getSubtarget<AArch64Subtarget>().isTargetMachO())
254 addPass(createAArch64CollectLOHPass());