1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 #include "AArch64TargetMachine.h"
15 #include "llvm/PassManager.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/Support/CommandLine.h"
18 #include "llvm/Support/TargetRegistry.h"
19 #include "llvm/Target/TargetOptions.h"
20 #include "llvm/Transforms/Scalar.h"
24 EnableCCMP("aarch64-ccmp", cl::desc("Enable the CCMP formation pass"),
25 cl::init(true), cl::Hidden);
28 EnableStPairSuppress("aarch64-stp-suppress", cl::desc("Suppress STP for AArch64"),
29 cl::init(true), cl::Hidden);
32 EnableAdvSIMDScalar("aarch64-simd-scalar", cl::desc("Enable use of AdvSIMD scalar"
33 " integer instructions"), cl::init(false), cl::Hidden);
36 EnablePromoteConstant("aarch64-promote-const", cl::desc("Enable the promote "
37 "constant pass"), cl::init(true), cl::Hidden);
40 EnableCollectLOH("aarch64-collect-loh", cl::desc("Enable the pass that emits the"
41 " linker optimization hints (LOH)"), cl::init(true),
45 EnableDeadRegisterElimination("aarch64-dead-def-elimination", cl::Hidden,
46 cl::desc("Enable the pass that removes dead"
47 " definitons and replaces stores to"
48 " them with stores to the zero"
53 EnableLoadStoreOpt("aarch64-load-store-opt", cl::desc("Enable the load/store pair"
54 " optimization pass"), cl::init(true), cl::Hidden);
57 EnableAtomicTidy("aarch64-atomic-cfg-tidy", cl::Hidden,
58 cl::desc("Run SimplifyCFG after expanding atomic operations"
59 " to make use of cmpxchg flow-based information"),
62 extern "C" void LLVMInitializeAArch64Target() {
63 // Register the target.
64 RegisterTargetMachine<AArch64leTargetMachine> X(TheAArch64leTarget);
65 RegisterTargetMachine<AArch64beTargetMachine> Y(TheAArch64beTarget);
67 RegisterTargetMachine<AArch64leTargetMachine> Z(TheARM64leTarget);
68 RegisterTargetMachine<AArch64beTargetMachine> W(TheARM64beTarget);
71 /// TargetMachine ctor - Create an AArch64 architecture model.
73 AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
74 StringRef CPU, StringRef FS,
75 const TargetOptions &Options,
76 Reloc::Model RM, CodeModel::Model CM,
79 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
80 Subtarget(TT, CPU, FS, LittleEndian),
81 InstrInfo(Subtarget), TLInfo(*this) {
85 void AArch64leTargetMachine::anchor() { }
87 AArch64leTargetMachine::
88 AArch64leTargetMachine(const Target &T, StringRef TT,
89 StringRef CPU, StringRef FS, const TargetOptions &Options,
90 Reloc::Model RM, CodeModel::Model CM,
92 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
94 void AArch64beTargetMachine::anchor() { }
96 AArch64beTargetMachine::
97 AArch64beTargetMachine(const Target &T, StringRef TT,
98 StringRef CPU, StringRef FS, const TargetOptions &Options,
99 Reloc::Model RM, CodeModel::Model CM,
100 CodeGenOpt::Level OL)
101 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
104 /// AArch64 Code Generator Pass Configuration Options.
105 class AArch64PassConfig : public TargetPassConfig {
107 AArch64PassConfig(AArch64TargetMachine *TM, PassManagerBase &PM)
108 : TargetPassConfig(TM, PM) {}
110 AArch64TargetMachine &getAArch64TargetMachine() const {
111 return getTM<AArch64TargetMachine>();
114 void addIRPasses() override;
115 bool addPreISel() override;
116 bool addInstSelector() override;
117 bool addILPOpts() override;
118 bool addPreRegAlloc() override;
119 bool addPostRegAlloc() override;
120 bool addPreSched2() override;
121 bool addPreEmitPass() override;
125 void AArch64TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
126 // Add first the target-independent BasicTTI pass, then our AArch64 pass. This
127 // allows the AArch64 pass to delegate to the target independent layer when
129 PM.add(createBasicTargetTransformInfoPass(this));
130 PM.add(createAArch64TargetTransformInfoPass(this));
133 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
134 return new AArch64PassConfig(this, PM);
137 void AArch64PassConfig::addIRPasses() {
138 // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
140 addPass(createAtomicExpandLoadLinkedPass(TM));
142 // Cmpxchg instructions are often used with a subsequent comparison to
143 // determine whether it succeeded. We can exploit existing control-flow in
144 // ldrex/strex loops to simplify this, but it needs tidying up.
145 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
146 addPass(createCFGSimplificationPass());
148 TargetPassConfig::addIRPasses();
151 // Pass Pipeline Configuration
152 bool AArch64PassConfig::addPreISel() {
153 // Run promote constant before global merge, so that the promoted constants
154 // get a chance to be merged
155 if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
156 addPass(createAArch64PromoteConstantPass());
157 if (TM->getOptLevel() != CodeGenOpt::None)
158 addPass(createGlobalMergePass(TM));
159 if (TM->getOptLevel() != CodeGenOpt::None)
160 addPass(createAArch64AddressTypePromotionPass());
165 bool AArch64PassConfig::addInstSelector() {
166 addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
168 // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
169 // references to _TLS_MODULE_BASE_ as possible.
170 if (TM->getSubtarget<AArch64Subtarget>().isTargetELF() &&
171 getOptLevel() != CodeGenOpt::None)
172 addPass(createAArch64CleanupLocalDynamicTLSPass());
177 bool AArch64PassConfig::addILPOpts() {
179 addPass(createAArch64ConditionalCompares());
180 addPass(&EarlyIfConverterID);
181 if (EnableStPairSuppress)
182 addPass(createAArch64StorePairSuppressPass());
186 bool AArch64PassConfig::addPreRegAlloc() {
187 // Use AdvSIMD scalar instructions whenever profitable.
188 if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar)
189 addPass(createAArch64AdvSIMDScalar());
193 bool AArch64PassConfig::addPostRegAlloc() {
194 // Change dead register definitions to refer to the zero register.
195 if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
196 addPass(createAArch64DeadRegisterDefinitions());
200 bool AArch64PassConfig::addPreSched2() {
201 // Expand some pseudo instructions to allow proper scheduling.
202 addPass(createAArch64ExpandPseudoPass());
203 // Use load/store pair instructions when possible.
204 if (TM->getOptLevel() != CodeGenOpt::None && EnableLoadStoreOpt)
205 addPass(createAArch64LoadStoreOptimizationPass());
209 bool AArch64PassConfig::addPreEmitPass() {
210 // Relax conditional branch instructions if they're otherwise out of
211 // range of their destination.
212 addPass(createAArch64BranchRelaxation());
213 if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
214 TM->getSubtarget<AArch64Subtarget>().isTargetMachO())
215 addPass(createAArch64CollectLOHPass());